Can't use type as a selected name

Prior to VHDL-2002 (I think), if you have a record type and you refer to an attribute of a member of that record, the code would compile fine with Modelsim. After that time, Modelsim flags that usage as a warning, but GHDL flags it as an error. Technically, GHDL may be performing per the LRM, but the issue is that legacy code written in this way, which used to be legal, is now left with no viable workaround.

type t_Some_Record is record
My_Data: std_ulogic_vector(7 downto 0);
...
end record t_Some_Record;

In an entity that processes the data you might have the following listed as a port signal listed like this:
Some_Out: out std_ulogic_vector( t_Some_Record.My_Data'length - 1 downto 0);

Without declaring some form of dummy constant/signal/variable, there is no clean work around that doesn't involve a lot of code changes. Allowing the GHDL user to control this behavior (i.e. an error or a warning) might be something to consider addingas a feature.

Kevin Jennings