improve power board (2026-1-16)
add top level link to UI-Pinning
fix link
improve NeoPixel sequence names
Add main power bus board with crank.
Holes for Logistics board from M2 to M3, moved holes away from connectors and tracks
Rename old Kurbel
added wiring help board
solder jumpers for field LED sequence
update website for second prototype
move connection of wires further down in order to deconflict against the board that sits on the block board.
fix inverted direction error indicator and make it purple
remove obsolete #include "GeneralIo.h"
add log output
adapt 2gl pin usage to new boards
IIC out, replace GeneralIo by NeoPixelRgbw
fix typo
Fixed blue inversion
On this branch I want to fix the blue TSp inversion
add branches
Haltmelder
vor Cloppenburg
relais to pin 17
finish business logic
FestlegeMelder works
make HardwareTest compile again
Glass für Anschalter und TSp
Tsp Melder holes and board attachment
boxes in schematic, another dimension in pcb, time stamp
fix leg, merge bodies
Kontur für Störmelder verbessert, passt jetzt
bk_ui_boards
first prototype
Fix link: Gleisschaltmittel
Front screw hole(s) added
Fix position of Str1 LED, was 0.1mm to far left, aligned with other LEDs in first prototype
Hinterseite wieder flach, Schraublöcher von hinten
FHT
change Felderblock from PCA9685 to NeoPixel
add measurements in PCB, tweak lables in schematic
tweak yellow
move or delete now unused test code and obsolete constant pin definition
disable DEBUG_SPEED
reenable interrupts in first seven bit times of a byte in the low phase
remove obsolete GeneralIo.*
fix inverted "Blaue TSp", disable interrupts during transfer (will be reenabled in specific parts of the transfer)
sendByte() all assembler
in the process of replacing IIC powered IO and Servos with NeoPixels
wildly refactor NeoPixelRgbw
make GetPort() and WireSpec2Bit() public and the other lookup functions inline
split model in half in order to derive Tastensperren and Festleger from same base body
updated footprints during jlcpcb order
Put title into silkscreen
put logo and holes into schematic, add Hole4, move vias off pads
Spare LED added
Haltmelder angepasst
bevore slimmer boards
Tastensperren innen hohl, Schraublöcher angepasst, Haltmelderplatform
Thick back
Switch holes all green
Completely redesigned switch holes to be open in Y direction instead of -Z
before rework of BasePlatebody
Nicer leg for table
UpperAssemblyY is new depth of key locks and table
Undo Anschalterzaehler, add support for PE0 deciding local ESig GO state transmitted, remove debouncing obsolete buttons
copy regular Tf71 over Tf71_Pabst, but including Anschalter-Counter, custom EndFeld.c removed
reworked transmitting our local ESig state; direct LN support removed, deciding GO_40 vs GO by digital input instead
Operate Anschalter counter at PORTA.7
Call BlockPacketSendBauart() from LogicMainTransmitState()
add BlockPacketBauart to makefile, remove LN from sysdef.h
Fix parameter use in call to BlockPacketReceiveBauart(channel)
almost complete, separable single boards, testable in one piece
rename
rename
rename
rename ...UI to ...UI_TSp
first working smoke test
https://github.com/bigjosh/SimpleNeoPixelDemo/blob/master/SimpleNeopixelDemo/SimpleNeopixelDemo.ino
Label pins of J1 on silkscreen
first manufacturing
add tags
rename J1, some output settings
only frontside board, rigit
plotsettings
move Felderblock_UI files to trunk
add tags
add trunk
name User.2 as "Stiffener" and put text into that layer
final b
fixed Haltmelder in schematic (was lost???), finished holes, repositioned some capcitors
Place Holes
Add neoPixel for Haltmelder, restructure flex around Haltmelder
Haltmelder
changes 2024-05-18
finally adapt control panel to fixed state message of block post
ANSM/STR swapped
routed, filled