Activity for FREMO Streckenblock
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Stefan Bormann committed [r1225] on Svn
improve power board (2026-1-16)
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add top level link to UI-Pinning
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fix link
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improve NeoPixel sequence names
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FREMO Streckenblock released /TF71/TF71_2024-09-10.hex
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Add main power bus board with crank.
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Holes for Logistics board from M2 to M3, moved holes away from connectors and tracks
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Rename old Kurbel
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added wiring help board
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solder jumpers for field LED sequence
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update website for second prototype
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move connection of wires further down in order to deconflict against the board that sits on the block board.
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fix inverted direction error indicator and make it purple
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remove obsolete #include "GeneralIo.h"
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add log output
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adapt 2gl pin usage to new boards
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IIC out, replace GeneralIo by NeoPixelRgbw
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fix typo
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Fixed blue inversion
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On this branch I want to fix the blue TSp inversion
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add branches
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Haltmelder
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vor Cloppenburg
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relais to pin 17
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finish business logic
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FestlegeMelder works
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make HardwareTest compile again
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Glass für Anschalter und TSp
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Tsp Melder holes and board attachment
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boxes in schematic, another dimension in pcb, time stamp
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fix leg, merge bodies
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Kontur für Störmelder verbessert, passt jetzt
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bk_ui_boards
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first prototype
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Fix link: Gleisschaltmittel
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Front screw hole(s) added
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Fix position of Str1 LED, was 0.1mm to far left, aligned with other LEDs in first prototype
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Hinterseite wieder flach, Schraublöcher von hinten
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FHT
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change Felderblock from PCA9685 to NeoPixel
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add measurements in PCB, tweak lables in schematic
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tweak yellow
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move or delete now unused test code and obsolete constant pin definition
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disable DEBUG_SPEED
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reenable interrupts in first seven bit times of a byte in the low phase
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remove obsolete GeneralIo.*
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fix inverted "Blaue TSp", disable interrupts during transfer (will be reenabled in specific parts of the transfer)
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sendByte() all assembler
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in the process of replacing IIC powered IO and Servos with NeoPixels
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wildly refactor NeoPixelRgbw
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make GetPort() and WireSpec2Bit() public and the other lookup functions inline
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split model in half in order to derive Tastensperren and Festleger from same base body
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updated footprints during jlcpcb order
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Put title into silkscreen
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put logo and holes into schematic, add Hole4, move vias off pads
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Spare LED added
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Haltmelder angepasst
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bevore slimmer boards
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Tastensperren innen hohl, Schraublöcher angepasst, Haltmelderplatform
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Thick back
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Switch holes all green
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Completely redesigned switch holes to be open in Y direction instead of -Z
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before rework of BasePlatebody
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Nicer leg for table
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UpperAssemblyY is new depth of key locks and table
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Undo Anschalterzaehler, add support for PE0 deciding local ESig GO state transmitted, remove debouncing obsolete buttons
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copy regular Tf71 over Tf71_Pabst, but including Anschalter-Counter, custom EndFeld.c removed
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reworked transmitting our local ESig state; direct LN support removed, deciding GO_40 vs GO by digital input instead
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Operate Anschalter counter at PORTA.7
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Call BlockPacketSendBauart() from LogicMainTransmitState()
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add BlockPacketBauart to makefile, remove LN from sysdef.h
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Fix parameter use in call to BlockPacketReceiveBauart(channel)
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almost complete, separable single boards, testable in one piece
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rename
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rename
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rename
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rename ...UI to ...UI_TSp
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first working smoke test
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https://github.com/bigjosh/SimpleNeoPixelDemo/blob/master/SimpleNeopixelDemo/SimpleNeopixelDemo.ino
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Label pins of J1 on silkscreen
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first manufacturing
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add tags
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rename J1, some output settings
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only frontside board, rigit
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plotsettings
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move Felderblock_UI files to trunk
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add tags
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add trunk
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name User.2 as "Stiffener" and put text into that layer
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final b
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fixed Haltmelder in schematic (was lost???), finished holes, repositioned some capcitors
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Place Holes
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Add neoPixel for Haltmelder, restructure flex around Haltmelder
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Haltmelder
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changes 2024-05-18
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finally adapt control panel to fixed state message of block post
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ANSM/STR swapped
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routed, filled