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WO2006038991A3 - System, apparatus and method for managing predictions of various access types to a memory associated with cache - Google Patents

System, apparatus and method for managing predictions of various access types to a memory associated with cache Download PDF

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Publication number
WO2006038991A3
WO2006038991A3 PCT/US2005/029135 US2005029135W WO2006038991A3 WO 2006038991 A3 WO2006038991 A3 WO 2006038991A3 US 2005029135 W US2005029135 W US 2005029135W WO 2006038991 A3 WO2006038991 A3 WO 2006038991A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
cache
speculator
program instructions
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/029135
Other languages
French (fr)
Other versions
WO2006038991A2 (en
Inventor
Ziyad S Hakura
Radoslav Danilak
Brad W Simeral
Brian Keith Langendorf
Stefano A Pescador
Dmitry Vyshetsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/920,995 external-priority patent/US7260686B2/en
Priority claimed from US10/920,610 external-priority patent/US7441087B2/en
Priority claimed from US10/920,682 external-priority patent/US7461211B2/en
Priority claimed from US10/921,026 external-priority patent/US7206902B2/en
Application filed by Nvidia Corp filed Critical Nvidia Corp
Priority to CN2005800270828A priority Critical patent/CN101002178B/en
Priority to JP2007527950A priority patent/JP5059609B2/en
Publication of WO2006038991A2 publication Critical patent/WO2006038991A2/en
Publication of WO2006038991A3 publication Critical patent/WO2006038991A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A system, apparatus, and method are disclosed for predicting accesses to memory (112). In one embodiment, an exemplary apparatus comprises a processor (104) configured to execute program instructions and process program data, a memory (112) including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator (108) can comprise a sequential predictor and a nonsequential predictor for generating a configurable number of sequential and nonsequential addresses respectively. In one embodiment, a prefetcher (106) implements the apparatus. In various embodiments, the speculator (108) can also include any of the following: an expediter, a suppressor, an inventory, an inventory filter, a post-inventory filter and a data return cache memory, which can include a short term and a long term cache, among other things.
PCT/US2005/029135 2004-08-17 2005-08-16 System, apparatus and method for managing predictions of various access types to a memory associated with cache Ceased WO2006038991A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2005800270828A CN101002178B (en) 2004-08-17 2005-08-16 Prefetcher for predictive access to various types of memory
JP2007527950A JP5059609B2 (en) 2004-08-17 2005-08-16 System, apparatus, and method for predicting various types of access to memory and for managing predictions associated with cache memory

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US10/920,995 US7260686B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory
US10/921,026 2004-08-17
US10/920,610 US7441087B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for issuing predictions from an inventory to access a memory
US10/920,682 US7461211B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for generating nonsequential predictions to access a memory
US10/920,682 2004-08-17
US10/920,610 2004-08-17
US10/920,995 2004-08-17
US10/921,026 US7206902B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for predicting accesses to a memory

Publications (2)

Publication Number Publication Date
WO2006038991A2 WO2006038991A2 (en) 2006-04-13
WO2006038991A3 true WO2006038991A3 (en) 2006-08-03

Family

ID=36142947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/029135 Ceased WO2006038991A2 (en) 2004-08-17 2005-08-16 System, apparatus and method for managing predictions of various access types to a memory associated with cache

Country Status (4)

Country Link
JP (1) JP5059609B2 (en)
KR (1) KR100987832B1 (en)
TW (1) TWI348097B (en)
WO (1) WO2006038991A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7636813B2 (en) * 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
JP6252348B2 (en) * 2014-05-14 2017-12-27 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
EP3049915B1 (en) * 2014-12-14 2020-02-12 VIA Alliance Semiconductor Co., Ltd. Prefetching with level of aggressiveness based on effectiveness by memory access type
EP3129887B1 (en) 2014-12-14 2018-08-15 VIA Alliance Semiconductor Co., Ltd. Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
JP2017072929A (en) 2015-10-06 2017-04-13 富士通株式会社 Data management program, data management apparatus, and data management method
US10509726B2 (en) * 2015-12-20 2019-12-17 Intel Corporation Instructions and logic for load-indices-and-prefetch-scatters operations
US20170177349A1 (en) * 2015-12-21 2017-06-22 Intel Corporation Instructions and Logic for Load-Indices-and-Prefetch-Gathers Operations
KR102696971B1 (en) * 2016-09-06 2024-08-21 삼성전자주식회사 Storage device including nonvolatile memory device and access method for nonvolatile memory device
US10579531B2 (en) * 2017-08-30 2020-03-03 Oracle International Corporation Multi-line data prefetching using dynamic prefetch depth
US11281589B2 (en) * 2018-08-30 2022-03-22 Micron Technology, Inc. Asynchronous forward caching memory systems and methods
KR102142498B1 (en) * 2018-10-05 2020-08-10 성균관대학교산학협력단 GPU memory controller for GPU prefetching through static analysis and method of control
KR102238383B1 (en) * 2019-10-30 2021-04-09 주식회사 엠투아이코퍼레이션 HMI having optimization function of communication
KR20210077923A (en) * 2019-12-18 2021-06-28 에스케이하이닉스 주식회사 Data processing system using artificial intelligence for managing power consumption
US11816034B2 (en) * 2020-10-26 2023-11-14 International Business Machines Corporation Fast cache tracking to support aggressive prefetching

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US6789171B2 (en) * 2002-05-31 2004-09-07 Veritas Operating Corporation Computer system implementing a multi-threaded stride prediction read ahead algorithm

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103169A (en) * 1992-09-18 1994-04-15 Nec Corp Read data prefetching mechanism for central arithmetic processor
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor
JP3741945B2 (en) * 1999-09-30 2006-02-01 富士通株式会社 Instruction fetch control device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US6789171B2 (en) * 2002-05-31 2004-09-07 Veritas Operating Corporation Computer system implementing a multi-threaded stride prediction read ahead algorithm

Also Published As

Publication number Publication date
KR100987832B1 (en) 2010-10-13
TWI348097B (en) 2011-09-01
JP5059609B2 (en) 2012-10-24
TW200619937A (en) 2006-06-16
JP2008510258A (en) 2008-04-03
KR20070050443A (en) 2007-05-15
WO2006038991A2 (en) 2006-04-13

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