WO2006008747A2

WO2006008747A2 - On-chip inductor

Info

Publication number: WO2006008747A2
Application number: PCT/IL2005/000781
Authority: WO
Inventors: Amikam Nemirovsky
Original assignee: BlueBird Optical MEMS Ltd
Current assignee: BlueBird Optical MEMS Ltd
Priority date: 2004-07-22
Filing date: 2005-07-21
Publication date: 2006-01-26
Anticipated expiration: 2007-01-22
Also published as: WO2006008747A3

Abstract

An inductor and a respective method of manufacturing for achieving very small integrated on-chip inductors, having high quality factor (Q) values, as well as simple and a single-level geometry. The proposed method is based on completely coating a conductor strip with an electrically highly resistive soft ferromagnetic material having a high permeability. Such a material may be a nano-crystaline material containing Fe-Co-X-N, where X may be, for example, any one of Ta, Cu, Ta-Si, Cu-Si, or Si. Depending on the inductor's linear dimension, coating permeability, electrical resistivity and thickness, Q values of well-over fifty at frequencies of over one giga-Hertz, and inductance values of several tens of nano-Henry per millimeter length of inductor, are achieved.

Description

ON-CHIP INDUCTOR

FIELD OF THE EVVENTION

The present invention relates generally to on-chip inductors and more particularly to on- chip inductors capable of operating at very high frequencies.

BACKGROUND OF THE INVENTION

An inductor is typically produced of a coil and in many occasions is produced around a core made of a high permeability material. The inductor is a passive electrical component that generates between its contacts a voltage that is proportional to the instantaneous rate of change in current flowing between the contacts. An inductor is measured by its inductance value, measured in Henry (H). The current flowing through an inductor produces an electromagnetic field that can be calculated from Maxwell's equations. The inductance of the inductor, usually denoted by an "L" symbol, defines the proportion between the voltage generated in the inductor arid the time derivative of the current, 1, flowing through the inductor.

Another important property of an inductor is its quality factor "Q". The quality factor, Q, of a system, is defined as the maximal energy stored in the system when exited by a pure harmonic input, multiplied by the exiting angular frequency and divided by the average power dissipated in the system. In the case of radio frequency (RF) filters, it is desirable to have a high"Q" factor because it is desirable to lose as little energy as possible in the filter itself. With respect to the filter elements, such as capacitors and inductors for example, a low energy loss implies providing a Q factor as high as possible for each filter element.

With the development of integrated circuits and especially with the capabilities required for high frequency systems, it has become more desirable to be able to integrate passive components, such as inductors, capacitors and resistors, on an integrated chip (IC). This poses new challenges to the chip designers due to the limited space available on an IC and the limitations of the materials and processes used in the designs of such ICs.

Prior art solutions have attempted to find one way or another to imitate the geometrical design of stand-alone inductors for the on-chip inductor. Therefore, in many cases, coil or spiral shapes are used either as two-dimensional planar implementations (2D) or as three- dimensional (3D) implementations.

In a 2D implementation, such as in Fig. 1, an exemplary implementation of a prior art on-chip 2D inductor is shown. A prior art spiral like inductor 100 known in the art is comprised of a conducting strip 110 formed as a coil having 2.5 turns, the conducting strip having a width "W" and a space "S" between turns. Inductor 100 is further comprised of segment 120, where segment 120 is connected- to conducting strip 110 by a "via" hole in the area of overlap 130. Considering segment 120 and the connecting "via", it is obvious that a spiral shaped inductor necessarily implies a three dimensional structure rather than a simpler planar structure, as segment 120 must be electrically isolated from the turns and thus must be implemented in a different layer. In itself, this solution usually leads to inductors having an inductance level in the range of 1- 40 nano-Henry (nH) and a Q-factor, in the GHz frequency range, of the order of five for complementary metal-oxide semiconductor (CMOS) implementations and of the order often for bipolar CMOS (BiCMOS) processes.

Fukuda et al., in their paper "Planar Inductor with Ferrite Layers for DC- DC Converter" suggest a spiral shaped "planar" inductor (a planar spiral indeed, although that together with its electrical connections the whole structure must be implemented as a strictly three dimensional structure, because of reasons explained above). Fukuda et al. suggest to completely coat the spiral structure with bottom and upper layers made of a material containing a ferrite, intended to enhance both Q factor and the inductance L of the inductor. The inductor proposed by Fukuda et al. is intended for implementation of on-chip purposes and for use in the frequency range of up to five mega Hertz. Fukuda et al. were able to show a maximum Q-factor of 40 at that frequency range and have shown it to decrease as frequency was increased above that range.

Another important aspect of on-chip inductors is the inductance per square micron (micrometer) that provides an indication of the efficiency of use of IC area. In the case of Fukuda et al, an efficiency of 0.042* 10^'3 nano-Henry per square micron is achieved.

Another body of prior art solutions suggests a 3D design of a coil inductor, as shown in Fig. 2. Figure 2 is an exemplary implementation of a prior art on-chip 3D inductor. Device 200 comprising an inductor is composed of conducting strips 230 and conducting strips 240 formed, respectively, on surfaces 210 and 220 of device 200. Conducting strips 230 and conducting strips 240 are connected through metal filled "via" holes 250 and together form a 3D structure of a coil, noted above as being typical of an implementation of an inductor. In some cases these inductors are created around a ferromagnetic and electrically non- conductive core, intended to enhance both the inductance L and the Q factor of the inductors.

A notable advantage over the planar spirals is the fact that the 3D inductors save on IC area. However, production of such inductors is very complicated and expensive as compared to strictly planar inductors. 3D design inductors also suffer from a low Q factor and a low inductance level, similar to their 2D inductor counter-parts.

In view of the limitations of prior art solutions, it would be advantageous to provide a solution for the design of a strictly planar inductor that would be implemented, including its electrical contacts, in a single layer.

It would be further advantageous if such an inductor would present a Q-factor in excess of 100 and still further advantageous if the inductance of such an inductor would be in the range of 1 micro-Henry per square millimeter. It would be further advantageous if such an inductor were operable in a high frequency range, for example, over one giga Hertz.

SUMMARY OF THE INVENTION

Accordingly, it is a principal object of the present invention to overcome the disadvantages of prior art techniques used for producing on-chip inductors capable of operating at very high frequencies.

The present invention discloses an improved and efficient inductor and a respective method of manufacturing for achieving very small integrated on-chip inductors, having high quality factor (Q), values, as well as simple and a single-level geometry. In accordance with a preferred embodiment of the present invention, there is provided an inductor integrated onto an integrated circuit (IC), comprising: a first layer of an electrically highly resistive, high permeability soft ferromagnetic material , deposited on a surface of the IC; an electrically conducting strip made of a highly conducting material, the strip formed on top of the first layer and having electrical contacts formed at both ends of the strip, wherein the strip and the contacts are not intersecting or self-intersecting; and a second layer of an electrically highly resistive, high permeability soft ferromagnetic material, deposited over the strip and at least partly over the first layer, such that the strip is entirely covered by a non-conducting and high permeability soft ferromagnetic material, of either the first layer or the second layer.

In accordance with another embodiment of the present invention, the surface of an IC is one of a plurality of layers of the IC.

In accordance with another embodiment of the present invention, a relative permeability of the high permeability soft ferromagnetic material is over 50.

In accordance with yet another embodiment of the present invention, the highly resistive, high permeability soft ferromagnetic material is composed of Fe-Co-X-N wherein X may be any one of: Ta, Cu, Ta-Si, Cu-Si, or Si.

In accordance with yet another embodiment of the present invention, the inductor has a Q-factor of above one hundred.

In accordance with yet another embodiment of the present invention, the electrically highly resistive and high permeability soft ferromagnetic material is composed of materials at least one of which is a ferrite.

. In accordance with yet another embodiment of the present invention, the conducting strip is formed in a planar shape forming one of: a U-shape, a rectangular shape, a meander-shape.

In accordance with yet another embodiment of the present invention, at least a portion of the second layer is removed from over the conducting strip for the purpose of post-processing trimming.

In accordance with yet another embodiment of the present invention, the removal of the portion of the second layer is performed by a laser. In accordance with yet another embodiment of the present invention, the removal of the portion of the second layer is performed symmetrically at the proximities of the electrical contacts.

In accordance with yet another embodiment of the present invention, a thickness of the first layer and the second layer is at least one micrometer.

In accordance with yet another embodiment of the present invention, the thickness of the first layer and the second layer is less than one micrometer.

In accordance with yet another embodiment of the present invention, the conducting strip is made of at least one of: gold, aluminum, copper, platinum.

In accordance with yet another embodiment of the present invention, the electrical contacts are located so as to enable essential nullification of electromagnetic interference to a surrounding.

Additional features and advantages of the invention will become apparent from the following drawings and description.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention with regard to the embodiments thereof, reference is made to the accompanying drawings, in which like numerals designate corresponding elements or sections throughout, and in which:

Fig. 1 is an exemplary implementation of a prior art on-chip 2D inductor;

Fig. 2 is an exemplary implementation of a prior art on-chip 3D inductor;

Fig. 3A is an exemplary linear U-shaped inductor designed in accordance with a first embodiment of the present invention;

Fig. 3B is an exemplary linear square-shaped inductor designed in accordance with a second embodiment of the present invention;

Fig. 4 is a cross-section of the linear square-shaped inductor design of Fig. 3B, in accordance with the present invention;

- D - Fig. 5 is a simulation of the current density in the cross-section of the inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip at a frequency of 0.1 giga Hertz;

Fig. 6 is a simulation of the current density in a cross section of the inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip, at a frequency of 5 giga Hertz;

Fig. 7 is an exemplary meander-shaped inductor designed in accordance with a third embodiment of the present invention; ' _r

Fig. 8 is a cross-section of the meander-shaped inductor design of Fig. 7 in accordance with the present invention;

Fig. 9 is a simulation of the current density in a cross section of the meander-shaped inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip, at a frequency of 2.4 giga Hertz; and

Fig. 10 is an exemplary linear U-shaped inductor with trimming in accordance with a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention overcomes limitations of prior art solutions by providing a high Q value for an on-chip inductor. Providing a high Q factor value is achieved by coating a linear shaped conductor with an electrically highly resistive, soft ferromagnetic material having a high permeability, for example, nano-crysrallines containing Fe-Co-X-N, where X may be, for example, any one of Ta, Cu, Ta-Si, Cu-Si, or Si. The geometrical design of the inductor does not require turns or spirals and can, in fact, assume almost any geometrical form as may be convenient for production or for on-chip layout. These valuable properties of the present invention are due to magnetic flux trapping, thus providing simple strictly single level design implementation having negligible electromagnetic interference levels.

While prior art solutions have focused traditionally on creating coil or spring type inductors, the present invention does not make such a requirement on the design of the inductor. Specifically, the present invention enables the two ends of the conducting strip composing the inductor to be placed close by and in parallel to each other, i.e. at the same layer of the integrated circuit.

Therefore, the preferred embodiments of the present invention allow access to the inductor at the same layer where the inductor is realized. Furthermore, the electromagnetic fields at the exit of the inductor essentially cancel each other, thus significantly reducing the electromagnetic interference caused in prior art implementations, where the entry to the inductor is at a significantly different location than the exit thereof.

The proposed inductor, in accordance with the present invention, posses Q values of well-over fifty, typically having values exceeding one hundred, and an inductance level of over twenty-five nano-Henry per millimeter length, at frequencies of over one giga-Hertz. Moreover, the process used for manufacturing is suitable for post-processing of standard manufacturing technology.

Reference is now made to Fig. 3A, where an exemplary and non-limiting planar inductor having a U-shape, and to Fig. 3B where an exemplary and non-limiting planar inductor having a square-shape, both designed in accordance with a first and a second embodiment of the present invention, are respectively shown. The proposed inductors are implemented on IC 300A and IC 300B, respectively.

A cross-section A-A of the IC, for example IC 300B, is shown in Fig. 4. On top of an IC surface 310 a bottom layer 340-B of electrically highly resistive, soft ferromagnetic material having a high permeability is deposited. A minimal thickness of such a bottom layer 340-B is typically less than one micrometer (micron), but may reach up to several microns. Layer 340-B may be made of, but not limited to, a nano-crystaline material containing Fe-Co- X-N, where X may be, for example, any one of Ta, Cu, Ta-Si, Cu-Si, or Si.

On top of the layer 340-B there is deposited a conducting strip 320. The conducting strip 320 may be formed in a linear shape or in a variety of other shapes, for example a U- shape or a meander shape. The conducting strip has two ends 330 and 335 that form the electrical contacts to other network elements. Conducting strip 320 is formed of a highly conducting material, including but not limited to metals like gold, copper or platinum. The conducting strip is formed by using, for example, patterning techniques (etching, lift-off, molding or other) commonly used in semiconductor manufacturing.

The conducting strip is now coated with a top layer 340-T of an electrically highly resistive, soft ferromagnetic material having a high permeability. The two ferromagnetic layers 340-B and 340-T cover and surround the conducting strip completely. Hence, when the two layers are thick enough, most of the electromagnetic energy associated with an electrical current flowing in the conducting strip 320 is trapped inside layers 340-T and 340-B.

Energy losses in layers 340-B and 340-T depend on the specific electrical conductivities of the materials comprising the two layers. The choice of electrically highly resistive materials is essential for low energy losses.

Layer 340-T may be made of, but is not limited to, nano-crystaline material containing Fe-Co-X-N, where X may be, for example, any one of Ta, Cu, Ta-Si, Cu-Si, or Si. A minimal thickness of such a top layer 340-T is typically one micron or less, and may reach up to several microns.

Ends 330 and 335 may be placed such that the electrical connections of the inductor to other network elements are in proximity and are implemented parallel to each other, thereby ensuring that interference electromagnetic fields caused outside the inductor are essentially nullified.

Using a copper conductor having a cross section of fifteen-by-fifteen micrometers and a two micron thick coating, wherein the two micron thick coating is made of a soli ferromagnetic material having a relative permeability of 600 and a specific electrical resistivity of 10 ohm-cm, results in a Q-factor exceeding four hundred, at 1.842 giga Hertz (1,842 mega Hertz). This is due to the magnetic flux trapping that takes place in coating layers 340-B and 340-T, completely coating conducting strip 320.

Furthermore, high inductance values are achieved due to the magnetic flux density amplification in the ferromagnetic coating of layers 340-B and 340-T. The trapping phenomena are shown in Figs. 5 and 6, where an enlargement of the ferromagnetic coating and the conducting strip cross-sections are shown.

Fig. 5 is a simulation of the current density in the cross-section of the inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip, at driving frequency of 0.1 giga Hertz. For this driving frequency the current density is practically uniform over the cross section of conducting strip 320. The magnetic flux lines, lying in planes in a locally lateral manner to the conductor, are essentially trapped in the volume of the ferromagnetic coating surrounding the conducting strip. As a result, the effects discussed above are obtained.

Fig. 6 is a simulation of the current density in a cross section of the inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip, at a driving frequency of 5 giga Hertz. At this driving frequency the current density is significantly higher at the outer sharp edges of the conducting strip than at the vicinity of the center of the conducting strip cross section (this is known as "skin effect"). Yet, the essential trapping of the magnetic flux remains in effect.

By significantly reducing electromagnetic leakage to higher or lower layers of IC 300, electromagnetic losses are significantly reduced and essentially eliminated. Moreover, because of the trapping effect shown, there is no need for turns, coils or spiral-like implementations, commonly used in prior art solutions. Thus, the need for "via" holes is also eliminated.

Manufacturing of a planar inductor, in accordance with the present invention, fits well within the process flows of standard semiconductor manufacturing. The standard manufacturing processing is carried out by adding either post-processing or in process of deposition of the ferromagnetic layers 340-B and 340-T.

On top of a surface of IC 300, at the end of standard processing, a first layer 340-B of electrically highly resistive, high-permeability soft ferromagnetic material is deposited. A highly conductive metal layer is then deposited on top of the first layer, patterned, and etched as normally performed in semiconductor manufacturing known in the art, such that a conducting strip having the desired geometrical form is obtained.

The conducting strip of the inductor is formed to comply with the restrictions discussed above, and more specifically, no self-intersecting of the conducting strip is permitted. There is no requirement to move to a different layer in order to complete the design of the inductor, or to be able to access it electrically. Thereafter at least the area of the inductor is coated with a second layer 340-T of an electrically highly resistive soft ferromagnetic material having a high permeability, where the electrical high resistivity is required to minimize eddy currents loss of power in the coating layers. Thereon, the process continues as is customary for standard semiconductor manufacturing. A typical thickness of first layer 340-B and second layer 340-T is one micron or less, but may reach higher values, depending on the nature of the coating materials and range of frequencies.

A U-shaped inductor may well provide an adequate solution, however, there may be cases where higher inductance per unit area is necessary. This may be achieved by taking advantage of the fact that the total inductance is proportional to the length of the conducting strip covered by the ferromagnetic layers.

Reference is now made to Fig. 7, where an exemplary and non-limiting meander-shaped conducting strip 720, designed in accordance with a third implementation of the present invention on IC 700, is shown. Reference is further made to Fig. 8 where a cross-section A-A of IC 700 is shown.

The inductor comprises a layer 740-B of an electrically highly resistive, soft ferromagnetic material having a high permeability, which is deposited over surface 710.

At the next step, a conducting strip 720 is formed in a meander shape, composed of an even number of parallel sections, where the two ends 730 and 735 of the conducting strip are placed such that they run close and parallel to each other.^' The use of the meander shape provides for relatively high inductance per unit IC area and also for the requirement not to have any serf-intersecting point in conducting strip 720, thus avoiding any need to move to a higher or lower layer of IC 700.

Another important advantage of a meander shaped inductor is with respect to the further suppression of electromagnetic leakage. This is due to the fact that the electrical current flowing in any two adjacent sections of the meander generates magnetic fields that are equal in magnitude but reverse in direction. If the meander is composed of an even number of sections, then the magnetic fields generated by all the sections, at distances relatively far from the meander inductor, tend to cancel each other, thus reducing the electromagnetic leakage, or interference, to the environment.

The surface area of conducting strip 720 is coated by a second layer 740-T of an electrically highly resistive, high permeability soft ferromagnetic material, so that conducting strip 720 is completely everywhere covered by either one of the two ferromagnetic layers. Such a ferromagnetic layer may be made of, or contain, a nano-crystaline material containing Fe-Co-X-N, where X may be, for example, any one of Ta, Cu, Ta-Si, Cu-Si, or Si.

Once coated with the second layer 740-T, processing of IC 700 may continue in accordance with standard semiconductor manufacturing technologies and processes. The manufacturing processes of the meander shaped inductor are similar to those explained above.

Using a copper conductor strip having a cross section of fifteen-by-fifteen micrometers, coated by a two micrometer coating of an electrically highly resistive, soft ferromagnetic material 740, having a relative permeability of 600 and anelectrical specific resistivity of 10 ohms-cm, shows, at 1.842 giga Hertz, a Q-factor exceeding 400. The inductance per unit length of such a meander shaped inductor may come close to twenty-five nano-Henry per millimeter, wherein the inductance per unit area may come close to one micro-Henry per square millimeter. This happens due to the magnetic flux trapping that occurs in the coating layers 740-B and 740-T, completely coating conducting strip 720. Furthermore, high inductance values are achieved because of the magnetic flux density amplification due to the ferromagnetic coating comprising layers 740-B and 740-T. The phenomena are shown in Fig. 9 where an enlargement of a portion of the cross-section is shown.

Reference is now made to Fig. 9 that shows a simulation of the current density in a cross section of the meander-shaped inductor's conducting strip and the magnetic flux in the coating around the inductor's conducting strip, at a frequency of 2.4 giga Hertz. When the frequency of operation is 2.4 giga-Hertz the current density is significantly higher at the sharp edges of the cross section of meander-shaped conducting strip 720 than the current density at the center of the cross section of conducting strip 720.

The magnetic flux caused due to the current flow through conducting strip 720 is almost completely trapped in the ferromagnetic material 740 around conducting strip 720. By minimizing electromagnetic leakage penetration to a higher or lower layers of IC 700 through "via" holes or otherwise, power losses are significantly reduced and essentially eliminated. Moreover,^' because of the trapping effect shown, there is no need for turns, coils or spiral-like implementations commonly used in prior art solutions.

A person skilled in the art would note that due to process variations there might be a need to trim an inductor manufactured in accordance with the present invention, in order for the inductance value to be more accurate.

Reference is now made to Fig. 10 where an exemplary and non-limiting linear U-shaped inductor with trimming is shown in accordance with a fourth embodiment of the present invention. U-shaped conducting strip 320 is deposited upon a layer 340-B, the layer made of an electrically highly resistive, soft ferromagnetic material having a high permeability. Conducting strip 320 is then covered by a deposited layer 340-T of highly resistive soft ferromagnetic material having a high permeability.

If it is necessary to trim the value of U-shaped inductor, then it is desirable to expose at least a portion, such as exposure area 1010, of the conducting strip 320, from electrically highly resistive, soft ferromagnetic material having a high permeability layer 340-T. Such an exposure can be performed by, but is not limited to, a laser. Once exposed, there is an impact on the inductance of the inductor proportional to the length of conducting strip exposed. There may further be a small degradation of the value of Q of the inductor. However, due to the very high Q values of inductors manufactured according to the present invention, such degradation is relatively small and the inductor will still have a high Q value.

In accordance with yet another embodiment of the present invention, the areas exposed at the proximities of the electrical contacts of the inductor (not shown) are equal and symmetrical at both ends. This is to ensure minimization of interference electromagnetic fields caused outside the inductor, discussed in more detail above.

Having described the invention with regard to certain specific embodiments thereof, it is to be understood that the description is not meant as a limitation, since further modifications will now suggest themselves to those skilled in the art, and it is intended to cover such modifications as fall within the scope of the appended claims.

Claims

1. An inductor integrated onto an integrated circuit (IC), said inductor comprising; a first layer of an electrically highly resistive soft ferromagnetic material having a high permeability, deposited on a surface of the IC; an electrically conducting strip made of a highly conducting metal, said strip formed on top of said first layer and having electrical contacts formed at both ends of said strip, wherein said strip and said contacts are not intersecting nor self-intersecting; and a second layer of an electrically- highly resistive soft ferromagnetic material having a high permeability, deposited over said strip and at least partially over said first layer, such that said strip is entirely covered by an electrically highly resistive soft ferromagnetic material having a high permeability, of either said first layer or said second layer.

2. The inductor of claim 1, wherein said surface of the IC is one of a plurality of layers of the IC

3. The inductor of claim 1, wherein said soft ferromagnetic material having a high permeability has a relative permeability over 50.

4. The inductor of claim 3, wherein said inductor has a Q-factor of above one , hundred.

5. The inductor of claim 1, wherein said electrically highly resistive soft ferromagnetic material having a high permeability is at least in part in a form of hano-crystallines.

6. The inductor of claim 1, wherein said conducting strip is formed in a planar shape forming one of: a U-shape, a rectangular shape, a meander-shape.

7. The inductor of claim 1, wherein at least a portion of said second layer is removed from over said conducting strip for the purpose of post-processing trimming.

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8. The inductor of claim 7, wherein said removal of said at least a portion of said second layer is performed by a laser.

9. The inductor of claim 7, wherein said removal of said at least a portion of said second layer is performed symmetrically at the proximities of said electrical contacts.

10. The inductor of claim 1, wherein a thickness of said first layer and said second layer is less than one micrometer.

11. The inductor of claim 1, wherein said thickness of said first layer and said second layer is at least one micrometer.

12. The inductor of claim 1, wherein said conducting strip is made of at least one of: gold, aluminum, copper, platinum.

13. The inductor of claim 1, wherein said electrical contacts are located so as to essentially enable nullification of electromagnetic interference to a surrounding.

14. . A method for integrating an inductor onto a surface of an integrated circuit (IC), the method comprising the steps of: providing a surface of an integrated circuit; depositing on top of said surface a first layer of electrically highly resistive soft ferromagnetic material having a high permeability; depositing a highly electrically conductive metal layer over at least said first layer; patterning said metal layer forming a conducting strip and electrical contacts at both ends of said strip, such that said conducting strip and said electrical contacts do not intersect or self-intersect; and depositing a second layer of an electrically highly resistive and soft ferromagnetic material having a high permeability, such that said conducting strip is entirely covered by an electrically highly resistive soft ferromagnetic material having a high permeability, of either said first layer or said second layer.

15. The method of claim 14 further comprising the step of: trimming said inductor by removing at least a portion of said second layer off said conducting strip.

16. The method of claim 15, wherein said removal of said at least a portion of said second layer is performed by a laser.