TWM675394U - Double-sided printed circuit board with trace offset check mark - Google Patents

Abstract

A double-sided printed circuit board (PCB) with circuit offset inspection marks is used to solve the problem of difficulty in inspecting upper and lower circuit offsets on conventional double-sided PCBs. The system comprises: a substrate; a plurality of offset identification marks, located on the upper and lower surfaces of the substrate, respectively; four of the offset identification marks forming a group, each group of offset identification marks having another group of offset identification marks positioned oppositely on the other surface of the substrate; and a perforated alignment mark, which penetrates the upper and lower surfaces of the substrate and is located between two groups of offset identification marks positioned oppositely on the upper and lower surfaces. The offset components between the offset identification marks and each offset identification mark are less than a first error range, and the total offset components in the same direction are less than a second error range. This improves inspection efficiency and increases product yield.

Description

Double-sided printed circuit board with circuit offset check marks

This invention relates to a double-sided substrate for electronic components and circuits, and more particularly to a double-sided printed circuit board with circuit deviation inspection marks that simplifies circuit deviation defect detection.

Conventional double-sided printed circuit boards (PCBs) feature conductive traces on both the top and bottom surfaces of the substrate, allowing for the assembly of more electronic components, saving costs and increasing mounting space. When interconnection between the traces on the top and bottom surfaces is required, through-holes are provided in the substrate to allow electrical connection between the upper and lower trace patterns. However, if offset errors occur during the sequential manufacturing process, the upper and lower traces may not be properly connected, and the conductive traces may even be damaged when the circuit board is cut.

Conventional printed circuit board (PCB) manufacturing processes typically use automated optical inspection (AOI) to verify the correctness of circuit patterns to eliminate defects such as open circuits, short circuits, dimensional anomalies, and foreign objects. However, the conventional double-sided PCBs mentioned above require flipping over and performing another inspection after completing one-sided inspection. However, even this second inspection cannot effectively identify misaligned circuit patterns on the top and bottom surfaces. This can lead to faulty circuits not being detected until later during component assembly, resulting in wasted manufacturing costs and reduced production efficiency.

In view of this, conventional double-sided printed circuit boards and their testing methods still need to be improved.

To address the aforementioned issues, this invention aims to provide a double-sided printed circuit board with trace offset detection markings, allowing for rapid inspection of trace offsets on both upper and lower layers.

A secondary purpose of this invention is to provide a double-sided printed circuit board with a trace offset detection mark to improve process efficiency.

Another purpose of this invention is to provide a double-sided printed circuit board with a trace offset inspection mark to improve product yield.

Throughout this document, directional terms or similar terms, such as "left," "right," "upper (top)," "lower (bottom)," and "side," are primarily used with reference to the directions in the accompanying drawings. These directional terms or similar terms are intended solely to facilitate the description and understanding of the various embodiments of this document and are not intended to limit this document.

The use of the quantifiers "a" or "an" in the elements and components described throughout this work is merely for convenience and to provide a general understanding of the scope of this work. In this work, they should be interpreted as including one or at least one, and the singular concept also includes the plural, unless it is obvious that it means otherwise.

Throughout this work, terms such as "first," "second," ..., and "Nth" are primarily used to distinguish between different elements or features (such as components, directions, or steps). They do not indicate a maximum or minimum number of such elements or features that a corresponding subject or method may possess, nor do they limit the order of precedence.

The double-sided printed circuit board with circuit offset detection marks of this invention comprises: a substrate having a circuit layer on its upper and lower surfaces; a plurality of offset identification marks located on the upper and lower surfaces of the substrate, respectively. The offset identification marks are located on both sides of the circuit layer and formed together with the circuit layer, wherein four offset identification marks form a group, and each group of offset identification marks has a plurality of offset identification marks on the other side of the substrate. There is another set of offset identification marks positioned opposite each other; and a perforated alignment mark that penetrates the upper and lower surfaces of the substrate and is located between the two sets of offset identification marks at opposite positions on the upper and lower surfaces. The offset component between the perforated alignment mark and the surrounding offset identification marks on the upper and lower surfaces is less than a first error range, and the total offset component in the same direction on each of the upper and lower surfaces is less than a second error range.

Based on this, the double-sided printed circuit board (PCB) with circuit offset inspection marks, which are created during circuit pattern exposure, forms several offset identification marks. The offset of these marks on the top and bottom surfaces is then measured using the perforation alignment mark as a reference point. This allows automated optical inspection to quickly determine whether the top and bottom layers of the PCB meet product specifications, thereby improving product yield and enhancing the efficiency of the inspection process.

The first error range is 20 microns, and the second error range is 25 microns. This allows pattern deviation to be controlled within product specifications, improving the yield rate of printed circuit boards.

Each offset identification mark is a circular pattern with a diameter of 0.1 mm to 0.2 mm. This allows automated optical inspection equipment to identify the offset identification marks, automating and improving inspection efficiency.

The four offset identification marks are arranged along a crosshair, with the intersection of the crosshairs equidistant from each offset identification mark. This allows measurement along the crosshairs to determine the offset in four directions: up, down, left, and right, effectively assisting in detecting the position of the pattern.

The upper and lower offset identification marks, as well as the left and right offset identification marks, each have an identification width. This distance is the distance between the center points of the two offset identification marks and is between 0.8 mm and 2 mm. This identification width allows for the placement of the laser perforation and its offset, facilitating the establishment of a reference point and the measurement of offset.

The distance between the center of the perforated alignment mark and the intersection of the crosshairs is a total offset, which includes two offset components in the up and down directions and the left and right directions. This allows for separate verification of offset in different directions, effectively ensuring accuracy.

The center of the perforated alignment mark overlaps with the intersection of the crosshairs, and the total offset and each offset component are zero. This allows for rapid alignment, improving inspection efficiency.

The diameter of the perforation alignment mark is 0.5 mm to 1 mm. This allows the perforation alignment mark to be set via laser perforation, simplifying the manufacturing process.

1:Substrate

2: Offset identification mark

3: Perforation alignment mark

E: Line layer

T: Transmission hole

C: Crosshairs

P: Intersection

W: Recognition width

d1,d2: diameter

[Figure 1] A plan view of the circuit board layout of a preferred embodiment of this invention.

[Figure 2] A partially enlarged cross-sectional view of the inspection mark of a preferred embodiment of this invention.

[Figure 3] A partially enlarged cross-sectional view of the inspection mark of another embodiment of this invention.

[Figure 4] A partially enlarged plan view of the inspection mark of a preferred embodiment of this invention.

To make the above and other purposes, features, and advantages of this invention more clearly understood, the following provides a preferred embodiment of this invention and a detailed description thereof with reference to the accompanying drawings. Furthermore, elements marked with the same symbols in different drawings are considered identical and their descriptions are omitted.

Please refer to Figures 1 and 2, which illustrate a preferred embodiment of a double-sided printed circuit board with circuit offset detection marks according to the present invention. The board comprises a substrate 1, several offset identification marks 2, and a through-hole alignment mark 3. The offset identification marks 2 are located at opposite positions on the upper and lower surfaces of the substrate 1, respectively. The through-hole alignment mark 3 penetrates the substrate 1 and is located between the offset identification marks 2.

The upper and lower surfaces of the substrate 1 may each have a circuit layer E. This circuit layer E forms a conductive pattern on the surface of the substrate 1 through processes such as exposure, development, and etching. This pattern is used to mount and electrically connect electronic components on the circuit board. Furthermore, the edges of the substrate 1, i.e., on both sides of the circuit layer E, may have a plurality of transmission holes T arranged in a row to facilitate transport and processing of the substrate 1 between various process machines. The spaces between these transmission holes T may also contain markings for alignment during the various process steps and for quality control inspection of the completed circuit board.

Referring to Figures 2-4 , the offset identification marks 2 can be arranged in groups of four and located at the top, bottom, left, and right, respectively. The four offset identification marks 2 are arranged along a crosshair C, with the intersection point P of the crosshairs C preferably being equidistant from each offset identification mark 2. A recognition width W is defined between the top and bottom (left and right) offset identification marks 2. This recognition width W can be the distance between the center points of the two offset identification marks 2 and can range from 0.8 mm to 2 mm. In this embodiment, each offset identification mark 2 is a circular pattern, and the diameter d1 of each offset identification mark 2 can be 0.1 mm to 0.2 mm. That is, the identification width W can be the distance between the centers of the two offset identification marks 2, and the distance from the center of each offset identification mark 2 to the intersection point P can be 0.4 mm to 1 mm. However, each offset identification mark 2 in this invention can also be a pattern with an easily identifiable center point, such as a cross, diamond, or 'poz', and this invention is not limited to this.

The multiple offset identification marks 2 can also be formed on the surface of the substrate 1 along with the circuit layer E through processes such as exposure, development, and etching. Each set of offset identification marks 2 has another set of offset identification marks 2 positioned oppositely on the other side of the substrate 1. As shown in Figure 2, each offset identification mark 2 can be at the same height as the circuit layer E, protruding from the surface of the substrate 1. Alternatively, as shown in Figure 3, each offset identification mark 2 can be located on the surface of the substrate 1, lower than the surrounding circuit layer E. However, this invention is not limited to this.

The perforation alignment mark 3 can be drilled together with the through-hole on the printed circuit board during the laser drilling process. It is located between a set of offset identification marks 2. As shown in Figure 2, since the perforation alignment mark 3 penetrates the substrate 1, it is also located between another set of offset identification marks 2 on the other side of the substrate 1. The diameter d2 of the perforation alignment mark 3 can be between 0.5 mm and 1 mm. Using the position of the perforation alignment mark 3 as a reference point, the offset of the surrounding offset identification marks 2 can be measured to determine whether a circuit layer E formed on the upper and lower surfaces of the substrate 1 has offset.

During the visual inspection of printed circuit boards (PCBs), automated optical inspection measures the relative distances between the perforation alignment mark 3 and the surrounding offset identification marks 2 located on the upper and lower surfaces of the substrate 1. If the exposure pattern of the circuit layer E and the offset identification marks 2 is consistent, as shown in Figure 3, the center of the perforation alignment mark 3 overlaps with the intersection P of the crosshairs C. A total offset is measured between the intersection P and the center of the perforation alignment mark 3. If the offset components of this total offset in all directions (upward, downward, leftward, and rightward on both the upper and lower surfaces) are all less than a first error range, the PCB is considered acceptable. Otherwise, it is considered defective. This first error range can be 20 microns.

In addition, the sum of the offset components in the same direction on the upper and lower surfaces must be less than a second error range. The second error range can be 25 microns. For example, if the offset on the upper surface is 15 microns to the right and the offset on the lower surface is 15 microns to the right, then the circuit layer E and the offset identification marks 2 on the upper and lower surfaces are only offset from the perforation alignment mark 3. The offsets between them are exactly offset, and each offset component is within the error range. The deviation on the top surface is 15 microns to the right, and the deviation on the bottom surface is 15 microns to the left (i.e., -15 microns to the right). While the deviations between the circuit layer E and the offset identification marks 2 on both the top and bottom surfaces and the perforation alignment mark 3 are within the error range, the total deviation between the top and bottom surfaces is 30 microns, exceeding the second error range and thus being a defective product.

In summary, this invention's double-sided printed circuit board with circuit offset inspection marks forms several offset identification marks during circuit pattern exposure. The offset of these multiple offset identification marks on the top and bottom surfaces is then measured using the perforation alignment mark as a reference point. This allows automated optical inspection to quickly determine whether the top and bottom layers of a double-sided printed circuit board meet product specifications, thereby improving product yield and enhancing the efficiency of the inspection process.

Although this invention has been disclosed using the preferred embodiments described above, they are not intended to limit this invention. Any person skilled in the art may make various changes and modifications to the embodiments described above without departing from the spirit and scope of this invention. These changes and modifications are still within the scope of technology protected by this invention. Therefore, the scope of protection of this invention shall include all changes within the meaning and equivalent scope of the attached patent application.

1:Substrate

2: Offset identification mark

3: Perforation alignment mark

E: Line layer

T: Transmission hole

Claims (8)

A double-sided printed circuit board with circuit offset detection marks comprises: a substrate having a circuit layer on its upper and lower surfaces; a plurality of offset identification marks located on the upper and lower surfaces of the substrate, respectively, the offset identification marks being located on both sides of the circuit layer and formed together with the circuit layer, wherein four of the offset identification marks form a group, and each group of offset identification marks has another group of offset identification marks located oppositely on the other side of the substrate; and A perforated alignment mark passes through the upper and lower surfaces of the substrate and is simultaneously located between two sets of offset identification marks at relatively opposite positions on the upper and lower surfaces. The offset component between the perforated alignment mark and each of the surrounding offset identification marks located on the upper and lower surfaces is less than a first error range, and the total offset component in the same direction on each of the upper and lower surfaces is less than a second error range. A double-sided printed circuit board with a line deviation check mark as claimed in claim 1, wherein the first error range is 20 microns and the second error range is 25 microns. A double-sided printed circuit board with a line offset check mark as claimed in claim 1, wherein each of the offset identification marks is a circular pattern, and the diameter of each of the offset identification marks is 0.1 mm to 0.2 mm. A double-sided printed circuit board with line offset check marks as claimed in claim 1, wherein the four offset identification marks are arranged according to a cross line, and the intersection of the cross line is equidistant from each of the offset identification marks. As in claim 4, a double-sided printed circuit board with a line offset check mark, wherein there is an identification width between the two upper and lower offset identification marks and between the two left and right offset identification marks, and the identification width is the distance between the center points of the two offset identification marks, and the identification width is 0.8 mm to 2 mm. As in claim 4, a double-sided printed circuit board with a line offset check mark, wherein the distance between the center of the perforated alignment mark and the intersection of the cross line is a total offset, and the total offset includes two offset components in the upper and lower directions and the left and right directions. A double-sided printed circuit board with a line offset check mark as claimed in claim 6, wherein the center of the perforated alignment mark overlaps with the intersection of the crosshairs, and the total offset and each of the offset components are zero. A double-sided printed circuit board with a line deviation check mark as claimed in claim 1, wherein the diameter of the perforation alignment mark is 0.5 mm to 1 mm.