TWM642378U - Semiconductor packaging carrier board structure - Google Patents

Abstract

The creation discloses a semiconductor packaging carrier board structure, which includes an insulating layer and a circuit build-up structure. The circuit build-up structure is combined with the insulating layer and a plurality of patterned external electrical connection pads being existed on at least one side of the circuit build-up structure. The patterned external electrical connection pads are embedded in the insulating layer and one side of them is exposed on a surface of the insulating layer. The peripheral surface of the patterned external electrical connection pad has a plurality of concave parts and/or a plurality of convex parts arranged side by side and extending longitudinally, wherein the concave parts are grooves and the convex parts are convex bars.

Description

Semiconductor Package Substrate Structure

The invention relates to a semiconductor device, in particular to a semiconductor packaging substrate structure.

Land Grid Array (LGA) packaging is a surface mounting technology for integrated circuits. Compared with the Ball Grid Array (BGA) package, it has a lighter and thinner package appearance, and is especially suitable for applications requiring high electrical performance.

FIG. 1A is a schematic diagram of a conventional planar grid array package 10 . The planar grid array package 10 includes an insulating portion 111 and a conductive portion 112 . As the planar grid array package 10 meets the demand of high power, the area of the contact surface 113 between the insulating part 111 and the conductive part 112 increases. Under such conditions, as shown in FIG. 1B , it is easy to cause cracks C1 or separation on the contact surface of the insulating part 111 and the conductive part 112 during the reliability verification during the packaging process or during packaging. In addition to reducing the electrical performance, the abnormal condition may even cause structural damage to the package carrier and reliability problems.

Therefore, how to provide a semiconductor package carrier structure to avoid the above-mentioned problems is one of the current important issues.

One purpose of the present invention is to provide a semiconductor packaging substrate structure, which can avoid cracks or separation defects between different components in the structure by designing the whole body as an irregular structure.

To achieve the above purpose, the present invention provides a semiconductor packaging substrate structure, which includes an insulating layer and a circuit build-up structure. Layer-added structure system and insulation The insulation layers are combined, and at least one side of the circuit build-up structure includes a plurality of patterned external electrical connection pads. The patterned external electrical connection pads are embedded in the insulating layer, and one side of them is exposed on a surface of the insulating layer. Wherein, the peripheral surface of the patterned external electrical connection pad is provided with a plurality of concave parts and/or a plurality of convex parts extending longitudinally side by side, and the concave parts are grooves, and the convex parts are convex lines.

In one embodiment, the semiconductor package substrate structure is a land grid array package substrate (LGA) structure.

In one embodiment, the cross-sectional shapes of the concave portion and the convex portion are respectively rectangular, triangular, arc, irregular or a combination thereof.

In one embodiment, the concave portion is a groove with a cross section expanding inward, and the convex portion is a ridge with a cross section expanding outward.

In one embodiment, the material of the insulating layer includes organic photosensitive dielectric material, organic non-photosensitive dielectric material and/or inorganic oxide material.

In one embodiment, the circuit build-up structure further includes a plurality of patterned conductive pillars, and the peripheral surface of the patterned conductive pillars is provided with a plurality of concave portions and/or a plurality of convex portions extending longitudinally in parallel, and the concave portions are is a groove, and the convex part is a convex line.

In one embodiment, the cross-sectional shapes of the concave portion and the convex portion of the patterned conductive pillar are respectively rectangular, triangular, curved, irregular or a combination thereof.

In one embodiment, the concave portion of the patterned conductive pillar is a groove whose cross-section expands inward, and the convex portion is a ridge whose cross-section expands outward.

Based on the above, the structure of the semiconductor packaging substrate in this creation uses the concave-convex structure to increase the contact area between the insulating layer and the circuit build-up structure or the interfering interference force, thereby increasing the bonding force, and thus avoiding the insulation Cracks or separations occur between the layer and the circuit build-up structure, thereby enhancing the reliability of the semiconductor packaging substrate structure.

10: Planar grid array package

111: insulation part

112: Conductive part

113: contact surface

20:Semiconductor Package Substrate Structure

210: core layer

211: The first side

212: second side

220: The first building-up structure

2201: First mounting surface

221: The first insulating layer

222: Layer-increased structure of the first line

2221: Patterned external electrical connection pads

2211: surface

230: Second build-up structure

2301: Second mounting surface

231: Second insulating layer

232: Layer-increased structure of the second line

2321: Patterned conductive pillars

240: conductive connection layer

251: convex part

252: Concave

260: protective layer

270: chip

271: Conductive bump

C1: Crack

[FIG. 1A] and [FIG. 1B] are schematic diagrams showing a conventional semiconductor package substrate structure.

[FIG. 2] is a schematic cross-sectional view showing a structure of a semiconductor packaging substrate according to a preferred embodiment of the present invention.

[FIG. 3] is a schematic plan view showing the bottom surface of a semiconductor package carrier structure according to a preferred embodiment of the present invention.

[FIG. 4A] is a partial three-dimensional schematic diagram of the first circuit build-up layer structure of the semiconductor package substrate structure of the present invention, which has a plurality of protrusions around it.

[FIG. 4B] is a partial perspective view of the plurality of recesses corresponding to the protrusions in the first insulating layer of the semiconductor package substrate structure of the present invention.

[FIG. 5A] to [FIG. 5C] are schematic diagrams of changes in the combination of concave and convex portions of the semiconductor package substrate structure of the present invention.

[FIG. 6A] to [FIG. 6B] are schematic diagrams showing the variation of the cross-sectional shape of the recessed part and the convex part of the semiconductor package substrate structure of the present invention.

[FIG. 7] is a schematic view showing that the structure of the semiconductor packaging substrate of the present invention also has a protective layer.

In order to enable those with ordinary knowledge in the technical field to understand the content of the creation and realize the content of the creation based on it, appropriate embodiments and drawings are hereby described as follows.

Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic cross-sectional view of a semiconductor package carrier structure 20 according to a preferred embodiment of the present invention, and FIG. 3 is a schematic plan view of the bottom surface of the semiconductor package carrier structure 20 . The semiconductor package substrate structure 20 includes a core layer 210 and a first build-up structure 220 and a second build-up structure 230 disposed on the upper and lower sides of the core layer 210 . The first build-up structure 220 is disposed on the first surface 211 of the core layer 210 , and the second build-up structure 230 is disposed on the second surface 212 of the core layer 210 . The first build-up structure 220 and the second build-up structure 230 are electrically connected to each other through a conductive connection layer 240 passing through the core layer 210 . It should be noted that in some embodiments, the core layer 210 and the conductive connection layer 240 are not necessary, and the semiconductor package substrate structure can also be formed by stacking the first build-up structure and the second build-up structure (ie For Coreless package carrier board).

The first build-up structure 220 has a first insulating layer 221 and a first The wiring build-up structure 222 is a first mounting surface 2201 on a side away from the first surface 211 of the core layer 210 . The first insulating layer 221 covers the first circuit build-up structure 222 , and one side of the first circuit build-up structure 222 exposed on the first insulating layer 221 is a patterned external electrical connection pad 2221 . It can be seen from FIG. 2 that the patterned external electrical connection pad 2221 is embedded in the first insulating layer 221 , and one side of the patterned external electrical connection pad 2221 is exposed on a surface 2211 of the first insulating layer 221 . In other embodiments, the first build-up structure 220 may have a plurality of stacked layers of the first insulating layer 221 and the first wiring build-up structure 222 , and the number of layers is not limited.

Please refer to FIG. 4A and FIG. 4B , which are partial perspective views showing part of the first insulating layer 221 and part of the first circuit build-up structure 222 respectively. As shown in FIG. 4A , the patterned first wiring build-up structure 222 is provided with a plurality of longitudinally extending convex portions 251 on the peripheral surface of the external electrical connection pad 2221 in the form of convex strips. As shown in FIG. 4B , the first insulating layer 221 has a plurality of corresponding recesses 252 in the form of grooves. The convex portion 251 in the shape of a convex line is combined with the concave portion 252 in the shape of a groove. It is worth mentioning that the aforementioned longitudinal direction is approximately perpendicular to the first installation surface 2201 .

5A to 5C are partially enlarged schematic diagrams showing the bottom surface of the semiconductor package substrate structure 20 . FIG. 5A shows an embodiment in which the first insulating layer 221 has a concave portion 252 and the first circuit build-up structure 222 has a convex portion 251 . FIG. 5B shows an embodiment in which the first insulating layer 221 has a convex portion 251 and the first wiring build-up structure 222 has a concave portion 252 . FIG. 5C shows an embodiment in which the first insulating layer 221 and the first wiring build-up structure 222 have protrusions 251 and recesses 252 respectively.

The above description is based on the example that the cross-sectional shape of the convex portion 251 and the concave portion 252 is an arc shape, especially the cross-sectional shape is an arc shape that fits and interferes with each other. In other words, the protruding portion 251 is, for example, a ridge with a section that expands outward, and the concave portion 252 is, for example, a groove with a section that expands inward. In other embodiments, the cross-sectional shapes of the convex portion 251 and the concave portion 252 can also be other shapes, such as including but not limited to triangular (as shown in FIG. 6A ), rectangular (as shown in FIG. 6B ) or irregular (not shown in FIG. Shows). In addition, in other embodiments, the convex portion 251 and the concave portion 252 with the same or different cross-sectional shapes may also be present in the same semiconductor package substrate structure 20 at the same time, which is not limited.

Through the convex portion 251 and the concave portion 252, the contact area between the first insulating layer 221 and the first wiring build-up structure 222 can be increased and a rough contact surface can be formed, or the interference between the two can be increased by interfering with each other. between the bonding force, thereby avoiding cracks.

Please refer to FIG. 2 again, the second build-up structure 230 has a second insulating layer 231 and a second line build-up structure 232 stacked, and on the side away from the second surface 212 of the core layer 210 is a first Two mounting surfaces 2301 . The same as the first build-up structure 220 is that the second build-up structure 230 can have a plurality of stacked layers of the second insulating layer 231 and the second circuit build-up structure 232 , and the number of layers is not limited. The second circuit build-up structure 232 may include a plurality of patterned conductive pillars 2321 . The peripheral surface of the patterned conductive pillar 2321 is juxtaposed with a plurality of protrusions 251 extending longitudinally, and the second insulating layer 231 has a plurality of recesses 252 . In this embodiment, the convex portion 251 is a convex line, and the concave portion 252 is a groove, similar to the first build-up structure 220 described above, the second circuit build-up structure 232 and the convex portion 251 of the second insulating layer 231 and The implementation of the concave portion 252 can also have the same variation as above.

In other embodiments, the conductive connection layer 240 can also have a plurality of protrusions and/or recesses similar to the above-mentioned patterned conductive pillars 2321, and the core layer 210 can have a plurality of corresponding recesses and/or protrusions. Interference with each other at the right time increases the binding force. Wherein, the implementation and changes of the convex part and the concave part are the same as above, and will not be repeated here.

Referring to FIG. 2 again, the semiconductor package substrate structure 20 further includes a chip 270 which can be electrically connected to the second mounting surface 2301 of the second build-up structure 230 through a plurality of conductive bumps 271 . Wherein, the conductive bump 271 includes, but is not limited to, solder balls, gold bumps, or conductive glue and other connection elements with conductive functions.

The semiconductor packaging substrate structure 20 of this embodiment can be a planar grid array packaging substrate structure, and the first mounting surface 2201 and the second mounting surface 2301 mentioned above can be used to electrically connect chips or other packaging substrate structures. and can be applied to, for example but not limited to, power management ICs (PMICs).

In addition, please refer to FIG. 7 again, the semiconductor package substrate structure 20 is also A protection layer 260 may be included, which may be formed on a portion of the first mounting surface 2201 to expose a portion of the patterned external electrical connection pads 2221 of the first circuit build-up structure 222 . The protection layer 260 is used as a solder resist layer, and can protect the first circuit build-up structure 222 to avoid or delay oxidation reaction.

In addition, the above-mentioned first insulating layer 221 and the second insulating layer 231 may be made of organic photosensitive dielectric material or organic non-photosensitive dielectric material, such as insulating material including glass fiber and organic resin. Wherein, the organic resin includes but not limited to the base material such as BT, FR4 or FR5 or the epoxy resin of prepreg (prepreg), organic base material ABF (Ajinomoto Build-up Film), epoxy molding resin (Epoxy Molding Compound , EMC), film EMC or polyimide (Polyimide, PI). The material of part of the insulating layer may also include micron or nanoscale inorganic oxide materials, such as silicon oxide (SiOx), nickel oxide (NiO) or copper oxide. In some specific embodiments, the insulating layers can be made of the same or different materials.

To sum up, a semiconductor packaging substrate structure in this invention is to provide a connection structure on the contact surface between the insulating layer and the circuit build-up structure, and increase the contact area by cooperating with the convex part and the concave part, or by embedding Interference with each other, and then increase the bonding force to avoid cracks and increase reliability, especially suitable for large-area, high-power electronic devices.

The above-mentioned embodiments are only used to enumerate the implementation of the creation and explain the technical characteristics of the creation, and are not used to limit the scope of protection of the creation. Any changes or equivalence arrangements that can be easily accomplished by those familiar with this technology fall within the scope of this creation, and the protection scope of this creation should be based on the scope of the patent application.

20:Semiconductor Package Substrate Structure

210: core layer

211: The first side

212: second side

220: The first building-up structure

2201: First mounting surface

221: The first insulating layer

2211: surface

222: Layer-added structure of the first line

2221: Patterned external electrical connection pads

230: Second build-up structure

2301: Second mounting surface

231: Second insulating layer

232: Layer-increased structure of the second line

2321: Patterned conductive pillars

240: conductive connection layer

251: convex part

252: Concave

270: chip

271: Conductive bump

Claims (8)

A semiconductor package carrier structure, comprising: an insulating layer; and A circuit build-up structure combined with the insulating layer, and at least one side of the circuit build-up structure includes a plurality of patterned external electrical connection pads, the patterned external electrical connection pads are embedded in the insulating layer layer, and one of the sides is exposed on one surface of the insulating layer; Wherein, the peripheral surface of the patterned external electrical connection pad is provided with a plurality of concave parts and/or a plurality of convex parts extending longitudinally in parallel, and the concave parts are grooves, and the convex parts are convex strips. The semiconductor packaging substrate structure described in claim 1 is a planar grid array packaging substrate structure. The semiconductor package substrate structure according to claim 1, wherein the cross-sectional shapes of the concave portion and the convex portion are respectively rectangular, triangular, arc, irregular or a combination thereof. The semiconductor package substrate structure according to claim 1, wherein the concave portion is a groove with a cross-section expanding inward, and the convex portion is a ridge with a cross-section expanding outward. The semiconductor packaging substrate structure according to claim 1, wherein the insulating layer is made of an organic photosensitive dielectric material, an organic non-photosensitive dielectric material and/or an inorganic oxide material. The semiconductor package substrate structure as described in claim 1, wherein the circuit build-up structure further includes a plurality of patterned conductive pillars, and the peripheral surface of the patterned conductive pillars is provided with a plurality of longitudinally extending concave portions and And/or a plurality of convex parts, the concave part is a groove, and the convex part is a convex line. The semiconductor package substrate structure according to claim 6, wherein the cross-sectional shapes of the concave portion and the convex portion of the patterned conductive pillar are respectively rectangular, triangular, arc, irregular or a combination thereof. The semiconductor package substrate structure as claimed in claim 6, wherein the concave portion of the patterned conductive pillar is a groove with a cross section expanding inward, and the convex portion is a convex strip with a cross section expanding outward.

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