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TWI800845B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI800845B
TWI800845B TW110120650A TW110120650A TWI800845B TW I800845 B TWI800845 B TW I800845B TW 110120650 A TW110120650 A TW 110120650A TW 110120650 A TW110120650 A TW 110120650A TW I800845 B TWI800845 B TW I800845B
Authority
TW
Taiwan
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
TW110120650A
Other languages
English (en)
Other versions
TW202226554A (zh
Inventor
福本敦之
藤田淳也
有隅修
文帆
伊藤貴之
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202226554A publication Critical patent/TW202226554A/zh
Application granted granted Critical
Publication of TWI800845B publication Critical patent/TWI800845B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H10P32/141—
    • H10P32/171—
TW110120650A 2020-09-09 2021-06-07 半導體裝置及其製造方法 TWI800845B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020151455A JP7502122B2 (ja) 2020-09-09 2020-09-09 半導体装置およびその製造方法
JP2020-151455 2020-09-09

Publications (2)

Publication Number Publication Date
TW202226554A TW202226554A (zh) 2022-07-01
TWI800845B true TWI800845B (zh) 2023-05-01

Family

ID=80470064

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110120650A TWI800845B (zh) 2020-09-09 2021-06-07 半導體裝置及其製造方法

Country Status (4)

Country Link
US (1) US20220077184A1 (zh)
JP (1) JP7502122B2 (zh)
CN (1) CN114242727A (zh)
TW (1) TWI800845B (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201605024A (zh) * 2014-07-17 2016-02-01 愛思開海力士有限公司 非易失性記憶體裝置的單位單元、非易失性記憶體裝置的單元陣列及製造其之方法
TW201803030A (zh) * 2014-01-10 2018-01-16 東芝記憶體股份有限公司 半導體記憶體裝置及其製造方法
US20180190667A1 (en) * 2016-10-12 2018-07-05 Sandisk Technologies Llc Select transistors with tight threshold voltage in 3d memory
TW201836072A (zh) * 2017-03-16 2018-10-01 日商東芝記憶體股份有限公司 半導體記憶體
TW201836128A (zh) * 2017-03-17 2018-10-01 旺宏電子股份有限公司 具有分層的導體的三維記憶體裝置
US20190074292A1 (en) * 2009-07-06 2019-03-07 Samsung Electronics Co., Ltd. Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device
TW201941407A (zh) * 2018-03-20 2019-10-16 日商東芝記憶體股份有限公司 半導體記憶裝置及半導體記憶裝置之製造方法
US20200020702A1 (en) * 2018-07-16 2020-01-16 Samsung Electronics Co., Ltd. Semiconductor memory device, semiconductor device, and method of manufacturing semiconductor device
US20200098779A1 (en) * 2018-09-20 2020-03-26 Sunrise Memory Corporation Staircase Structures for Electrically Connecting Multiple Horizontal Conductive Layers of a 3-Dimensional Memory Device
TW202013684A (zh) * 2018-09-20 2020-04-01 日商東芝記憶體股份有限公司 半導體記憶裝置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120060480A (ko) * 2010-12-02 2012-06-12 삼성전자주식회사 수직 구조의 비휘발성 메모리 소자, 반도체 소자 및 시스템
US8902657B2 (en) * 2012-09-07 2014-12-02 Kabushiki Kaisha Toshiba Semiconductor memory device and controller
JP2015177002A (ja) 2014-03-14 2015-10-05 株式会社東芝 半導体記憶装置
US9455263B2 (en) * 2014-06-27 2016-09-27 Sandisk Technologies Llc Three dimensional NAND device with channel contacting conductive source line and method of making thereof
US9991272B2 (en) 2016-09-13 2018-06-05 Toshiba Memory Corporation Semiconductor memory device
JP2018142654A (ja) * 2017-02-28 2018-09-13 東芝メモリ株式会社 半導体装置及びその製造方法
KR102644525B1 (ko) 2018-11-07 2024-03-07 삼성전자주식회사 수직형 반도체 소자
JP2020141008A (ja) 2019-02-27 2020-09-03 キオクシア株式会社 半導体記憶装置及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190074292A1 (en) * 2009-07-06 2019-03-07 Samsung Electronics Co., Ltd. Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device
TW201803030A (zh) * 2014-01-10 2018-01-16 東芝記憶體股份有限公司 半導體記憶體裝置及其製造方法
TW201605024A (zh) * 2014-07-17 2016-02-01 愛思開海力士有限公司 非易失性記憶體裝置的單位單元、非易失性記憶體裝置的單元陣列及製造其之方法
US20180190667A1 (en) * 2016-10-12 2018-07-05 Sandisk Technologies Llc Select transistors with tight threshold voltage in 3d memory
TW201836072A (zh) * 2017-03-16 2018-10-01 日商東芝記憶體股份有限公司 半導體記憶體
TW201836128A (zh) * 2017-03-17 2018-10-01 旺宏電子股份有限公司 具有分層的導體的三維記憶體裝置
TW201941407A (zh) * 2018-03-20 2019-10-16 日商東芝記憶體股份有限公司 半導體記憶裝置及半導體記憶裝置之製造方法
US20200020702A1 (en) * 2018-07-16 2020-01-16 Samsung Electronics Co., Ltd. Semiconductor memory device, semiconductor device, and method of manufacturing semiconductor device
US20200098779A1 (en) * 2018-09-20 2020-03-26 Sunrise Memory Corporation Staircase Structures for Electrically Connecting Multiple Horizontal Conductive Layers of a 3-Dimensional Memory Device
TW202013684A (zh) * 2018-09-20 2020-04-01 日商東芝記憶體股份有限公司 半導體記憶裝置

Also Published As

Publication number Publication date
CN114242727A (zh) 2022-03-25
JP2022045717A (ja) 2022-03-22
US20220077184A1 (en) 2022-03-10
JP7502122B2 (ja) 2024-06-18
TW202226554A (zh) 2022-07-01

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