TWI891349B - Resonant power converter and control method thereof - Google Patents

Abstract

A resonant power converter includes a resonant capacitor, a transformer, a high-side transistor, a low-side transistor, a divider, a full-wave rectifying device, a control circuit, and a regulator. The resonant capacitor is coupled between a resonant node and a ground. The transformer includes a primary winding coupled between a switch node and the resonant node and a secondary winding. The high-side transistor provides an input voltage to the switch node and the low-side transistor couples the switch node to the ground. The divider divides a voltage of the resonant node to generate a dividing signal. The full-wave rectifying device full-wave rectifies the dividing signal to generate a rectified signal. The control circuit compares the rectified signal and a feedback voltage related to an output voltage to drive the high-side transistor and the low-side transistor. The regulator is coupled to the secondary winding and generates the output voltage.

Description

Resonant power conversion circuit and control method thereof

The present invention relates to a resonant power conversion circuit and a control method thereof, and more particularly to a resonant power conversion circuit and a control method thereof that controls a high-side transistor and a low-side transistor by using a rectified signal generated by full-wave rectification and a signal related to the voltage across a resonant capacitor and a feedback voltage.

With the continuous growth of portable electronic devices, power conversion circuits, like most power products, are trending towards high efficiency, high power density, high reliability, and low cost. Resonant power conversion circuits (including LLC resonant power conversion circuits) have seen increasing adoption in DC converters in recent years due to their advantages, such as achieving zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) in the secondary-side rectifier diodes across the full load range. Frequency control allows for a 50% duty cycle for both the high-side and low-side transistors, eliminating the need for an output inductor and enabling the use of lower-voltage transistors on the secondary side, reducing cost and improving efficiency.

However, in reality, the duty cycles of the upper and lower bridge transistors are not each 50% or 50%, resulting in uneven current transfer to the secondary side and reduced conversion efficiency. Therefore, it is necessary to improve the balancing of the duty cycles of the upper and lower bridge transistors.

In view of this, the present invention proposes a resonant power conversion circuit, comprising a resonant capacitor, a transformer, a high-bridge transistor, a low-bridge transistor, a first voltage divider circuit, a full-wave rectifier, a control circuit, a rectifier circuit, and a feedback circuit. The resonant capacitor is coupled between a resonant node and a ground terminal. The transformer comprises a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and the resonant node. The high-bridge transistor provides an input voltage to the switching node based on an high-bridge drive signal. The low-bridge transistor couples the switching node to the ground terminal based on a low-bridge drive signal. The first voltage divider circuit divides the voltage at the resonant node to generate a divided voltage signal. The full-wave rectifier device full-wave rectifies the divided voltage signal generated by the first voltage divider circuit to generate a rectified signal. The control circuit compares the rectified signal with a feedback voltage to generate the upper bridge drive signal and the lower bridge drive signal. The rectifier circuit is coupled to the secondary coil and converts the current flowing through the secondary coil into an output voltage. The feedback circuit generates the feedback voltage based on the output voltage.

According to one embodiment of the present invention, the full-wave rectifier generates the rectified signal by full-wave rectifying the divided signal using a base voltage as the DC level. The base voltage is equal to the sum of a divided voltage and an offset voltage, where the divided voltage is equal to the input voltage divided and multiplied by a first ratio. The full-wave rectifier further compares the rectified signal with a first threshold voltage slightly greater than the base voltage to generate a crossover signal.

According to one embodiment of the present invention, when the rectified signal is less than the first threshold voltage, the full-wave rectifier sets the cross signal to a disabled state. When the rectified signal exceeds the first threshold voltage, the full-wave rectifier sets the cross signal to an enabled state. In response to the cross signal changing from the disabled state to the enabled state, the control circuit sets a phase signal to the enabled state. In response to the full-wave rectified signal exceeding the feedback voltage, the control circuit sets the phase signal to the disabled state based on a load dead time signal or a load dead time signal. The upper bridge dead band time signal controls the upper bridge dead band time of one of the upper bridge drive signals, and the lower bridge dead band time signal controls the lower bridge dead band time of one of the lower bridge drive signals.

According to one embodiment of the present invention, when the upper bridge drive signal turns on the upper bridge transistor and the phase signal is in the enabled state, the control circuit disables the upper bridge drive signal in response to the rectified signal exceeding the feedback voltage. When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge drive signal after the lower bridge dead band time to turn on the lower bridge transistor. When the lower bridge drive signal turns on the lower bridge transistor and the phase signal is in the enabled state, the control circuit disables the lower bridge drive signal in response to the rectified signal exceeding the feedback voltage. When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal after the upper bridge dead time to turn on the upper bridge transistor.

According to one embodiment of the present invention, the control circuit further limits the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal to no more than a maximum enable cycle.

According to one embodiment of the present invention, the offset voltage is determined based on the difference between the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal. The offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal is close to the enable period of the lower bridge drive signal.

According to one embodiment of the present invention, the resonant power conversion circuit further includes a second voltage divider circuit. The second voltage divider circuit is used to divide the input voltage to generate the divided voltage. The full-wave rectifier device includes a first resistor, a first current source, and an automatic adjustment circuit. The first resistor is coupled between the divided voltage and the base voltage, wherein the voltage across the first resistor generates the offset voltage. The first current source provides a first current to the base voltage. The automatic adjustment circuit extracts an adjustment current from the base voltage based on the upper bridge drive signal, the lower bridge drive signal, the upper bridge dead time signal, and the lower bridge dead time signal.

According to one embodiment of the present invention, in response to the first current being greater than the adjusted current, the offset voltage is positive, and the base voltage is greater than the divided voltage. In response to the first current being less than the adjusted current, the offset voltage is negative, and the base voltage is less than the divided voltage. In response to the first current being equal to the adjusted current, the base voltage is equal to the divided voltage.

According to one embodiment of the present invention, the automatic adjustment circuit includes a time-to-voltage conversion circuit. The time-to-voltage conversion circuit is configured to convert the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal into an upper bridge enable cycle voltage and a lower bridge enable cycle voltage, respectively. The time-to-voltage conversion circuit includes a second current source, a first switch, a second switch, a first capacitor, a second capacitor, a third capacitor, a third switch, and a fourth switch. The second current source provides a second current. The first switch provides the second current to a charging node based on the enabled upper bridge drive signal or the enabled lower bridge drive signal. During the upper bridge dead band time and the lower bridge dead band time, the second switch couples the charging node to the ground terminal. The first capacitor is coupled between the charging node and the ground terminal. The second capacitor is coupled between an upper bridge enable cycle voltage and the ground terminal. The third capacitor is coupled between a lower bridge enable cycle voltage and the ground terminal. The third switch couples the charging node to the upper bridge enable cycle voltage based on the upper bridge drive signal being enabled. The fourth switch couples the charging node to the lower bridge enable cycle voltage based on the lower bridge drive signal being enabled. The upper bridge enable cycle voltage represents the enable cycle of the upper bridge drive signal, and the lower bridge enable cycle voltage represents the enable cycle of the lower bridge drive signal.

According to one embodiment of the present invention, the automatic adjustment circuit further includes a comparison circuit, a plurality of registers, a counter, and a digital-to-analog converter. The comparison circuit compares the upper bridge enable cycle voltage and the lower bridge enable cycle voltage to generate an up-count signal and a down-count signal. The register is used to latch the up-count signal and the down-count signal during the upper bridge dead band time and the lower bridge dead band time. The counter counts up a digital code based on the enabled up-count signal and counts down the digital code based on the enabled down-count signal. The digital-to-analog converter generates the adjustment current based on the digital code. When the upper bridge enable cycle voltage is greater than the lower bridge enable cycle voltage, the comparison circuit enables the up-count signal and disables the down-count signal. When the upper bridge enable cycle voltage is not greater than the lower bridge enable cycle voltage, the comparison circuit disables the up-count signal and enables the down-count signal.

According to one embodiment of the present invention, the feedback voltage decreases in response to an increase in the output voltage. In response to the feedback voltage falling below a low-power threshold voltage, a lower bridge dead-band timing signal enables a burst signal, causing the control circuit to operate in a burst mode based on the enabled burst signal. When the control circuit operates in the burst mode, both the upper bridge transistor and the lower bridge transistor are non-conductive. The duration of the burst mode increases as the output power of the output voltage decreases.

According to one embodiment of the present invention, the control circuit includes a first amplifier, a second amplifier, a second resistor, an N-type transistor, and a current mirror. The first amplifier includes a first positive input, a first negative input, and a first output, wherein the first positive input receives the feedback voltage, and the first negative input is coupled to the first output. The second amplifier includes a second positive input, a second negative input, and a second output, wherein the second positive input receives a feedback threshold voltage. The second resistor is coupled between the second negative input and the first output to generate a differential current. The N-type transistor includes a gate, a drain, and a source. The gate is coupled to the second output, and the source is coupled to the second negative input. The current mirror maps the differential current into a mirrored current. The feedback threshold voltage is the lower limit of the feedback voltage, and the mirrored current is used to adjust the duration.

The present invention further provides a control method for controlling a resonant power conversion circuit. The resonant power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, a high-bridge transistor that provides an input voltage to a switching node, a low-bridge transistor that couples the switching node to the ground terminal, a rectifier circuit that converts current flowing through the secondary coil into an output voltage, and a feedback circuit that generates a feedback voltage based on the output voltage. The primary coil is coupled between the switching node and the resonant node. The control method includes: utilizing a first voltage divider circuit to divide the voltage across the resonant capacitor to generate a divided signal; full-wave rectifying the divided signal to generate a rectified signal; and comparing the rectified signal with the feedback voltage to drive the upper and lower bridge transistors.

According to one embodiment of the present invention, the control method further includes: performing full-wave rectification on the divided signal using a base voltage as a DC level to generate the rectified signal; and comparing the rectified signal with a first threshold voltage to generate a crossover signal. The base voltage is equal to the sum of a divided voltage and an offset voltage. The divided voltage is equal to the input voltage multiplied by a first ratio, and the first threshold voltage is slightly greater than the base voltage.

According to one embodiment of the present invention, the control method further includes: setting the cross signal to a disabled state when the rectified signal is less than the first threshold voltage; setting the cross signal to an enabled state when the rectified signal exceeds the first threshold voltage; setting a phase signal to the enabled state in response to the cross signal changing from the disabled state to the enabled state; and setting the phase signal to the disabled state during an upper bridge dead band time or a lower bridge dead band time in response to the full-wave rectified signal exceeding the feedback voltage. The lower bridge dead band time is the time between the time when the upper bridge transistor turns off and the time when the lower bridge transistor turns on. The upper bridge dead time is the time between the lower bridge transistor turning off and the upper bridge transistor turning on.

According to one embodiment of the present invention, the control method further includes: when the upper transistor is conductive and the phase signal is in the enabled state, in response to the rectified signal exceeding the feedback voltage, turning off the upper transistor; when the upper transistor is not conductive, turning on the lower transistor after the lower dead time; when the lower transistor is conductive and the phase signal is in the enabled state, in response to the rectified signal exceeding the feedback voltage, turning off the lower transistor; and when the lower transistor is not conductive, turning on the upper transistor after the upper dead time.

According to one embodiment of the present invention, the control method further includes limiting the enable cycle of the upper bridge transistor and the enable cycle of the lower bridge transistor to no more than a maximum enable cycle.

According to one embodiment of the present invention, the control method further includes determining the offset voltage based on the difference between the enable period of the upper bridge transistor and the enable period of the lower bridge transistor. The offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal is close to the enable period of the lower bridge drive signal.

According to one embodiment of the present invention, the control method further includes: generating the offset voltage by a voltage across a first resistor, wherein the first resistor is coupled between the divided voltage and the base voltage; providing a first current to flow to the base voltage; and automatically adjusting the voltage by an automatic adjustment circuit based on whether the upper bridge transistor and the lower bridge transistor are conducting or not conducting, the upper bridge dead time, and the lower bridge dead time. The base voltage extracts a regulated current; in response to the first current being greater than the regulated current, the offset voltage is positive and the base voltage is greater than the divided voltage; in response to the first current being less than the regulated current, the offset voltage is negative and the base voltage is less than the divided voltage; and in response to the first current being equal to the regulated current, the base voltage is equal to the divided voltage.

According to one embodiment of the present invention, the step of extracting the regulated current from the basic voltage using the automatic regulating circuit based on the conduction and non-conduction of the upper bridge transistor and the lower bridge transistor, the upper bridge dead time, and the lower bridge dead time further includes: using a time-to-voltage conversion circuit to convert the conduction time of the upper bridge transistor into an upper bridge enable cycle voltage; using the time-to-voltage conversion circuit to , converting the conduction time of the lower bridge transistor into a lower bridge enable cycle voltage; comparing the upper bridge enable cycle voltage and the lower bridge enable cycle voltage to generate an up signal and a down signal; increasing the adjustment current when the upper bridge enable cycle voltage is greater than the lower bridge enable cycle voltage; and reducing the adjustment current when the upper bridge enable cycle voltage is not greater than the lower bridge enable cycle voltage.

According to one embodiment of the present invention, the control method further includes: in response to the feedback voltage being lower than a low-power threshold voltage, operating in a burst mode, wherein the feedback voltage decreases in response to an increase in the output voltage; in the burst mode, simultaneously turning off the high-side transistor and the low-side transistor; and increasing a duration of the burst mode in response to a decrease in the output power of the output voltage.

According to one embodiment of the present invention, the control method further includes: limiting the feedback voltage to no greater than a feedback threshold voltage; generating a differential current using a second resistor, the feedback voltage, and the feedback threshold voltage; mapping the differential current into a mapped current; and adjusting the duration using the mapped current.

100: Resonant power conversion circuit

110: Upper bridge transistor

120: Lower bridge transistor

130: First voltage divider circuit

140,200: Full-wave rectifier

150,500: Control circuit

160: Level shift circuit

170: Rectifier circuit

180: Feedback circuit

190: Second voltage divider circuit

TM: Transformer

LR: Resonant Inductor

CR: Resonance Capacitor

HSD: High-side drive circuit

LSD: Lower Drive Circuit

PS: Beginner coil

SS: Secondary coil

NR: Resonance Node

SW: Switch Node

HSG: High-side gate drive signal

LSG: Lower Gate Drive Signal

VIN: Input voltage

SD: voltage division signal

C1: First capacitor

C2: Second capacitor

R1: First resistor

R2: Second resistor

FW: Rectified signal

SZ: Cross signal

COUT: output capacitance

FB: Feedback voltage

HS: Upper bridge drive signal

LS: Lower bridge drive signal

D1: First rectifier element

D2: Second rectifier element

VOUT: output voltage

R3: The third resistor

R4: The fourth resistor

DR: Voltage Regulator

PD: Photocoupler

R5: The fifth resistor

R6: Sixth resistor

LED: diode

Q: Transistor

VCC: supply voltage

R7: Seventh resistor

R8: Eighth resistor

VD1: First divided voltage

VD2: Second divided voltage

210: Full-wave rectifier

220: Bias circuit

221: Automatic adjustment circuit

CMP1: First comparator

R9: Ninth resistor

R10: Tenth resistor

R11: Eleventh resistor

R12: 12th resistor

R13: Thirteenth resistor

AMP1: First amplifier

AMP2: Second amplifier

D3: The third diode

D4: Fourth Diode

VT1: First threshold voltage

AMP3: Third amplifier

CS1: First current source

R14: Fourteenth resistor

I1: First current

VBS: Base voltage

CK_H: Bridge dead time signal

CK_L: Downbridge dead zone time signal

ID: Adjust current

VOS: offset voltage

DC: Direct current level

400: Compensation circuit

AMP4: Fourth amplifier

AMP5: Fifth amplifier

R15: Fifteenth resistor

MN1: First N-type transistor

CM1: First Current Mirror

VTC: Feedback Threshold Voltage

INP4: Fourth positive input terminal

INN4: Fourth negative input terminal

O4: Fourth output port

INP5: Fifth positive input terminal

INN5: Fifth negative input terminal

O5: Fifth output port

IDIFF: differential current

IB: Mapping Current

G: Gate terminal

D: Drain terminal

S: Source

FF1: First Flip-Flop

AND1: First AND gate

SE: Phase signal

CMP2: Second comparator

AND2: Second AND gate

OR1: First OR gate

OR2: Second OR gate

DT1: First dead time generator

DT2: Second dead time generator

FF2: Second flip-flop

FF3: Third Flip-Flop

AND3: Third AND gate

AND4: Fourth and Gate

AND5: Fifth and Gate

AND6: Sixth and Gate

dHS: Delayed bridge drive signal

IHS: Initial Hit-Speed Drive Signal

dLS: Delayed lower bridge drive signal

ILS: Initial Lower Link Drive Signal

IX: First current adjustment

IY: Second adjustment current

INV1: First inverter

INV2: Second inverter

501: First cycle limit circuit

502: Second cycle limit circuit

600: Waveform

T1: First time

T2: Second Time

T3: The third time

T4: The Fourth Time

700: Delay time generator

INV3: Third inverter

MN2: Second N-type transistor

C3: The third capacitor

CS2: Second current source

CS3: Third current source

CM2: Second current mirror

CMP3: Third comparator

IN: Input signal

VCAP1: First capacitor voltage

I2: Second current

I3: Third current

I4: Fourth current

I5: Fifth current

I6: Sixth current

I7: Seventh Current

VT2: Second threshold voltage

OUT: output signal

IA: Input current

800: Time-to-voltage conversion circuit

CS4: Fourth current source

OR3: Third OR Gate

SW1: First switch

SW2: Second switch

SW3: Third switch

SW4: Fourth switch

NAND1: First NAND Gate

C4: Fourth capacitor

C5: Fifth capacitor

C6: Sixth capacitor

VDH: Upper bridge enable cycle voltage

VDL: Lower bridge enable cycle voltage

900: Automatic adjustment circuit

910: Comparison Circuits

920: Signal generation circuit

FF4: Fourth Flip-Flop

FF5: The Fifth Flip-Flop

930:Counter

940: Digital-to-Analog Converter

UP: Upward signal

DWN: Downward signal

LTH: latch signal

CLK: clock signal

B:Digital code

CMP4: Fourth comparator

CMP5: Fifth Comparator

INV4: Fourth inverter

INV5: Fifth inverter

AND7: Seventh and Gate

AND8: The Eighth and Gate

AND9: Ninth and Gate

LUP: Latch Up Digital Signal

LDWN: latch down signal

CS5: Fifth Current Source

C7: Seventh capacitor

VCAP2: Second capacitor voltage

1000: Output voltage detection circuit

1010: Delay circuit

CMP6: Sixth Comparator

NAND2: Second NAND Gate

FF6: The Sixth Flip-Flop

INV6: Sixth inverter

VTLP: Threshold Voltage for Low Power

CP: Comparative Signal

SB: anti-phase burst signal

BST: Burst Signal

ST: Reset signal

1100: Control Method

S1110~S1130: Step Flow

FIG1 is a block diagram of a resonant power conversion circuit according to an embodiment of the present invention; FIG2 is a block diagram of a full-wave rectifier according to an embodiment of the present invention; FIG3 is a waveform diagram of a rectified signal and a divided voltage signal according to an embodiment of the present invention; FIG4 is a block diagram of a compensation circuit according to an embodiment of the present invention; FIG5 is a block diagram of a control circuit according to an embodiment of the present invention; FIG6 is a block diagram of a control circuit according to an embodiment of the present invention. FIG7 is a waveform diagram showing a dead time generator according to an embodiment of the present invention; FIG8 is a schematic diagram showing a time-to-voltage conversion circuit according to an embodiment of the present invention; FIG9 is a schematic diagram showing an automatic adjustment circuit according to an embodiment of the present invention; FIG10 is a block diagram showing an output voltage detection circuit according to an embodiment of the present invention; and FIG11 is a flow chart showing a control method for controlling a resonant power conversion circuit according to an embodiment of the present invention.

The following descriptions are examples of embodiments of the present disclosure. They are intended to illustrate the general principles of the present disclosure and should not be construed as limiting the scope of the present disclosure, which is defined by the scope of the patent application.

It is important to note that the following disclosure provides multiple embodiments or examples for implementing various features of the present disclosure. The specific component examples and arrangements described below are intended only to briefly illustrate the spirit of the present disclosure and are not intended to limit the scope of the present disclosure. Furthermore, the following description may reuse the same component symbols or text in multiple examples. However, this reuse is intended solely to simplify and clarify the description and is not intended to limit the relationship between the various embodiments and/or configurations discussed below.

Furthermore, descriptions in the following description of a feature being connected to, coupled to, and/or formed on another feature may actually include a variety of different embodiments, including those features being directly in contact, or including additional features formed between those features, so that the features are not in direct contact.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It will be understood that if the device in the drawings is turned upside down, the element described as being on the "lower" side would become the element on the "upper" side.

It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts should not be limited by these terms, and these terms are merely used to distinguish one element, component, region, layer, and/or part from another. Thus, a first element, component, region, layer, and/or part discussed below could be referred to as a second element, component, region, layer, and/or part without departing from the teachings of some embodiments of the present disclosure.

Some embodiments of this disclosure can be understood in conjunction with the accompanying drawings, which are considered part of the description of the disclosed embodiments. It should be understood that the drawings of the disclosed embodiments are not drawn to scale relative to actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly illustrate the features of the disclosed embodiments. Furthermore, the structures and devices in the drawings are schematically depicted to clearly illustrate the features of the disclosed embodiments.

Herein, the terms "about," "approximately," and "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given herein are approximate quantities, meaning that even without the specific wording "about," "approximately," or "substantially," the meaning of "about," "approximately," or "substantially" is implied.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, unless otherwise specified, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure positioned between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed.

In the drawings, similar components and/or features may have the same reference numerals. Components of the same type may be distinguished by adding a letter or number after the reference numeral to distinguish similar components and/or similar features.

FIG1 is a block diagram of a resonant power conversion circuit according to one embodiment of the present invention. As shown in FIG1 , the resonant power conversion circuit 100 includes a transformer TM, a resonant inductor LR, a resonant capacitor CR, a high-side transistor 110, a low-side transistor 120, a first voltage divider circuit 130, a full-wave rectifier 140, a control circuit 150, a level shifter circuit 160, a high-side driver circuit HSD, a low-side driver circuit LSD, a rectifier circuit 170, and a feedback circuit 180.

The transformer TM includes a primary coil PS and a secondary coil SS, wherein the primary coil PS is coupled to a resonance node NR. A resonant inductor LR is coupled between a switching node SW and the primary coil PS, and a resonant capacitor CR is coupled between the resonant node NR and ground. According to one embodiment of the present invention, the resonant inductor LR can be replaced by the leakage inductance of the primary coil PS of the transformer TM. In other words, the primary coil PS can be coupled between the switching node SW and the resonance node NR.

The high-gate drive signal HSG turns high-side transistor 110 on and off, providing input voltage VIN to switching node SW. The low-gate drive signal LSG turns low-side transistor 120 on and off, coupling switching node SW to ground. The first voltage divider circuit 130 divides the voltage at resonant node NR to generate a divided voltage signal SD. In other words, the first voltage divider circuit 130 divides the voltage across resonant capacitor CR to generate the divided voltage signal SD.

According to one embodiment of the present invention, the first voltage divider circuit 130 may be composed of a first capacitor C1 and a second capacitor C2. According to another embodiment of the present invention, the first voltage divider circuit 130 may be composed of a first resistor R1 and a second resistor R2. According to other embodiments of the present invention, the first voltage divider circuit 130 may include a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. In the embodiment of FIG. 1 , the voltage at the resonance node NR is divided by the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 for illustrative purposes only, and is not intended to be limiting in any way. According to other embodiments of the present invention, the divided voltage signal SD can be further amplified by an amplifier so that the divided voltage signal SD is close to the voltage of the resonance node NR, or even greater than the voltage of the resonance node NR.

The full-wave rectifier 140 performs full-wave rectification on the divided voltage signal SD to generate a rectified signal FW and a crossover signal SZ. The control circuit 150 compares the rectified signal FW with the feedback voltage FB to generate a high-side drive signal HS and a low-side drive signal LS. The level shifter 160 converts the high-side drive signal HS to the voltage level of the input voltage VIN and generates a high-side gate drive signal HSG via the high-side drive circuit HSD to drive the high-side transistor 110. The lower bridge drive circuit LSD generates a lower bridge gate drive signal LSG based on the lower bridge drive signal LS to drive the lower bridge transistor 120.

Rectifier circuit 170 is coupled to secondary winding SS and is used to convert the current flowing through secondary winding SS into an output voltage VOUT. As shown in Figure 1, rectifier circuit 170 includes a first rectifier element D1, a second rectifier element D2, and an output capacitor COUT. The first rectifier element D1 and the second rectifier element D2 are used to more efficiently charge the output capacitor COUT with the current flowing through secondary winding SS, thereby generating the output voltage VOUT. According to other embodiments of the present invention, the first rectifier element D1 and the second rectifier element D2 can be replaced with electronic components with low on-resistance to further improve conversion efficiency.

Feedback circuit 180 generates a feedback voltage FB based on the output voltage VOUT. As shown in Figure 1, feedback circuit 180 includes a third resistor R3, a fourth resistor R4, a voltage regulator DR, an optocoupler PD, a fifth resistor R5, and a sixth resistor R6. The third resistor R3 and the fourth resistor R4 divide the output voltage VOUT to generate a first divided voltage VD1. Based on the first divided voltage VD1, the voltage regulator DR generates a current flowing through the diode LED of the optocoupler PD, causing the diode LED to emit light, which in turn turns on the transistor Q of the optocoupler PD through optical coupling.

The fifth resistor R5 is used to limit the current flowing through the diode LED. The supply voltage VDD generates the feedback voltage FB through the sixth resistor R6 and the conductive transistor Q. According to one embodiment of the present invention, the voltage regulator element DR can be a TL431. According to some embodiments of the present invention, as the output voltage VOUT increases, the feedback voltage FB decreases accordingly. According to other embodiments of the present invention, as the output voltage VOUT decreases, the feedback voltage FB increases accordingly.

As shown in Figure 1, the resonant power conversion circuit 100 further includes a second voltage divider circuit 190. The second voltage divider circuit 190 includes a seventh resistor R7 and an eighth resistor R8. The second voltage divider circuit 190 is used to divide the input voltage VIN to generate a second divided voltage VD2. According to one embodiment of the present invention, the second divided voltage VD2 is equal to the input voltage VIN multiplied by a first ratio, where the first ratio is less than 1. The control method of the resonant power conversion circuit 100 will be described in detail below.

FIG2 is a block diagram of a full-wave rectifier according to one embodiment of the present invention. According to one embodiment of the present invention, the full-wave rectifier 200 in FIG2 corresponds to the full-wave rectifier 140 in FIG1 . As shown in FIG2 , the full-wave rectifier 200 includes a full-wave rectifier 210, a first comparator CMP1, and a bias circuit 220. The full-wave rectifier 210 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first amplifier AMP1, a twelfth resistor R12, a thirteenth resistor R13, a third diode D3, a fourth diode D4, and a second amplifier AMP2. The full-wave rectifier 210 uses the base voltage VBS as the DC level to perform full-wave rectification on the divided signal SD generated by the first divider circuit 130 to generate a rectified signal FW.

The first comparator CMP1 compares the rectified signal FW with a first threshold voltage VT1 to generate a cross signal SZ. According to one embodiment of the present invention, the first threshold voltage VT1 is slightly greater than the base voltage VBS. According to one embodiment of the present invention, when the rectified signal FW is less than the first threshold voltage VT1, the first comparator CMP1 disables the cross signal SZ. According to another embodiment of the present invention, when the rectified signal FW exceeds the first threshold voltage VT1, the first comparator CMP1 enables the cross signal SZ.

The bias circuit 220 includes a third amplifier AMP3, a first current source CS1, a fourteenth resistor R14, and an automatic adjustment circuit 221. As shown in Figure 2, the positive input of the third amplifier AMP3 receives the second divided voltage VD2, and the third amplifier AMP3 is coupled as a unity-gain buffer, so that the voltage at the output of the third amplifier AMP3 is equal to the second divided voltage VD2. The first current source CS1 provides a first current I1 to flow to the base voltage VBS, and the fourteenth resistor R14 is coupled between the base voltage VBS and the output of the third amplifier AMP3.

The automatic adjustment circuit 221 extracts an adjustment current ID from the base voltage VBS based on the upper bridge drive signal HS, the lower bridge drive signal LS, the upper bridge dead-band timing signal CK_H, and the lower bridge dead-band timing signal CK_L. The automatic adjustment circuit 221, the upper bridge dead-band timing signal CK_H, and the lower bridge dead-band timing signal CK_L are described in detail below. According to one embodiment of the present invention, the base voltage VBS is equal to the sum of the second divided voltage VD2 and the offset voltage VOS.

According to one embodiment of the present invention, when the first current I1 is greater than the adjusted current ID, the offset voltage VOS is positive, and the base voltage VBS is greater than the second divided voltage VD2. According to another embodiment of the present invention, when the first current I1 is less than the adjusted current ID, the offset voltage VOS is negative, and the base voltage VBS is less than the second divided voltage VD2. According to another embodiment of the present invention, when the first current I1 is equal to the adjusted current ID, the base voltage VBS is equal to the second divided voltage VD2. According to another embodiment of the present invention, when the first current I1 is equal to the adjustment current ID, the offset voltage VOS is zero, and the base voltage VBS is equal to the second divided voltage VD2.

FIG3 shows waveforms of a rectified signal and a divided voltage signal according to an embodiment of the present invention. As shown in FIG3 , the divided voltage signal SD has a DC level DC. The full-wave rectifier 210 performs full-wave rectification on the divided voltage signal SD using the base voltage VBS as the DC level, generating a rectified signal FW. Next, the first comparator CMP1 compares the rectified signal FW with the first threshold voltage VT1 to generate a crossover signal SZ. As shown in FIG3 , when the rectified signal FW is less than the first threshold voltage VT1, the first comparator CMP1 disables the crossover signal SZ.

FIG4 is a block diagram of a compensation circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the control circuit 150 of FIG1 includes a compensation circuit 400. As shown in FIG4 , the compensation circuit 400 includes a fourth amplifier AMP4, a fifth amplifier AMP5, a fifteenth resistor R15, a first N-type transistor MN1, and a first current mirror CM1. The compensation circuit 400 is configured to generate a compensation voltage COMP based on the feedback voltage FB and to limit the compensation voltage COMP to no less than the feedback threshold voltage VTC. In other words, the compensation voltage COMP generated by compensation circuit 400 is equal to the feedback voltage FB, and the minimum value of compensation voltage COMP is limited to the feedback threshold voltage VTC.

The fourth amplifier AMP4 includes a fourth positive input terminal INP4, a fourth negative input terminal INN4, and a fourth output terminal O4. The fourth positive input terminal INP4 receives a feedback voltage FB, and the fourth negative input terminal INN4 is coupled to the fourth output terminal O4. The fifth amplifier AMP5 includes a fifth positive input terminal INP5, a fifth negative input terminal INN5, and a fifth output terminal O5. The fifth positive input terminal INP5 receives a feedback threshold voltage VTC. According to one embodiment of the present invention, the fourth amplifier AMP4 is coupled as a unity-gain amplifier, so the voltage at the fourth output terminal O4 is equal to the feedback voltage FB.

The fifteenth resistor R15 is coupled between the fifth negative input terminal INN5 and the fourth output terminal O4 and generates a differential current IDIFF. The first N-type transistor MN1 includes a gate terminal G, a drain terminal D, and a source terminal S. The gate terminal G is coupled to the fifth output terminal O5, and the source terminal S is coupled to the fifth negative input terminal INN5 and generates a compensation voltage COMP. The first current mirror CM1 is coupled to the drain terminal D and maps the differential current IDIFF into a mapped current IB. According to some embodiments of the present invention, the mapped current IB is N times the differential current IDIFF, where N is the mapping magnification of the first current mirror CM1.

According to one embodiment of the present invention, when the feedback voltage FB is less than the feedback threshold voltage VTC, the difference between the feedback threshold voltage VTC and the feedback voltage FB and the resistance value of the fifteenth resistor R15 generates a differential current IDIFF, which is mapped into a mirrored current IB via the first current mirror CM1. The compensation voltage COMP is equal to the feedback threshold voltage VTC. According to another embodiment of the present invention, when the feedback voltage FB is greater than or equal to the feedback threshold voltage VTC, the fifth amplifier AMP5 turns off the first N-type transistor MN1, so that the first current mirror CM1 does not generate the mirrored current IB, and the compensation voltage COMP is equal to the feedback voltage FB.

In other words, when the feedback voltage FB is less than the feedback threshold voltage VTC, the compensation voltage COMP equals the feedback threshold voltage VTC, and a corresponding mirrored current IB is generated. When the feedback voltage FB is not less than the feedback threshold voltage VTC, the compensation voltage COMP equals the feedback voltage FB, and no mirrored current IB is generated. The function of the mirrored current IB will be explained in detail below.

FIG5 is a block diagram of a control circuit according to one embodiment of the present invention. As shown in FIG5 , the control circuit 500 includes a first flip-flop FF1 and a first AND gate AND1. The first flip-flop FF1 outputs the supply voltage VCC as the phase signal SE (i.e., sets the phase signal SE to the enabled state) based on a positive signal edge of the cross signal SZ (i.e., when the cross signal SZ changes from a disabled state to an enabled state). According to some embodiments of the present invention, the cross signal SZ is disabled at a low logic level and enabled at a high logic level. In other words, when the rectified signal FW increases and exceeds the first threshold voltage VT1, the phase signal SE is enabled.

The first flip-flop FF1 further disables the phase signal SE based on the disabled state (i.e., low logic level) of the upper bridge dead-band time signal CK_H or the lower bridge dead-band time signal CK_L. In other words, the phase signal SE is disabled during the upper bridge dead-band time and the lower bridge dead-band time. As shown in Figure 5, the control circuit 500 further includes a second comparator CMP2, a second AND gate AND2, a first OR gate OR1, a first dead-time generator DT1, a second flip-flop FF2, and a third AND gate AND3.

When the rectified signal FW exceeds the compensation voltage COMP generated by the compensation circuit 400, the delayed high-bridge drive signal dHS is enabled, and the phase signal SE is enabled, the second AND gate AND2 and the first OR gate OR1 trigger the first dead-time generator DT1 to generate a negative pulse on the lower-bridge dead-time signal CK_L. This, in turn, disables the upper-bridge drive signal HS via the third AND gate AND3, thereby turning off the upper-bridge transistor 110 in FIG1 . Furthermore, the negative pulse of the lower-bridge dead-time signal CK_L resets the second flip-flop FF2, disabling the delayed high-bridge drive signal dHS. According to one embodiment of the present invention, the width of the negative pulse of the lower bridge dead time signal CK_L is used to determine the lower bridge dead time of the lower bridge transistor 120. According to one embodiment of the present invention, the first adjustment current IX is used to adjust the length of the lower bridge dead time.

As shown in Figure 5, the control circuit 500 further includes a first inverter INV1, a fourth AND gate AND4, a third flip-flop FF3, a fifth AND gate AND5, a second OR gate OR2, a second dead-time generator DT2, and a sixth AND gate AND6. The first inverter INV1 inverts the disabled delayed upper bridge drive signal dHS and enables the initial upper bridge drive signal IHS. When the lower bridge dead-time signal CK_L changes from a disabled state (negative pulse) to an enabled state and the burst signal BST is enabled, the third flip-flop FF3 outputs the enabled initial upper bridge drive signal IHS as the delayed lower bridge drive signal dLS (i.e., enabled).

Next, when the delayed lower bridge drive signal dLS is enabled, the rectified signal FW exceeds the compensation voltage COMP, and the phase signal SE is enabled, the second dead-time generator DT2 is enabled via the fifth AND gate AND5 and the second OR gate OR2 to generate a negative pulse in the upper bridge dead-time signal CK_H. Furthermore, the lower bridge drive signal LS is disabled via the sixth AND gate AND6, thereby turning off the lower bridge transistor 120 in FIG. 1 . Furthermore, the negative pulse of the upper bridge dead-time signal CK_H resets the third flip-flop FF3, disabling the delayed lower bridge drive signal dLS. According to one embodiment of the present invention, the width of the negative pulse of the load dead-time signal CK_H is used to determine the load dead-time of the load transistor 110. According to one embodiment of the present invention, the second adjustment current IY is used to adjust the length of the load dead-time.

As shown in Figure 5 , the control circuit 500 further includes a first cycle limit circuit 501, a second cycle limit circuit 502, and a second inverter INV2. When the enable cycle of the high-bridge drive signal HS exceeds the maximum enable cycle, the first cycle limit circuit 501 issues an enable signal to trigger the first dead-time generator DT1 to generate a negative pulse, resetting (or disabling) the delay high-bridge drive signal dHS, thereby disabling the high-bridge drive signal HS. According to one embodiment of the present invention, during the enable cycle of the high-bridge drive signal HS, the high-bridge transistor 110 is turned on; during the enable cycle of the low-bridge drive signal LS, the low-bridge transistor 120 is turned on.

When the enable cycle of the lower bridge drive signal LS exceeds the maximum enable cycle, the second cycle limit circuit 502 issues an enable signal to trigger the second dead-time generator DT2 to generate a negative pulse, resetting or disabling the delayed lower bridge drive signal dLS, thereby disabling the lower bridge drive signal LS. The second inverter INV2 is used to invert the delayed lower bridge drive signal dLS to generate the initial lower bridge drive signal ILS.

Figure 6 shows a waveform diagram of a control circuit according to one embodiment of the present invention. The following will provide a detailed explanation combining the control circuit 500 in Figure 5 and the waveform diagram 600 in Figure 6.

At the first time T1 in Figure 6, the lower-side drive signal LS is enabled and the rectifier signal FW continues to increase, just exceeding the compensation voltage COMP. As shown in Figure 5, because the rectifier signal FW exceeds the compensation voltage COMP, the output of the second comparator CMP2 triggers the second dead-time generator DT2 to generate a negative pulse in the upper-side dead-time signal CK_H via the fifth AND gate AND5 and the second OR gate OR2. This negative pulse of the upper-side dead-time signal CK_H resets the first flip-flop FF1, disabling the phase signal SE. In addition, the negative pulse of the upper-side dead-time signal CK_H simultaneously disables the lower-side drive signal LS.

According to one embodiment of the present invention, when the upper bridge dead-band timing signal CK_H is disabled, that is, between the first time T1 and the second time T2, the third flip-flop FF3 is reset, disabling the delayed lower bridge drive signal dLS. Furthermore, the disabled delayed lower bridge drive signal dLS stops the second dead-band generator DT2 from further disabling the upper bridge dead-band timing signal CK_H via the fifth AND gate AND5 and the second OR gate OR2, thus ending the upper bridge dead-band timing and reaching the second time T2.

At the second time T2 in Figure 6, the upper bridge dead-band timing signal CK_H pulses back to the enabled state from the negative pulse. That is, the upper bridge dead-band timing signal CK_H generates a positive signal edge at the second time T2, causing the second flip-flop FF2 to output the initially enabled lower bridge drive signal ILS as the delayed upper bridge drive signal dHS, and to enable the upper bridge drive signal HS through the third AND gate AND3.

At the third time T3 in Figure 6, the upper-side drive signal HS remains enabled, and the rectifier signal FW continues to increase, just exceeding the compensation voltage COMP. As shown in Figure 5, as the rectifier signal FW increases and exceeds the compensation voltage COMP, the output of the second comparator CMP2 triggers the first dead-time generator DT1 to generate a negative pulse in the lower-side dead-time signal CK_L via the second AND gate AND2 and the first OR gate OR1. This negative pulse of the lower-side dead-time signal CK_L resets the first flip-flop FF1, disabling the phase signal SE. In addition, the negative pulse of the lower-bridge dead-band time signal CK_L simultaneously passes through the third AND gate AND3, disabling the upper-bridge drive signal HS.

According to one embodiment of the present invention, when the lower-bridge dead-band timing signal CK_L is disabled, the second flip-flop FF2 is reset, disabling the delayed upper-bridge driving signal dHS. The disabled delayed upper-bridge driving signal dHS stops the first dead-band timing generator DT1 from further disabling the lower-bridge dead-band timing signal CK_L via the second AND gate AND2 and the first OR gate OR1, thereby enabling the lower-bridge dead-band timing signal CK_L.

At the fourth time T4 in Figure 6, the lower bridge dead-band timing signal CK_L pulses back to the enabled state from a negative pulse. That is, the lower bridge dead-band timing signal CK_L generates a positive signal edge at the fourth time T4. Combined with the enabled state of the burst signal BST, the third flip-flop FF3 outputs the enabled initial upper bridge drive signal IHS as the delayed lower bridge drive signal dLS, and sets the lower bridge drive signal LS to the enabled state through the sixth AND gate AND6.

FIG7 shows a circuit diagram of a delay time generator according to one embodiment of the present invention. According to one embodiment of the present invention, the delay time generator 700 in FIG7 corresponds to the first dead time generator DT1 and the second dead time generator DT2 in FIG5.

As shown in FIG7 , the delay time generator 700 includes a third inverter INV3, a second N-type transistor MN2, a third capacitor C3, a second current source CS2, a second current mirror CM2, a third current source CS3, and a third comparator CMP3.

When the third inverter INV3 receives a disabled input signal IN, the second N-type transistor MN2 is conductive and couples the first capacitor voltage VCAP1 generated by the third capacitor C3 to ground. When the third inverter INV3 then receives an enabled input signal IN, the second N-type transistor MN2 is non-conductive, and the second current mirror CM2 mirrors the second current I2 generated by the second current source CS2 into a fourth current I4. Adding the third current I3 generated by the third current source CS3 connected in parallel to the second current mirror CM2, the third capacitor C3 is charged by the fifth current I5, generating the first capacitor voltage VCAP1. According to one embodiment of the present invention, the fifth current I5 is the sum of the third current I3 and the fourth current I4.

When the first capacitor voltage VCAP1 exceeds the second threshold voltage VT2, the third comparator CMP3 generates a disabled output signal OUT. When the input signal IN returns to the disabled state, the second N-type transistor MN2 turns on, discharging the first capacitor voltage VCAP1 to ground, causing the output signal OUT generated by the third comparator CMP3 to return to the enabled state. According to one embodiment of the present invention, the fifth current I5 is determined by the capacitance of the third capacitor C3 to determine the charging time.

According to one embodiment of the present invention, when additional input current IA is supplied to second current source CS2, the magnitude of fourth current I4 is reduced, thereby reducing fifth current I5 charging third capacitor C3, thereby extending the duration that output signal OUT remains in the disabled state. In other words, by increasing the magnitude of input current IA, the duration of the negative pulse of output signal OUT can be adjusted. According to some embodiments of the present invention, input current IA in FIG. 7 corresponds to first adjusted current IX and second adjusted current IY in FIG. 5 .

FIG8 is a schematic diagram of a time-to-voltage conversion circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the automatic adjustment circuit 221 of FIG2 includes a time-to-voltage conversion circuit 800. As shown in FIG8 , the time-to-voltage conversion circuit 800 includes a fourth current source CS4, a third OR gate OR3, a first switch SW1, a first NAND gate NAND1, a second switch SW2, a fourth capacitor C4, a third switch SW3, a fifth capacitor C5, a fourth switch SW4, and a sixth capacitor C6.

The fourth current source CS4 generates a sixth current I6. The third OR gate OR3 performs a logical OR operation on the upper bridge drive signal HS and the lower bridge drive signal LS, turning on the first switch SW1. This allows the sixth current I6 to charge the fourth capacitor C4. The first NAND gate NAND1 performs a logical NAND operation on the upper bridge dead-band timing signal CK_H and the lower bridge dead-band timing signal CK_L, turning on the second switch SW2, causing the fourth capacitor C4 to discharge to ground.

The upper bridge drive signal HS controls the third switch SW3, allowing the sixth current I6 to charge the fifth capacitor C5 and generate the upper bridge enable cycle voltage VDH. The lower bridge drive signal LS controls the fourth switch SW4, allowing the sixth current I6 to charge the sixth capacitor C6 and generate the lower bridge enable cycle voltage VDL.

In other words, when the high-bridge drive signal HS is enabled, the sixth current I6 charges the fourth capacitor C4 and the fifth capacitor C5. When the low-bridge drive signal LS is enabled, the sixth current I6 charges the fourth capacitor C4 and the sixth capacitor C6. During the high-bridge dead time and the low-bridge dead time, the fourth capacitor C4 is discharged, clearing the charge stored in the fourth capacitor C4. Therefore, the high-bridge enable cycle voltage VDH represents the enable cycle of the high-bridge drive signal HS, and the low-bridge enable cycle voltage VDL represents the enable cycle of the low-bridge drive signal LS.

FIG9 is a schematic diagram of an automatic adjustment circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the automatic adjustment circuit 900 corresponds to the automatic adjustment circuit 221 of FIG2.

As shown in Figure 9, the automatic adjustment circuit 900 includes a comparison circuit 910, a signal generation circuit 920, a fourth flip-flop FF4, a fifth flip-flop FF5, a counter 930, and a digital-to-analog converter 940. The comparison circuit 910 is used to compare the upper bridge enable cycle voltage VDH with the lower bridge enable cycle voltage VDL to generate an up signal UP and a down signal DWN.

Signal generation circuit 920 generates a clock signal CLK and a latch signal LTH based on the upper dead-band timing signal CK_H and the lower dead-band timing signal CK_L. The fourth flip-flop FF4 generates a latched up count signal LUP based on the latch signal LTH and the latched up count signal UP. The fifth flip-flop FF5 generates a latched down count signal LDWN based on the latch signal LTH and the latched down count signal DWN. Counter 930 counts digital code B based on the clock signal CLK. When the latched up count signal LUP is enabled and the latched down count signal LDWN is disabled, counter 930 counts digital code B. When the latch up signal LUP is in the disabled state and the latch down signal LDWN is in the enabled state, the counter 930 counts down the digital code B.

As shown in FIG9 , comparator circuit 910 includes a fourth comparator CMP4, a fifth comparator CMP5, a fourth inverter INV4, a fifth inverter INV5, a seventh AND gate AND7, and an eighth AND gate AND8. When the upper bridge enable period voltage VDH exceeds the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is enabled and the output of the fifth comparator CMP5 is disabled. When the upper bridge enable period voltage VDH does not exceed the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is disabled and the output of the fifth comparator CMP5 is enabled. Next, the up signal UP and the down signal DWN are generated through the fourth inverter INV4, the fifth inverter INV5, the seventh AND gate AND7, and the eighth AND gate AND8.

In other words, when the upper bridge enable cycle voltage VDH exceeds the lower bridge enable cycle voltage VDL, the up-count signal UP is enabled and the down-count signal DWN is disabled. When the upper bridge enable cycle voltage VDH does not exceed the lower bridge enable cycle voltage VDL, the up-count signal UP is disabled and the down-count signal DWN is enabled. In other words, when the enable cycle of the upper bridge drive signal HS exceeds the enable cycle of the lower bridge drive signal LS, the counter 930 counts up the digital code B, causing the digital-to-analog converter 940 to increase the adjustment current ID. When the enable period of the upper bridge drive signal HS does not exceed the enable period of the lower bridge drive signal LS, the counter 930 counts down the digital code B, causing the digital-to-analog converter 940 to reduce the regulation current ID.

Signal generation circuit 920 includes a ninth AND gate AND9, a fifth current source CS5, a third N-type transistor MN3, a seventh capacitor C7, a sixth inverter INV6, and a tenth AND gate AND10. The ninth AND gate AND9 performs logic operations on the upper bridge dead-band timing signal CK_H and the lower bridge dead-band timing signal CK_L to generate a clock signal CLK. When either the upper-bridge dead-band timing signal CK_H or the lower-bridge dead-band timing signal CK_L is in a negative pulse, the clock signal CLK is disabled, and the seventh current I7 of the fifth current source CS5 charges the seventh capacitor C7 to generate the second capacitor voltage VCAP2. Furthermore, the sixth inverter INV6 inverts the clock signal CLK, causing the latch signal LTH output by the tenth AND gate AND10 to generate a positive edge, thereby triggering the fourth flip-flop FF4 and the fifth flip-flop FF5 to latch the up signal UP and the down signal DWN, respectively.

According to one embodiment of the present invention, when the enable period of the upper bridge drive signal HS exceeds the enable period of the lower bridge drive signal LS, the adjustment current ID is increased to increase the offset voltage VOS and the base voltage VBS, thereby shortening the enable period of the upper bridge drive signal HS and extending the enable period of the lower bridge drive signal LS. According to another embodiment of the present invention, when the enable period of the high-side drive signal HS does not exceed the enable period of the low-side drive signal LS, the adjustment current ID is reduced to lower the offset voltage VOS and the base voltage VBS, thereby extending the enable period of the high-side drive signal HS and shortening the enable period of the low-side drive signal LS. In other words, by adjusting the base voltage VBS, the enable period of the high-side drive signal HS is brought closer to the enable period of the low-side drive signal LS.

FIG10 is a block diagram of an output voltage detection circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the control circuit 150 of FIG1 further includes an output voltage detection circuit 1000. As shown in FIG10 , the output voltage detection circuit 1000 includes a sixth comparator CMP6, a second NAND gate NAND2, a sixth flip-flop FF6, a sixth inverter INV6, and a delay circuit 1010.

The sixth comparator CMP6 compares the feedback voltage FB with the low-power threshold voltage VTLP to generate a comparison signal CP. According to one embodiment of the present invention, when the output voltage VOUT in FIG1 increases, the feedback voltage FB decreases. The increase in output voltage VOUT indicates a decrease in output power. In other words, when the comparison signal CP in FIG10 is at a high logical level, it indicates that the output power is too low.

The second NAND gate NAND2 performs a logical NAND operation on the lower bridge dead-time signal CK_L and the supply voltage VCC, triggering the sixth flip-flop FF6 to output the comparison signal CP as an inverted burst signal SB, which then generates the burst signal BST via the sixth inverter INV6. According to one embodiment of the present invention, when the lower bridge dead-band timing signal CK_L changes from a disabled state to an enabled state to enable the upper bridge drive signal HS, the comparison signal CP is at a high logic level (indicating that the output voltage VOUT is too high). A low-logic-level burst signal BST is provided to the third AND gate AND3 and the sixth AND gate AND6 in FIG. 2 , thereby simultaneously disabling the upper bridge drive signal HS and the lower bridge drive signal LS. This embodiment of the present invention is described as triggering the burst mode when the burst signal BST is at a low logic level, indicating an enabled state, but the present invention is not limited to this embodiment.

Furthermore, after receiving the high-logic-level inverted burst signal SB, the delay circuit 1010 delays the signal by a delay time to generate the reset signal ST. The mapped current IB in Figure 4 is used to adjust the delay time of the delay circuit 1010. According to one embodiment of the present invention, the delay circuit 1010 can be implemented by the delay time generator 700 in Figure 7, where the inverted burst signal SB corresponds to the input signal IN in Figure 7, and the reset signal ST corresponds to the output signal OUT in Figure 7. The detailed operation is not repeated here. According to one embodiment of the present invention, the supply voltage VCC input to the second NAND gate NAND2 can be replaced by the upper bridge dead-time signal CK_H.

FIG11 is a flow chart illustrating a control method for controlling a resonant power conversion circuit according to one embodiment of the present invention. The following description of the control method 1100 in FIG11 will be used in conjunction with the resonant power conversion circuit 100 in FIG1 for detailed explanation.

First, the first voltage divider circuit 130 divides the voltage across the resonant capacitor CR to generate a divided signal SD (step S1110). Next, the full-wave rectifier 140 performs full-wave rectification on the divided signal SD to generate a rectified signal FW (step S1120). The rectified signal FW is compared with the feedback voltage FB to generate a high-side drive signal HS and a low-side drive signal LS, which drive the high-side transistor 110 and the low-side transistor 120, respectively (step S1130). According to one embodiment of the present invention, the compensation circuit 400 of FIG. 4 is used to limit the lower limit of the feedback voltage FB to generate the compensation voltage COMP. In step S1130, the rectified signal FW and the compensation voltage COMP are compared to generate the upper bridge drive signal HS and the lower bridge drive signal LS.

This invention proposes a resonant power conversion circuit and control method. By using full-wave rectification and a divided voltage signal related to the voltage across a resonant capacitor and comparing the divided voltage signal with the feedback voltage, the enable cycle of the upper-side transistor is brought close to that of the lower-side transistor, thereby improving the conversion efficiency of the resonant power conversion circuit.

While the embodiments and advantages of this disclosure have been described above, it should be understood that changes, substitutions, and modifications may be made by anyone skilled in the art without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection provided by this disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps described in the specific embodiments herein. Anyone skilled in the art will understand from the disclosure of certain embodiments of this disclosure that any currently or future developed processes, machines, manufactures, compositions of matter, devices, methods, and steps that can achieve substantially the same functions or results as those described herein may be used in accordance with certain embodiments of this disclosure. Therefore, the scope of protection of the present disclosure includes the aforementioned processes, machines, manufacture, compositions of matter, devices, methods, and steps. In addition, each patent claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of individual patent claims and embodiments.

100: Resonant power conversion circuit 110: Upper-side transistor 120: Lower-side transistor 130: First voltage divider circuit 140: Full-wave rectifier 150: Control circuit 160: Level shift circuit 170: Rectifier circuit 180: Feedback circuit 190: Second voltage divider circuit TM: Transformer LR: Resonant inductor CR: Resonant capacitor HSD: Upper-side driver circuit LSD: Lower-side driver circuit PS: Primary winding SS: Secondary winding NR: Resonance node SW: Switching node HSG: Upper-side gate drive signal LSG: Low-side gate drive signal VIN: Input voltage SD: Divider signal C1: First capacitor C2: Second capacitor R1: First resistor R2: Second resistor FW: Rectified signal SZ: Crossover signal COUT: Output capacitor FB: Feedback voltage HS: High-side drive signal LS: Low-side drive signal D1: First rectifier element D2: Second rectifier element VOUT: Output voltage R3: Third resistor R4: Fourth resistor DR: Voltage regulator PD: Optocoupler R5: Fifth resistor R6: Sixth resistor LED: Diode Q: Transistor VCC: Supply voltage R7: Seventh resistor R8: Eighth resistor VD1: First divided voltage VD2: Second divided voltage

Claims (22)

A resonant power conversion circuit includes: a resonant capacitor coupled between a resonant node and a ground terminal; a transformer including a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and the resonant node; a high-side transistor providing an input voltage to the switching node based on a high-side drive signal; a low-side transistor coupling the switching node to the ground terminal based on a low-side drive signal; a first voltage divider circuit dividing the voltage at the resonant node to generate a divided voltage signal; A full-wave rectifier device that full-wave rectifies the divided signal generated by the first voltage divider circuit to generate a rectified signal; A control circuit that compares the rectified signal with a feedback voltage to generate the upper bridge drive signal and the lower bridge drive signal; A rectifier circuit coupled to the secondary coil and converting the current flowing through the secondary coil into an output voltage; and A feedback circuit that generates the feedback voltage based on the output voltage. The resonant power conversion circuit of claim 1, wherein the full-wave rectifier performs full-wave rectification on the divided signal using a base voltage as a DC level to generate the rectified signal; wherein the base voltage is equal to the sum of a divided voltage and an offset voltage; wherein the divided voltage is equal to the input voltage divided and multiplied by a first ratio; wherein the full-wave rectifier further compares the rectified signal with a first threshold voltage to generate a crossover signal; wherein the first threshold voltage is slightly greater than the base voltage. The resonant power conversion circuit of claim 2, wherein when the rectified signal is less than the first threshold voltage, the full-wave rectifier sets the cross signal to a disabled state; When the rectified signal exceeds the first threshold voltage, the full-wave rectifier sets the cross signal to an enabled state; In response to the cross signal changing from the disabled state to the enabled state, the control circuit sets a phase signal to the enabled state; In response to the full-wave rectified signal exceeding the feedback voltage, the control circuit sets the phase signal to the disabled state based on an upper bridge dead band time signal or a lower bridge dead band time signal; In response to the full-wave rectified signal exceeding the feedback voltage, the control circuit sets the phase signal to the disabled state based on an upper bridge dead band time signal or a lower bridge dead band time signal; In response to the upper bridge dead band time signal controlling an upper bridge dead band time of the upper bridge drive signal; The above-mentioned lower bridge dead zone time signal controls the lower bridge dead zone time of one of the above-mentioned lower bridge drive signals. The resonant power conversion circuit of claim 3, wherein when the upper bridge drive signal turns on the upper bridge transistor and the phase signal is in the enabled state, the control circuit disables the upper bridge drive signal in response to the rectified signal exceeding the feedback voltage; When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge drive signal after the lower bridge dead band time to turn on the lower bridge transistor; When the lower bridge drive signal turns on the lower bridge transistor and the phase signal is in the enabled state, the control circuit disables the lower bridge drive signal in response to the rectified signal exceeding the feedback voltage; When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal after the upper bridge dead time to turn on the upper bridge transistor. The resonant power conversion circuit of claim 3, wherein the control circuit further limits the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal to no more than a maximum enable cycle. The resonant power conversion circuit of claim 3, wherein the offset voltage is determined based on a difference between an enable period of the upper bridge drive signal and an enable period of the lower bridge drive signal; The offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal approaches the enable period of the lower bridge drive signal. The resonant power conversion circuit of claim 3 further includes: a second voltage divider circuit for dividing the input voltage to generate the divided voltage; the full-wave rectifier device includes: a first resistor coupled between the divided voltage and the base voltage, wherein the voltage across the first resistor generates the offset voltage; a first current source for providing a first current to the base voltage; and an automatic adjustment circuit for extracting a regulated current from the base voltage based on the upper bridge drive signal, the lower bridge drive signal, the upper bridge dead-band time signal, and the lower bridge dead-band time signal. The resonant power conversion circuit of claim 7, wherein, in response to the first current being greater than the adjusted current, the offset voltage is positive and the base voltage is greater than the divided voltage; in response to the first current being less than the adjusted current, the offset voltage is negative and the base voltage is less than the divided voltage; in response to the first current being equal to the adjusted current, the base voltage is equal to the divided voltage. The resonant power conversion circuit of claim 7, wherein the automatic adjustment circuit comprises: A time-to-voltage conversion circuit for converting the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal into an upper bridge enable cycle voltage and a lower bridge enable cycle voltage, respectively; The time-to-voltage conversion circuit comprises: A second current source for providing a second current; A first switch for providing the second current to a charging node based on the enabled upper bridge drive signal or the enabled lower bridge drive signal; A second switch for coupling the charging node to the ground during the upper bridge dead time and the lower bridge dead time; A first capacitor coupled between the charging node and the ground terminal; A second capacitor coupled between an upper bridge enable cycle voltage and the ground terminal; A third capacitor coupled between a lower bridge enable cycle voltage and the ground terminal; A third switch coupled to the charging node to the upper bridge enable cycle voltage in response to the upper bridge drive signal being enabled; and A fourth switch coupled to the charging node to the lower bridge enable cycle voltage in response to the lower bridge drive signal being enabled. The upper bridge enable cycle voltage represents the enable cycle of the upper bridge drive signal, and the lower bridge enable cycle voltage represents the enable cycle of the lower bridge drive signal. The resonant power conversion circuit of claim 9, wherein the automatic adjustment circuit further comprises: a comparison circuit for comparing the upper bridge enable cycle voltage and the lower bridge enable cycle voltage to generate an up-count signal and a down-count signal; a plurality of registers for latching the up-count signal and the down-count signal during the upper bridge dead time and the lower bridge dead time; a counter for counting up a digital code based on the enabled up-count signal and counting down the digital code based on the enabled down-count signal; and a digital-to-analog converter for generating the adjustment current based on the digital code; When the upper bridge enable cycle voltage is greater than the lower bridge enable cycle voltage, the comparison circuit enables the up-count signal and disables the down-count signal. When the upper bridge enable cycle voltage is not greater than the lower bridge enable cycle voltage, the comparison circuit disables the up-count signal and enables the down-count signal. The resonant power conversion circuit of claim 7, wherein the feedback voltage decreases in response to an increase in the output voltage; in response to the feedback voltage being lower than a low-power threshold voltage, a lower-side dead-band timing signal enables a burst signal, causing the control circuit to operate in a burst mode based on the enabled burst signal; when the control circuit operates in the burst mode, both the upper-side transistor and the lower-side transistor are non-conductive; in which a duration of the burst mode increases as the output power of the output voltage decreases. The resonant power conversion circuit of claim 11, wherein the control circuit comprises: a first amplifier comprising a first positive input terminal, a first negative input terminal, and a first output terminal, wherein the first positive input terminal receives the feedback voltage and the first negative input terminal is coupled to the first output terminal; a second amplifier comprising a second positive input terminal, a second negative input terminal, and a second output terminal, wherein the second positive input terminal receives a feedback threshold voltage; a second resistor coupled between the second negative input terminal and the first output terminal and generating a differential current; an N-type transistor comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to the second output terminal and the source terminal is coupled to the second negative input terminal; and A current mirror maps the differential current into a mapped current; wherein the feedback threshold voltage is a lower limit of the feedback voltage; wherein the mapped current is used to adjust the duration. A control method for controlling a resonant power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, a high-bridge transistor that provides an input voltage to a switching node, a low-bridge transistor that couples the switching node to the ground terminal, a rectifier circuit that converts current flowing through the secondary coil into an output voltage, and a feedback circuit that generates a feedback voltage based on the output voltage. The primary coil is coupled between the switching node and the resonant node. The control method includes: Using a first voltage divider circuit to divide the voltage across the resonant capacitor to generate a voltage-dividing signal; Full-wave rectifying the divided signal to generate a rectified signal; and Comparing the rectified signal with the feedback voltage to drive the upper bridge transistor and the lower bridge transistor. The control method of claim 13 further comprises: Full-wave rectifying the divided signal using a base voltage as a DC level to generate the rectified signal; Comparing the rectified signal with a first threshold voltage to generate a crossover signal; Wherein, the base voltage is equal to the sum of a divided voltage and an offset voltage; Wherein, the divided voltage is equal to the input voltage multiplied by a first ratio; Wherein, the first threshold voltage is slightly greater than the base voltage. The control method of claim 14 further includes: When the rectified signal is less than the first threshold voltage, setting the cross signal to a disabled state; When the rectified signal exceeds the first threshold voltage, setting the cross signal to an enabled state; In response to the cross signal changing from the disabled state to the enabled state, setting a phase signal to the enabled state; and In response to the full-wave rectified signal exceeding the feedback voltage, setting the phase signal to the disabled state during an upper bridge dead band time or a lower bridge dead band time; The lower bridge dead band time is the time between the time when the upper bridge transistor becomes non-conductive and the time when the lower bridge transistor becomes conductive; The upper bridge dead time is the time from when the lower bridge transistor turns off to when the upper bridge transistor turns on. The control method of claim 15 further comprises: When the upper bridge transistor is conductive and the phase signal is in the enabled state, in response to the rectified signal exceeding the feedback voltage, turning off the upper bridge transistor; When the upper bridge transistor is not conductive, turning on the lower bridge transistor after the lower bridge dead time; When the lower bridge transistor is conductive and the phase signal is in the enabled state, in response to the rectified signal exceeding the feedback voltage, turning off the lower bridge transistor; and When the lower bridge transistor is not conductive, turning on the upper bridge transistor after the upper bridge dead time. The control method of claim 15 further includes: Limiting the enable cycle of the upper bridge transistor and the enable cycle of the lower bridge transistor to no greater than a maximum enable cycle. The control method of claim 15 further includes: Determining the offset voltage based on a difference between an enable period of the upper bridge transistor and an enable period of the lower bridge transistor; Wherein, the offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal approaches the enable period of the lower bridge drive signal. The control method of claim 15 further includes: generating the offset voltage using a voltage across a first resistor, wherein the first resistor is coupled between the divided voltage and the base voltage; providing a first current to flow to the base voltage; using an automatic adjustment circuit to extract an adjustment current from the base voltage based on the conduction and non-conduction states of the upper and lower bridge transistors, the upper bridge dead time, and the lower bridge dead time; in response to the first current being greater than the adjustment current, the offset voltage is positive, and the base voltage is greater than the divided voltage; In response to the first current being less than the adjusted current, the offset voltage is negative, and the base voltage is less than the divided voltage; and In response to the first current being equal to the adjusted current, the base voltage is equal to the divided voltage. The control method of claim 19, wherein the step of extracting the regulated current from the base voltage using the automatic adjustment circuit based on the conduction and non-conduction states of the upper and lower bridge transistors, the upper bridge dead time, and the lower bridge dead time further includes: Using a time-to-voltage conversion circuit to convert the conduction time of the upper bridge transistor into an upper bridge enable cycle voltage; Using the time-to-voltage conversion circuit to convert the conduction time of the lower bridge transistor into a lower bridge enable cycle voltage; Comparing the upper bridge enable cycle voltage and the lower bridge enable cycle voltage to generate an up signal and a down signal; When the upper bridge enable cycle voltage is greater than the lower bridge enable cycle voltage, the regulated current is increased; and when the upper bridge enable cycle voltage is not greater than the lower bridge enable cycle voltage, the regulated current is decreased. The control method of claim 19 further comprises: In response to the feedback voltage being lower than a low-power threshold voltage, operating in a burst mode, wherein the feedback voltage decreases in response to an increase in the output voltage; In the burst mode, the high-side transistor and the low-side transistor are simultaneously non-conductive; and In response to a decrease in output power of the output voltage, increasing a duration of the burst mode. The control method of claim 21 further includes: limiting the feedback voltage to no greater than a feedback threshold voltage; generating a differential current using a second resistor, the feedback voltage, and the feedback threshold voltage; mapping the differential current into a mapped current; and adjusting the duration using the mapped current.