[go: up one dir, main page]

TWI869004B - Improved Field Plate Structure of GaN High Electron Mobility Transistor - Google Patents

Improved Field Plate Structure of GaN High Electron Mobility Transistor Download PDF

Info

Publication number
TWI869004B
TWI869004B TW112140958A TW112140958A TWI869004B TW I869004 B TWI869004 B TW I869004B TW 112140958 A TW112140958 A TW 112140958A TW 112140958 A TW112140958 A TW 112140958A TW I869004 B TWI869004 B TW I869004B
Authority
TW
Taiwan
Prior art keywords
gallium nitride
field plate
passivation layer
layer
electron mobility
Prior art date
Application number
TW112140958A
Other languages
Chinese (zh)
Other versions
TW202519027A (en
Inventor
陳志典
呂威儒
劉冠顯
張國仁
吳肇欣
林峯霆
Original Assignee
國家中山科學研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 國家中山科學研究院 filed Critical 國家中山科學研究院
Priority to TW112140958A priority Critical patent/TWI869004B/en
Application granted granted Critical
Publication of TWI869004B publication Critical patent/TWI869004B/en
Publication of TW202519027A publication Critical patent/TW202519027A/en

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明係提供一種氮化鎵高電子遷移率電晶體之場板改良結構,其包括:磊晶結構、源極、閘極、汲極、雙層鈍化層以及垂直場板;垂直場板之結構,可以使閘極與汲極間電場重新分布,能有效提高元件之崩潰電壓,並且也能改善電流崩塌效應之功效。 The present invention provides a field plate improvement structure for a gallium nitride high electron mobility transistor, which includes: an epitaxial structure, a source, a gate, a drain, a double passivation layer, and a vertical field plate; the vertical field plate structure can redistribute the electric field between the gate and the drain, which can effectively increase the breakdown voltage of the device and improve the current collapse effect.

Description

氮化鎵高電子遷移率電晶體之場板改良結構 Improved field plate structure of gallium nitride high electron mobility transistor

本發明係關於一種半導體元件結構,特別是關於一種氮化鎵高電子遷移率電晶體之場板改良結構。 The present invention relates to a semiconductor device structure, in particular to an improved field plate structure of a gallium nitride high electron mobility transistor.

為了滿足近年來市場上高功率與高頻元件的需求,氮化鋁鎵/氮化鎵高電子遷移率電晶體因為其能帶寬與高電子飽和速率等特點而受到極大的關注。另外,為了改善元件的崩潰電壓,場板技術被大量應用在元件上。場板技術能使元件橫向空間電荷分布較均勻,從而提高元件的崩潰電壓,也能改善電流崩塌的效應。在習知技術中有提出了幾種不同的場板結構,例如閘極場板、源極連接場板等。 In order to meet the market demand for high-power and high-frequency components in recent years, AlGaN/GaN high electron mobility transistors have received great attention due to their characteristics such as wide energy band and high electron saturation rate. In addition, in order to improve the breakdown voltage of components, field plate technology is widely used in components. Field plate technology can make the lateral spatial charge distribution of components more uniform, thereby increasing the breakdown voltage of components and improving the effect of current collapse. Several different field plate structures have been proposed in the prior art, such as gate field plates, source connection field plates, etc.

習知技術所提出之場板結構雖然可以增加元件之崩潰電壓與改善電流崩塌效應,然而,這些橫向或閘極連接的場板配置,會導致米勒電容的增加,而使得元件之高頻特性下降。另外,閘極橫向場板會導致閘極與汲極間距縮短,也就是電子漂移區縮短,這將使得電場集中於閘極或汲極邊緣,造成元件崩潰電壓下降,所以橫向場板結構也會限制元件微縮的發展。最後,場板的製作大多會選用氮化矽當作介電層材料,但其介電常數相比於其他高介電常數(high-k)材料 較低,這可能使得場板對元件崩潰電壓的改善效果下降。 Although the field plate structure proposed by the prior art can increase the breakdown voltage of the device and improve the current collapse effect, these lateral or gate-connected field plate configurations will lead to an increase in Miller capacitance, which will reduce the high-frequency characteristics of the device. In addition, the gate lateral field plate will cause the distance between the gate and the drain to shorten, that is, the electron drift region to shorten, which will cause the electric field to concentrate on the gate or drain edge, causing the device breakdown voltage to decrease, so the lateral field plate structure will also limit the development of device miniaturization. Finally, field plates are mostly made of silicon nitride as the dielectric material, but its dielectric constant is lower than other high-k materials, which may reduce the effect of field plates on improving device breakdown voltage.

綜觀上述,對於高功率氮化鎵元件而言,可靠度與崩潰電壓是一個重要的指標。為了提高元件的穩定性,我們必須提高元件的崩潰電壓,最常使用的方法為使用場板(field plate)結構,此結構能使閘極與汲極間電場重新分布,造成閘極附近峰值電場下降,進而減少熱電子被介電層所捕獲的機率,能有效改善電流崩塌效應(current collapse)並提升元件之崩潰電壓。但由於傳統橫向結構對於元件微縮的限制,所以本發明將製做垂直式場板結構以利在元件微縮的同時增加崩潰電壓並改善電流崩塌效應。 In summary, for high-power gallium nitride components, reliability and breakdown voltage are important indicators. In order to improve the stability of the component, we must increase the breakdown voltage of the component. The most commonly used method is to use a field plate structure. This structure can redistribute the electric field between the gate and the drain, causing the peak electric field near the gate to drop, thereby reducing the probability of hot electrons being captured by the dielectric layer, which can effectively improve the current collapse effect and increase the breakdown voltage of the component. However, due to the limitations of the traditional lateral structure on component miniaturization, the present invention will manufacture a vertical field plate structure to increase the breakdown voltage and improve the current collapse effect while miniaturizing the component.

鑒於上述悉知技術之缺點,本發明之主要目的在於提出一種氮化鎵高電子遷移率電晶體之場板改良結構,以利在元件微縮的同時增加崩潰電壓並改善電流崩塌效應。 In view of the above shortcomings of the known technology, the main purpose of the present invention is to propose an improved field plate structure of a gallium nitride high electron mobility transistor, so as to increase the breakdown voltage and improve the current collapse effect while miniaturizing the device.

為達到上述目的,根據本發明提出之一種氮化鎵高電子遷移率電晶體之場板改良結構,其包括:磊晶結構;三電極,其包括源極、閘極及汲極係設置於磊晶結構上,其中磊晶結構於對應汲極處形成垂直方向之缺口;雙層鈍化層,其包括L形之低介電常數之鈍化層及L形之高介電常數之鈍化層,並設置於垂直方向之缺口,以及垂直場板,其以垂直方向設置於雙層鈍化層上。 To achieve the above-mentioned purpose, the present invention proposes an improved field plate structure for a gallium nitride high electron mobility transistor, which includes: an epitaxial structure; a three-electrode structure including a source, a gate and a drain disposed on the epitaxial structure, wherein the epitaxial structure forms a vertical notch at the corresponding drain; a double-layer passivation layer including an L-shaped low-k passivation layer and an L-shaped high-k passivation layer disposed in the vertical notch, and a vertical field plate disposed in the vertical direction on the double-layer passivation layer.

較佳地,磊晶結構由下而上可為:碳化矽或矽基板、氮化鎵緩衝層、氮化鎵通道層及氮化鋁鎵障蔽層。 Preferably, the epitaxial structure from bottom to top can be: silicon carbide or silicon substrate, gallium nitride buffer layer, gallium nitride channel layer and aluminum gallium nitride barrier layer.

較佳地,三電極係可設置於氮化鋁鎵障蔽層上,源極之材料為鈦及金,閘極之材料為鎳及金,汲極之材料為鈦及金。 Preferably, the three electrodes can be set on the aluminum gallium nitride barrier layer, the source material is titanium and gold, the gate material is nickel and gold, and the drain material is titanium and gold.

較佳地,低介電常數之鈍化層材料可為氮化矽、氧化矽或氧化鋁材料。 Preferably, the low dielectric constant passivation layer material can be silicon nitride, silicon oxide or aluminum oxide material.

較佳地,高介電常數之鈍化層材料可為二氧化鉿、氧化釔、氧化鑭、氧化鈦或氧化鋯材料。 Preferably, the high dielectric constant passivation layer material can be einsteinium dioxide, yttrium oxide, titanium oxide, titanium oxide or zirconium oxide material.

較佳地,高介電常數之鈍化層係可設置於低介電常數之鈍化層上,而垂直場板係可設置於高介電常數之鈍化層上。 Preferably, the high dielectric constant passivation layer can be disposed on the low dielectric constant passivation layer, and the vertical field plate can be disposed on the high dielectric constant passivation layer.

較佳地,垂直方向之缺口延伸至氮化鎵緩衝層中的深度可大於該氮化鎵緩衝層厚度的1/2。 Preferably, the depth of the vertical notch extending into the GaN buffer layer can be greater than 1/2 of the thickness of the GaN buffer layer.

較佳地,垂直場板延伸至氮化鎵緩衝層中的深度可小於該氮化鎵緩衝層厚度的1/2。 Preferably, the depth of the vertical field plate extending into the GaN buffer layer can be less than 1/2 of the thickness of the GaN buffer layer.

較佳地,可進一步包含一平行場板係設置於汲極延向閘極之雙層鈍化層上方。 Preferably, it may further include a parallel field plate disposed above the double passivation layer extending from the drain to the gate.

以上之概述與接下來的詳細說明及附圖,皆是為了能進一步說明本發明達到預定目的所採取的方式、手段及功效。而有關本發明的其他目的及優點,將在後續的說明及圖式中加以闡述。 The above overview and the following detailed description and attached figures are all for the purpose of further explaining the methods, means and effects adopted by the present invention to achieve the intended purpose. Other purposes and advantages of the present invention will be elaborated in the subsequent description and drawings.

1:磊晶結構 1: Epitaxial structure

11:氮化鎵緩衝層 11: Gallium nitride buffer layer

12:氮化鎵通道層 12: Gallium nitride channel layer

13:氮化鋁鎵障蔽層 13: Aluminum-gallium nitride barrier layer

2:雙層鈍化層 2: Double passivation layer

21:低介電常數之鈍化層 21: Low dielectric constant passivation layer

22:高介電常數之鈍化層 22: High dielectric constant passivation layer

3:垂直場板 3: Vertical field plate

S:源極 S: Source

G:閘極 G: Gate

D:汲極 D: Drain

第1圖係為本發明提出之氮化鎵高電子遷移率電晶體之場板改良結構示意圖。 Figure 1 is a schematic diagram of the improved field plate structure of the gallium nitride high electron mobility transistor proposed in the present invention.

第2圖係為各種場板結構數據比較圖。 Figure 2 is a data comparison of various field plate structures.

第3圖係為平行場板及垂直場板之元件電場分布圖。 Figure 3 shows the electric field distribution of the device with parallel field plates and perpendicular field plates.

雖然本發明可表現為不同形式之實施例,但附圖所示者及於下文中說明者係為本發明之較佳實施例,並請瞭解本文所揭示者係考量為本發明之一範例,且並非意圖用以將本發明限制於圖示及或所描述之特定實施例中。 Although the present invention can be embodied in different forms, the embodiments shown in the attached drawings and described below are preferred embodiments of the present invention. Please understand that what is disclosed herein is considered as an example of the present invention and is not intended to limit the present invention to the specific embodiments shown and/or described.

現請參考第1圖,第1圖係為本發明提出之氮化鎵高電子遷移率電晶體之場板改良結構示意圖,其顯示為本發明之一種氮化鎵高電子遷移率電晶體之場板改良結構,其包括:磊晶結構1、三電極、雙層鈍化層2及垂直場板3。磊晶結構1由下而上可為:碳化矽或矽基板、氮化鎵緩衝層11、氮化鎵通道層12及氮化鋁鎵障蔽層13,亦可以進一步在氮化鋁鎵障蔽層13上設置氮化鎵覆蓋層。三電極其包括源極S、閘極G及汲極D係設置於磊晶結構1上,其中磊晶結構1於對應汲極D處形成垂直方向之缺口,此垂直方向之缺口從汲極 D延伸至氮化鎵緩衝層11中的深度可大於該氮化鎵緩衝層11厚度的1/2,在本實施方式中,氮化鎵緩衝層11的厚度介於1μm-3μm之間,而氮化鎵緩衝層11在缺口對應處的厚度介於0.3μm-1.4μm之間。 Please refer to FIG. 1, which is a schematic diagram of the field plate improvement structure of the gallium nitride high electron mobility transistor proposed in the present invention, which shows a field plate improvement structure of the gallium nitride high electron mobility transistor of the present invention, which includes: an epitaxial structure 1, a three-electrode, a double-layer passivation layer 2 and a vertical field plate 3. The epitaxial structure 1 can be from bottom to top: a silicon carbide or silicon substrate, a gallium nitride buffer layer 11, a gallium nitride channel layer 12 and an aluminum gallium nitride barrier layer 13, and a gallium nitride cap layer can be further provided on the aluminum gallium nitride barrier layer 13. The three electrodes including the source S, the gate G and the drain D are arranged on the epitaxial structure 1, wherein the epitaxial structure 1 forms a vertical notch at the position corresponding to the drain D. The depth of the vertical notch extending from the drain D to the gallium nitride buffer layer 11 may be greater than 1/2 of the thickness of the gallium nitride buffer layer 11. In the present embodiment, the thickness of the gallium nitride buffer layer 11 is between 1μm-3μm, and the thickness of the gallium nitride buffer layer 11 at the position corresponding to the notch is between 0.3μm-1.4μm.

雙層鈍化層2包括L形之低介電常數之鈍化層21及L形之高介電常數之鈍化層22,並設置於垂直方向之缺口,以及垂直場板3,其以垂直方向設置於雙層鈍化層2上。在本實施方式中,低介電常數之鈍化層21材料可為氮化矽、氧化矽或氧化鋁材料,而高介電常數之鈍化層22材料可為二氧化鉿、氧化釔、氧化鑭、氧化鈦或氧化鋯材料。高介電常數之鈍化層22係設置於低介電常數之鈍化層21上,而垂直場板3係設置於高介電常數之鈍化層22上。 The double-layer passivation layer 2 includes an L-shaped low-k passivation layer 21 and an L-shaped high-k passivation layer 22, which are arranged in a vertical notch, and a vertical field plate 3, which is arranged on the double-layer passivation layer 2 in a vertical direction. In this embodiment, the low-k passivation layer 21 material can be silicon nitride, silicon oxide or aluminum oxide material, and the high-k passivation layer 22 material can be einsteinium dioxide, yttrium oxide, titanium oxide, titanium oxide or zirconium oxide material. The high-k passivation layer 22 is arranged on the low-k passivation layer 21, and the vertical field plate 3 is arranged on the high-k passivation layer 22.

以上,將場板結構垂直延伸至磊晶結構1之氮化鎵緩衝層11,當在汲極D施加正偏壓時,它能將電場分散至氮化鎵緩衝層11,而不是集中於閘極G與汲極D之間,有利於在元件微縮的同時提高其崩潰電壓。另外,在此也將傳統單層鈍化層之氮化矽(SiN)結構再加上一層高介電常數材料(HfO2)以增加其崩潰電壓與改善電流崩塌效應。 As described above, the field plate structure is vertically extended to the gallium nitride buffer layer 11 of the epitaxial structure 1. When a positive bias is applied to the drain D, it can disperse the electric field to the gallium nitride buffer layer 11 instead of concentrating it between the gate G and the drain D, which is beneficial to improve the breakdown voltage while miniaturizing the device. In addition, a layer of high dielectric constant material (HfO 2 ) is added to the traditional single-layer passivation layer of silicon nitride (SiN) structure to increase its breakdown voltage and improve the current collapse effect.

另外,本實施方式中,三電極係設置於氮化鋁鎵障蔽層13上,源極S之材料為鈦及金,閘極G之材料為鎳及金,汲極D之材料為鈦及金。 In addition, in this embodiment, the three electrodes are arranged on the aluminum-gallium nitride barrier layer 13, the source S is made of titanium and gold, the gate G is made of nickel and gold, and the drain D is made of titanium and gold.

本實施方式中,垂直場板3延伸至氮化鎵緩衝層 11中的深度小於氮化鎵緩衝層11厚度的1/2,舉例來說,氮化鎵緩衝層11的厚度介於1μm-3μm之間,而垂直場板3延伸至氮化鎵緩衝層11中的深度介於0.2μm-1.4μm之間,以使閘極G與汲極D間電場重新分布,能有效提高元件之崩潰電壓,並且也能改善電流崩塌效應。 In this embodiment, the depth of the vertical field plate 3 extending into the gallium nitride buffer layer 11 is less than 1/2 of the thickness of the gallium nitride buffer layer 11. For example, the thickness of the gallium nitride buffer layer 11 is between 1μm-3μm, and the depth of the vertical field plate 3 extending into the gallium nitride buffer layer 11 is between 0.2μm-1.4μm, so that the electric field between the gate G and the drain D is redistributed, which can effectively increase the breakdown voltage of the device and improve the current collapse effect.

再者,本發明可進一步於汲極D處設置平行場板於雙層鈍化層2上方,此平行場板由汲極D延向閘極G,形成雙場板及雙層鈍化層2之結構。 Furthermore, the present invention can further set a parallel field plate at the drain D above the double-layer passivation layer 2. The parallel field plate extends from the drain D to the gate G to form a double field plate and double-layer passivation layer 2 structure.

現請參考第2圖及第3圖,第2圖係為各種場板結構數據比較圖。第3圖係為平行場板及垂直場板3之元件電場分布圖。由文獻數據第2圖可以看出當元件汲極D與閘極G距離微縮時,垂直式場板結構能夠幫助元件更好地提升崩潰電壓。其原因可以從第3圖元件電場分布圖看出,當間距微縮時,橫向場板結構會使電場集中於閘極G汲極D之間,這電場將造成熱電子產生,使得元件崩潰;反觀垂直場板3結構能將電場同時分散至閘極G汲極D之間與磊晶緩衝層,想較之下更能防止元件崩潰。 Please refer to Figure 2 and Figure 3. Figure 2 is a comparison of various field plate structure data. Figure 3 is a device electric field distribution diagram of parallel field plate and vertical field plate 3. From the literature data Figure 2, it can be seen that when the distance between the device drain D and the gate G is reduced, the vertical field plate structure can help the device to better increase the breakdown voltage. The reason can be seen from the device electric field distribution diagram in Figure 3. When the spacing is reduced, the lateral field plate structure will concentrate the electric field between the gate G and the drain D. This electric field will cause hot electrons to be generated, causing the device to collapse; on the other hand, the vertical field plate 3 structure can disperse the electric field between the gate G and the drain D and the epitaxial buffer layer at the same time, which can better prevent device collapse.

綜上所述,近年來由於高科技快速發展,在高頻通訊、高功率元件等領域的規格與需求皆大幅地提升。相較於其他半導體材料,氮化鎵因為能帶寬與高電子飽和速率等材料特性,被視為下一代取代砷化鎵(GaAs)的角色。但應用在高功率元件的氮化鎵電晶體,崩潰電壓勢必是一個重要的 指標,同時,電流崩塌也是一個必須克服的問題,電流崩塌會影響元件的表現及可靠度。本發明利用雙層鈍化層2(介電層)(SiN/HfO2)之垂直場板3結構,對於高功率元件的應用,除了可以減少閘極G附近峰值電場,同時也可以減少熱電子被介電層所捕獲的機率,進而增加元件的可靠度。 In summary, due to the rapid development of high technology in recent years, the specifications and demands in the fields of high-frequency communications and high-power components have been greatly improved. Compared with other semiconductor materials, gallium nitride is regarded as the next generation to replace gallium arsenide (GaAs) because of its material properties such as bandwidth and high electron saturation rate. However, for gallium nitride transistors used in high-power components, the breakdown voltage must be an important indicator. At the same time, current collapse is also a problem that must be overcome. Current collapse will affect the performance and reliability of the component. The present invention utilizes a vertical field plate 3 structure of a double passivation layer 2 (dielectric layer) (SiN/HfO 2 ). For high power device applications, it can not only reduce the peak electric field near the gate G, but also reduce the probability of hot electrons being captured by the dielectric layer, thereby increasing device reliability.

上述之實施例僅為例示性說明本發明之特點及其功效,而非用於限制本發明之實質技術內容的範圍。任何熟習此技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與變化。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are only for illustrative purposes to illustrate the features and effects of the present invention, and are not intended to limit the scope of the substantial technical content of the present invention. Anyone familiar with this art may modify and change the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

1:磊晶結構 1: Epitaxial structure

11:氮化鎵緩衝層 11: Gallium nitride buffer layer

12:氮化鎵通道層 12: Gallium nitride channel layer

13:氮化鋁鎵障蔽層 13: Aluminum-gallium nitride barrier layer

2:雙層鈍化層 2: Double passivation layer

21:低介電常數之鈍化層 21: Low dielectric constant passivation layer

22:高介電常數之鈍化層 22: High dielectric constant passivation layer

3:垂直場板 3: Vertical field plate

S:源極 S: Source

G:閘極 G: Gate

D:汲極 D: Drain

Claims (9)

一種氮化鎵高電子遷移率電晶體之場板改良結構,其包括:一磊晶結構;三電極,其包括一源極、一閘極及一汲極係設置於該磊晶結構上,其中該磊晶結構於對應該汲極處形成一垂直方向之缺口;一雙層鈍化層,其包括L形之一低介電常數之鈍化層及L形之一高介電常數之鈍化層,並設置於該垂直方向之缺口,以及一垂直場板,其以垂直方向設置於該雙層鈍化層上。 An improved field plate structure of a gallium nitride high electron mobility transistor includes: an epitaxial structure; three electrodes, including a source, a gate and a drain, disposed on the epitaxial structure, wherein the epitaxial structure forms a vertical notch corresponding to the drain; a double-layer passivation layer, including an L-shaped low-k passivation layer and an L-shaped high-k passivation layer, disposed in the vertical notch, and a vertical field plate, disposed in a vertical direction on the double-layer passivation layer. 如申請專利範圍第1項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該磊晶結構由下而上為:一碳化矽或矽基板、一氮化鎵緩衝層、一氮化鎵通道層及一氮化鋁鎵障蔽層。 As described in Item 1 of the patent application, the field plate improvement structure of the gallium nitride high electron mobility transistor, wherein the epitaxial structure from bottom to top is: a silicon carbide or silicon substrate, a gallium nitride buffer layer, a gallium nitride channel layer and an aluminum gallium nitride barrier layer. 如申請專利範圍第2項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該三電極係設置於該氮化鋁鎵障蔽層上,該源極之材料為鈦及金,該閘極之材料為鎳及金,該汲極之材料為鈦及金。 As described in Item 2 of the patent application, the field plate improvement structure of the gallium nitride high electron mobility transistor, wherein the three electrodes are arranged on the aluminum gallium nitride barrier layer, the source electrode is made of titanium and gold, the gate electrode is made of nickel and gold, and the drain electrode is made of titanium and gold. 如申請專利範圍第1項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該低介電常數之鈍化層材料為氮化矽、氧化矽或氧化鋁材料。 As described in Item 1 of the patent application scope, the field plate improvement structure of the gallium nitride high electron mobility transistor, wherein the low dielectric constant passivation layer material is silicon nitride, silicon oxide or aluminum oxide material. 如申請專利範圍第1項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該高介電常數之鈍化層材料為二氧化鉿、氧化釔、氧化鑭、氧化鈦或氧化鋯材料。 The field plate improvement structure of the gallium nitride high electron mobility transistor as described in Item 1 of the patent application scope, wherein the high dielectric constant passivation layer material is einsteinium dioxide, yttrium oxide, rhenium oxide, titanium oxide or zirconium oxide material. 如申請專利範圍第2項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該高介電常數之鈍化層係設置於該低介電常數之鈍化層上,而該垂直場板係設置於該高介電常數之鈍化層上。 As described in Item 2 of the patent application scope, the field plate improvement structure of the gallium nitride high electron mobility transistor, wherein the high dielectric constant passivation layer is disposed on the low dielectric constant passivation layer, and the vertical field plate is disposed on the high dielectric constant passivation layer. 如申請專利範圍第6項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該垂直方向之缺口延伸至該氮化鎵緩衝層中的深度大於該氮化鎵緩衝層厚度的1/2。 As described in Item 6 of the patent application, the field plate improvement structure of the gallium nitride high electron mobility transistor, wherein the vertical notch extends into the gallium nitride buffer layer to a depth greater than 1/2 of the thickness of the gallium nitride buffer layer. 如申請專利範圍第7項所述之氮化鎵高電子遷移率電晶體之場板改良結構,其中該垂直場板延伸至該氮化鎵緩衝層中的深度小於該氮化鎵緩衝層厚度的1/2。 An improved field plate structure for a gallium nitride high electron mobility transistor as described in Item 7 of the patent application, wherein the depth of the vertical field plate extending into the gallium nitride buffer layer is less than 1/2 of the thickness of the gallium nitride buffer layer. 如申請專利範圍第2項所述之氮化鎵高電子遷移率電晶體之場板改良結構,進一步包含一平行場板係設置於該汲極延向該閘極之該雙層鈍化層上方。 The improved field plate structure of the gallium nitride high electron mobility transistor as described in Item 2 of the patent application further includes a parallel field plate disposed above the double passivation layer extending from the drain to the gate.
TW112140958A 2023-10-24 2023-10-24 Improved Field Plate Structure of GaN High Electron Mobility Transistor TWI869004B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW112140958A TWI869004B (en) 2023-10-24 2023-10-24 Improved Field Plate Structure of GaN High Electron Mobility Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW112140958A TWI869004B (en) 2023-10-24 2023-10-24 Improved Field Plate Structure of GaN High Electron Mobility Transistor

Publications (2)

Publication Number Publication Date
TWI869004B true TWI869004B (en) 2025-01-01
TW202519027A TW202519027A (en) 2025-05-01

Family

ID=95152192

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112140958A TWI869004B (en) 2023-10-24 2023-10-24 Improved Field Plate Structure of GaN High Electron Mobility Transistor

Country Status (1)

Country Link
TW (1) TWI869004B (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027759A (en) * 2008-12-10 2010-07-16 Transphorm Inc Semiconductor heterostructure diodes
US20210126120A1 (en) * 2019-10-23 2021-04-29 Analog Devices, Inc. Modification of electric fields of compound semiconductor devices
CN112968059A (en) * 2021-02-04 2021-06-15 宁波海特创电控有限公司 Novel enhancement mode gaN HEMT device structure
US20210265477A1 (en) * 2020-02-25 2021-08-26 Cambridge Electronics, Inc. III-Nitride Transistor With A Cap Layer For RF Operation
TW202205603A (en) * 2020-07-24 2022-02-01 世界先進積體電路股份有限公司 Semiconductor device and operation circuit
US20220209000A1 (en) * 2019-04-30 2022-06-30 Dalian University Of Technology High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor
TW202230799A (en) * 2021-01-15 2022-08-01 世界先進積體電路股份有限公司 High electron mobility transistor and fabrication method thereof
CN116053293A (en) * 2022-09-09 2023-05-02 西安电子科技大学 P-GaN enhancement-mode Gallium Nitride high electron mobility transistors for single event burnout resistance
US20230299190A1 (en) * 2020-08-05 2023-09-21 Transphorm Technology, Inc. Iii-nitride devices including a depleting layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027759A (en) * 2008-12-10 2010-07-16 Transphorm Inc Semiconductor heterostructure diodes
US20220209000A1 (en) * 2019-04-30 2022-06-30 Dalian University Of Technology High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor
US20210126120A1 (en) * 2019-10-23 2021-04-29 Analog Devices, Inc. Modification of electric fields of compound semiconductor devices
US20210265477A1 (en) * 2020-02-25 2021-08-26 Cambridge Electronics, Inc. III-Nitride Transistor With A Cap Layer For RF Operation
TW202205603A (en) * 2020-07-24 2022-02-01 世界先進積體電路股份有限公司 Semiconductor device and operation circuit
US20230299190A1 (en) * 2020-08-05 2023-09-21 Transphorm Technology, Inc. Iii-nitride devices including a depleting layer
TW202230799A (en) * 2021-01-15 2022-08-01 世界先進積體電路股份有限公司 High electron mobility transistor and fabrication method thereof
CN112968059A (en) * 2021-02-04 2021-06-15 宁波海特创电控有限公司 Novel enhancement mode gaN HEMT device structure
CN116053293A (en) * 2022-09-09 2023-05-02 西安电子科技大学 P-GaN enhancement-mode Gallium Nitride high electron mobility transistors for single event burnout resistance

Also Published As

Publication number Publication date
TW202519027A (en) 2025-05-01

Similar Documents

Publication Publication Date Title
CN103035706B (en) A kind of vertical gallium nitride radical heterojunction field effect transistor with polarization doping current barrier layer
CN104201201B (en) A kind of adaptive-biased field plate for GaN base HEMT device
CN105261643B (en) A kind of high-breakdown-voltage GaN base transistor with high electronic transfer rate
CN104681617A (en) A Semiconductor Device And A Method For Manufacturing A Semiconductor Device
JP2016511544A (en) Electrode of semiconductor device and manufacturing method thereof
CN103367403A (en) Semiconductor device and manufacturing method thereof
TW201914026A (en) Nitride semiconductor component
CN104347701B (en) A kind of field-effect transistor with composite passivated Rotating fields
CN103632948B (en) A kind of semiconductor devices and its manufacturing method
CN104051523A (en) Semiconductor device with low ohmic contact resistance and manufacturing method thereof
CN104393040A (en) HEMT device with charged media
CN104157691A (en) Semiconductor device and manufacturing method thereof
US20240355921A1 (en) Folded channel gallium nitride based field-effect transistor and method of manufacturing the same
CN104992971B (en) Vertical GaN-based Heterojunction Field Effect Transistor with Composite Low-K Current Blocking Layer
CN111969047A (en) Gallium nitride heterojunction field effect transistor with composite back barrier layer
CN105870164A (en) Gallium nitride-based transistor with high electron mobility
CN105244376A (en) Enhanced AlGaN/GaN high electron mobility transistor
JP2020047741A (en) Semiconductor device
CN108878524A (en) A kind of GaN base transistor with high electronic transfer rate
CN115274846B (en) High Electron Mobility Transistor
Ajayan et al. Challenges and Advances in Materials and Fabrication Technologies for the Development of p-GaN Gated E-Mode AIGaN/GaN Power HEMTs: A Critical Review
TWI869004B (en) Improved Field Plate Structure of GaN High Electron Mobility Transistor
CN104393045B (en) A kind of new GaN base enhancement mode HEMT device and preparation method thereof
CN108807500A (en) A kind of enhancement type high electron mobility transistor with high threshold voltage
CN104282735A (en) Field effect transistor with anion injection passivation layer