TWI862352B - 3d phase change memory and method of manufacturing the same - Google Patents

Abstract

A method of manufacturing 3D phase change memory, including steps of forming a layer stack consisted of alternately stacked first layers and second layers on a substrate, forming a trench through entire layer stack in the layer stack, removing parts of the second layers exposed from the trench to form multiple lateral recesses, forming adhesive layer on the surface of lateral recesses, forming top electrodes filling up the lateral recesses on the adhesive layer, forming ovonic threshold switch (OTS) layers and phase change layers on two sidewalls of the trench, forming a bottom electrode filling up the trench, and removing parts of the bottom electrode and parts of the two phase change layers to form multiple holes extending from the substrate to the surface of layer stack in vertical direction.

Description

Three-dimensional phase change memory and its manufacturing method

The present invention relates to a phase change memory, and more specifically, to a three-dimensional phase change memory with a vertical XPoint architecture and a method for manufacturing the same.

Storage Class Memory (SCM) is one of the hottest storage technologies in recent years. Its features include high-speed access performance with a latency between DRAM and Flash, and non-volatile data storage. It can effectively solve the problem of large differences in access latency between different levels in the current data processing architecture, especially the latency gap between DRAM and solid-state drives (SSDs) (which can be up to a thousand times higher), and does not have the inherent disadvantages of non-volatile memories such as DRAM, such as energy consumption and easy data loss.

There are many emerging memories suitable for storage-class memory, including resistive memory such as magnetoresistive random access memory (MRAM), phase change memory (PCM), variable resistance memory (ReRAM), etc., or charge capture memory such as single-level cell (SLC) 3D NOR or 3D NAND. Among them, phase change memory (PCM) is the only storage-class memory suitable for all aspects of the artificial intelligence Internet of Things (AIoT) field, including as a storage type (S-type) solid-state hard drive or a memory type (M-type) processing in memory (PIM), which has great development potential.

However, most of the current phase change memory is a planar Xpoint type similar to NAND memory, and its storage density is limited. Although the phase change memory can be made with a structure similar to 3D NAND memory, it can greatly improve the storage density, but the multi-layer structural characteristics of the phase change memory (up to 5-7 layers) make its process quite complicated, especially in the atomic-level film deposition process, its process cost is quite expensive. On the other hand, as the number of stacked layers of the 3D memory architecture increases, it becomes very difficult to form holes with uniform aspect ratios. Therefore, general technicians in this field still need to improve the existing phase change memory structure and process in order to overcome the above shortcomings.

In view of the shortcomings of the above-mentioned prior art, the present invention proposes a novel three-dimensional phase change memory (PCM) and its manufacturing method, which is characterized in that the memory unit is formed in the form of grooves rather than holes. In this way, the atomic-level deposition process is only required when forming the lower electrode part, which can greatly reduce the manufacturing cost and time, and realize the mass production and application of phase change memory in the field of storage-level memory (SCM).

One aspect of the present invention is to provide a method for manufacturing a three-dimensional phase change memory, comprising: providing a substrate; forming a plurality of first layers and a plurality of second layers alternately stacked on the substrate to form a stacked structure; performing a first photolithography process to form a groove in the stacked structure, wherein the groove extends from the substrate to a vertical direction perpendicular to the substrate and passes through the entire stacked structure, and the groove extends to a horizontal second direction; performing an etching process to remove a portion of the second layers exposed from the groove, so that each of the second layers is recessed from the groove to a horizontal first direction to form a lateral groove, wherein the first direction is orthogonal to the second direction; forming an adhesive layer on the surface of each of the lateral grooves; An upper electrode is formed on each of the adhesive layers, and each of the upper electrodes fills one of the lateral grooves, wherein the side surfaces of the adhesive layers and the upper electrodes are flush with the side surfaces of the first layers exposed from the trench, and together constitute two opposite side walls of the trench in the first direction; bidirectional valve switch layers are sequentially formed on the two side walls of the trench respectively. and a phase change layer; forming a lower electrode between the two phase change layers in the trench to fill the trench; and performing a second photolithography process to remove part of the lower electrode and part of the two phase change layers to form a plurality of holes extending from the substrate in the vertical direction to the surface of the stacked structure, and the holes are arranged in the trench along the second direction.

Another aspect of the present invention is to provide a method for manufacturing a three-dimensional phase change memory, comprising: providing a substrate; forming a plurality of first layers and a plurality of second layers stacked alternately on the substrate to form a stacked structure; performing a first photolithography process to form a first trench in the stacked structure, wherein the first trench extends from the substrate to a vertical direction perpendicular to the substrate and passes through the entire stacked structure, and the trench extends to a horizontal second direction; performing an etching process to remove a portion of the second layers exposed from the trench, so that each of the second layers is recessed from the first trench to a horizontal first direction to form a first lateral groove, wherein the first direction is orthogonal to the second direction; and performing a first lateral groove on each of the first lateral grooves. A bidirectional valve switch layer is formed in the groove, each of which fills one of the first lateral grooves, wherein the side surfaces of the bidirectional valve switch layers are flush with the side surfaces of the first layers exposed from the groove, and together constitute two side walls of the groove opposite to each other in the first direction; a phase change layer is formed on the two side walls of the first groove respectively ; forming a lower electrode between the two phase change layers in the first trench to fill the first trench; and performing a second photolithography process to remove part of the lower electrode and part of the two phase change layers to form a plurality of holes extending from the substrate in the vertical direction to the surface of the stacked structure, and the holes are arranged in the trench along the second direction.

These and other purposes of the present invention should become more apparent after the reader reads the detailed description of the preferred embodiment described below with various diagrams and drawings.

100: Base

102:Layered structure

104: First level

106: Second level

108: Groove

110: Lateral groove

111: Adhesive layer

112: Upper electrode (word line)

112a: Upper electrode layer

114: Bidirectional valve switch layer

116,116a,116b: Phase change layer

118,118a,118b: Lower electrode

120: Heating layer

121: Hole

122: Isolation structure

200: Base

202:Layered structure

204: First level

206: Second level

208: Groove

210,226: Lateral grooves

212: Upper electrode layer (word line)

214: Bidirectional valve switch layer

216,216a,216b: Phase change layer

218,218a,218b:Lower electrode

220: Heating layer

221: Hole

222: Isolation structure

224: Groove

D1: First direction

D2: Second direction

D _V : Vertical direction

Figure 1 is a top view schematic diagram of a three-dimensional phase change memory according to an embodiment of the present invention; Figures 2 to 7 are cross-sectional schematic diagrams of a manufacturing process of a three-dimensional phase change memory according to an embodiment of the present invention; Figure 8 is a top view schematic diagram of a three-dimensional phase change memory according to another embodiment of the present invention; Figures 9 to 12 are cross-sectional schematic diagrams of a manufacturing process of a three-dimensional phase change memory according to an embodiment of the present invention; Figure 13 is a top view schematic diagram of a three-dimensional phase change memory according to another embodiment of the present invention; Figure 14 is a cross-sectional schematic diagram of a three-dimensional phase change memory according to an embodiment of the present invention. FIG15 is a schematic cross-sectional view of a three-dimensional phase change memory manufacturing process according to an embodiment of the present invention; and FIG16 to FIG19 are schematic cross-sectional views of a three-dimensional phase change memory manufacturing process according to an embodiment of the present invention; It should be noted that all the diagrams in this specification are of a legend nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the same reference symbols in the diagram will be used to indicate corresponding or similar component features after modification or in different embodiments.

Now, the following will describe in detail an exemplary embodiment of the present invention, which will refer to the attached figures to illustrate the described features so that the reader can understand and achieve the technical effect. The reader will understand that the description in the text is only by way of example and is not intended to limit the present invention. The various embodiments of the present invention and the various features in the embodiments that do not conflict with each other can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "above" and "above" in this case should be interpreted in a broad manner, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intervening feature or layer, and "on" or "above" not only means "on" or "above" something but also includes the meaning of being "on" or "above" something with no intervening features or layers (i.e., directly on something). In addition, spatially related terms such as "under", "below", "lower", "above", "upper", etc. may be used herein for the convenience of description to describe the relationship between one element or feature and another or more elements or features, as shown in the accompanying drawings.

As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of the lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and/or along an inclined surface. A substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnects, and/or vias are formed) and one or more dielectric layers.

Readers can generally understand terms at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the", or "said" can likewise be understood to convey singular usage or to convey plural usage. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

Readers can further understand that when the words "include" and/or "contain" are used in this specification, they specify the existence of the described features, regions, wholes, steps, operations, elements and/or components, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and/or their combinations.

Please refer to Figure 1 and Figure 6, which respectively show a top view and a cross-sectional view of a three-dimensional phase change memory according to an embodiment of the present invention, wherein the plane shown in Figure 1 is a horizontal cross-section with an upper electrode 112, and Figure 6 is a cross-sectional view taken along the line A-A' in Figure 1, so that readers can understand the plane layout of the phase change memory of the present invention and the relative positions and connection relationships of the main components in each layer structure. The phase change memory of the present invention is a 3D Xpoint architecture, and the intersection of its multi-layer word lines and multiple vertical bit lines is the location of the memory unit.

The three-dimensional phase change memory of the present invention is constructed on a substrate 100. The material of the substrate 100 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-covered substrates (such as GaN-on-silicon) or silicon-covered insulator (SOI) substrates, or other doped substrates, but are not limited thereto. In other embodiments, the substrate 100 may also be one of the inter-metal dielectrics (IMD) in the semiconductor back-end process. A stacked structure 102 is formed on a substrate 100, which is composed of a plurality of alternating first layers 104 and second layers 106. The number of stacked layers can be as high as hundreds of layers to increase the number of storage cells. In this embodiment, the materials of the first layer 104 and the second layer 106 can be silicon oxide and polysilicon, or silicon oxide and silicon nitride, respectively. The materials of these two layers have electrical insulation and have a significant etching selectivity. A trench 108 extends from the substrate 100 to a vertical direction D _V perpendicular to the substrate, passes through the entire stacked structure 102, and extends to a horizontal second direction D2. Furthermore, each second layer 106 is recessed from the trench 108 in a horizontal first direction D1 to form a lateral groove 110, and the first direction D1 is preferably orthogonal to the second direction D2. Thus, the stacked structure 102 is formed with a trench 108 and a plurality of lateral grooves 110 extending from both sides of the trench 108 and alternately located at different layers with the first layer 104.

Still referring to FIG. 1 and FIG. 6 . A conformal adhesion layer 111 is formed on the surface of each lateral groove 110 , which may be made of a conductive material. The rest of the space of each lateral groove 110 is filled with an upper electrode 112 , and the material of the upper electrode may be a metal with good conductivity such as tungsten, copper, aluminum, or an alloy thereof. In the embodiment of the present invention, the upper electrode 112 is the word line of the three-dimensional phase change memory, which is located at different levels and separated by the electrically insulating first layer 104. With this arrangement, in the embodiment of the present invention, the two side walls of the trench 108 located in the first direction D1 will have a plurality of word lines 112 , which are located at different levels and extend horizontally in the second direction D2 like the trench 108 . The extended word lines 112 may form a stepped structure and be connected to the external circuit above through the contacts thereon (not shown). Preferably, the upper electrodes 112, the adhesive layer 111, and the side surfaces of the first layer 104 in the first direction D1 are flush.

Still referring to FIG. 1 and FIG. 6 , an ovonic threshold switch (OTS) 114 and a plurality of phase change layers 116a, 116b are sequentially formed on the two sidewalls of the trench 108 in the first direction D1. The ovonic threshold switch layer 114 is used as a selector of the phase change memory, and covers the sidewalls formed by the first layer 104 and the upper electrode 112 and is in direct contact with them. The material of the bidirectional valve switch layer 114 can be an amorphous chalcogenide, such as selenium (Se) doped germanium telluride (GeTe), which has the characteristics of high selectivity, fast switching speed and bidirectional operation, and will not crystallize at the operating temperature of the phase change memory. The phase change layers 116a, 116b are storage units of the phase change memory. In the embodiment of the present invention, a plurality of phase change layers 116a, 116b are formed on the sidewalls of the bidirectional valve switch layer 114 and are separated and alternately arranged along the second direction D2. The phase change layers 116a and 116b are the odd memory cells and even memory cells of the three-dimensional phase change memory, respectively. The materials thereof may be germanium antimony telluride (GeSbTe, GST) alloys, such as nitrogen-doped germanium antimony telluride, antimony telluride (Sb ₂ Te), germanium antimony (GeSb) or indium-doped antimony telluride, etc. They have the characteristics of stable structure, stable resistance and fast crystallization speed. At the operating temperature of the phase change memory, they will crystallize, causing their resistance to change, thereby achieving a resistive storage mechanism.

Still referring to FIG. 1 and FIG. 6 . A plurality of lower electrodes 118a, 118b are located between the phase change layers 116a, 116b on both sides and fill the trench 108. In the embodiment of the present invention, the lower electrodes 118a, 118b are respectively the odd bit line and the even bit line of the three-dimensional phase change memory, which are in a columnar shape extending from the substrate 100 in the vertical direction D _V to the surface of the stacked structure 102, and are separated and alternately arranged along the second direction D2. In the read operation, the function of the lower electrodes 118a, 118b is to detect the resistance value of the phase change layers 116a, 116b corresponding to the two sides thereof, so as to know the storage state, such as 0 or 1 bit. Furthermore, in the embodiment of the present invention, a plurality of holes 121 are formed in the stacked structure 102, as shown in FIG. 7 (a cross-sectional view taken along the section line BB' in FIG. 1), which extend from the substrate 100 in the vertical direction D _V to the surface of the stacked structure 102. In the embodiment of the present invention, the holes 121 are components for separating the lower electrodes 118a, 118b from each other and the phase change layers 116a, 116b from each other. The holes 121 extend in the first direction D1 to the bidirectional valve switch layer 114 on both sides, and are arranged and aligned at equal intervals in the second direction D2, thereby separating the plurality of lower electrodes 118a, 118b and the phase change layers 116a, 116b. In other embodiments, the hole 121 may be filled with an insulating material, such as silicon oxide, to form an isolation structure 122, which may also separate the lower electrodes and the phase change layers.

Still referring to FIG. 1 and FIG. 6 . In addition to the above components, in the embodiment of the present invention, a heating layer 120 may be formed between the upper electrode 112 and the bidirectional valve switch layer 114, or between the bidirectional valve switch layer 114 and the phase change layers 116a, 116b, or between the phase change layers 116a, 116b and the lower electrodes 118a, 118b. The function of the heating layer 120 is to heat the bidirectional valve switch layer 114 and the phase change layers 116a, 116b, so that the phase change layers 116a, 116b produce phase conversion, thereby achieving memory storage operation. The material of the heating layer 120 may be amorphous carbon (σ-C), titanium nitride (TiN), titanium oxynitride (TiN _x O _y ), tantalum nitride (TaN), or titanium aluminum nitride (TiAlN) with good thermal conductivity.

Next, please refer to Figures 2 to 7 in sequence, which illustrate cross-sectional schematic diagrams of the manufacturing process of the three-dimensional phase change memory in the above-mentioned embodiment of the present invention.

Please refer to FIG. 2. First, a substrate 100 is provided. The material of the substrate 100 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-covered substrates (such as GaN-on-silicon) or silicon-covered insulator (SOI) substrates, or other doped substrates, but are not limited thereto. In other embodiments, the substrate 100 may also be one of the intermetallic dielectric layers (IMD) in the semiconductor back-end process. Next, a plurality of first layers 104 and a plurality of second layers 106 are alternately formed on the substrate 100, so as to form a stacked structure 102. The materials of the first layer 104 and the second layer 106 can be silicon oxide and polysilicon, or silicon oxide and silicon nitride, respectively, which can be formed by a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). After the stacked structure 102 is formed, a photolithography process is then performed to form a trench 108 in the stacked structure 102, which extends from the substrate 100 to the vertical direction D _V through the entire stacked structure 102 and extends to the horizontal second direction D2 (Figure 1). It should be noted that compared with the formation of holes in the prior art, the formation of trenches is easier to achieve a uniform aspect ratio, so that the electrical properties of the memory cell finally formed are better, which is its advantage.

Please refer to Figure 3. After the trench 108 is formed, a selective etching process is then performed to remove the portion of the second layer 106 exposed from the trench 108. The first layer 104 will not be removed in this process. In this way, each second layer 106 is recessed from the trench 108 in a horizontal first direction D1 to form a lateral groove 110. The first direction D1 is orthogonal to the second direction D2 (Figure 1). The lateral groove 110 extends from both sides of the trench 108 and is located at different layers in an alternating manner with the first layer 104.

Please refer to Figure 4. After the lateral groove 110 is formed, a conformal adhesion layer 111 and an upper electrode layer 112a are sequentially formed on the surface of the lateral groove 110 on both sides of the trench 108 in the first direction D1 and the side surfaces of the first layers 104. Each upper electrode layer 112a will fill the lateral groove 110 on one side of the trench 108 and cover the side.

In the embodiment of the present invention, the material of the adhesion layer 111 can be silicon oxide, and the material of the upper electrode layer 112a can be metals such as tungsten, copper, aluminum, or alloys thereof, which can be formed by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). After the adhesion layer 111 and the upper electrode layer 112a are formed, the trench 108 will still exist.

Please refer to Figure 5. After the adhesive layer 111 and the upper electrode layer 112a are formed, a lateral etching process is then performed to horizontally remove the two upper electrode layers 112a and the two adhesive layers 111 on both sides of the groove 108 until the first layer 104 is exposed, thereby forming the adhesive layer 111 located only on the surface of the lateral groove 110 and the upper electrode 112 located on the adhesive layers 111 and filling the lateral groove 110. Due to this process, the upper electrodes 112, the adhesive layers 111, and the side surfaces of the first layers 104 in the first direction D1 are preferably aligned, and together constitute two opposite side walls of the trench 108 in the first direction D1.

Please refer to Fig. 6. Then, a bidirectional valve switch layer 114 and a phase change layer 116 are sequentially formed on both side walls of the trench 108 in the first direction D1, and a lower electrode 118 is filled in the remaining space of the trench 108. The step of forming the bidirectional valve switch layer 114 and the phase change layer 116 may include first forming a conformal bidirectional valve switch layer 114 and a phase change layer 116 on the two side walls of the trench 108, the surface of the substrate 100 and the surface of the stack structure 102 in sequence, and then performing an anisotropic etching process to remove the bidirectional valve switch layer 114 and the phase change layer 116 on the horizontal plane, so that the stack structure 102 and the substrate 100 are exposed and the two bidirectional valve switch layers 114 and the two phase change layers 116 are left on the two side walls of the trench 108. In the embodiment of the present invention, the material of the bidirectional threshold switch layer 114 may be an amorphous chalcogenide, such as selenium (Se) doped germanium telluride (GeTe), and the material of the phase change layer 116 may be a germanium antimony telluride (GeSbTe, GST) alloy, such as nitrogen-doped germanium antimony telluride, antimony telluride ( _Sb2Te ), germanium antimony (GeSb) or indium-doped antimony telluride, both of which may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) processes. The material of the lower electrode 118 can be the same as that of the upper electrode 112, such as tungsten, copper, aluminum or other metals or alloys thereof, and can be formed by atomic layer deposition (ALD). It should be noted that in this process, compared with the conventional technology, since the present invention uses trenches instead of holes to form memory cells, it is easier to maintain a consistent film depth and width. In this way, only when forming the lower electrode portion, a relatively expensive atomic layer deposition process and machine are required, which can greatly reduce the manufacturing cost and time, and realize the mass production and application of phase change memory in the field of storage-level memory (SCM).

Finally, please refer to FIG. 1 and FIG. 7 at the same time. After the bidirectional valve switch layer 114, the phase change layer 116 and the lower electrode 118 are formed, a photolithography process is then performed to remove part of the lower electrode 118 and part of the two phase change layers 116 to form a plurality of holes 121 in the stacked structure 102. The holes 121 will pass through part of the phase change layer 116 and the lower electrode 118, and extend from the substrate 100 in the vertical direction D _V to the surface of the stacked structure 102, and the holes 121 will extend in the first direction D1 to the bidirectional valve switch layer 114 on both sides, and are arranged along the second direction D2. Thus, the holes 121 will separate the original phase change layer 116 and the lower electrode 118 into a plurality of phase change layers 116a, 116b and a plurality of lower electrodes 118a, 118b, wherein the phase change layers 116a, 116b are respectively the odd memory cells and even cells of the three-dimensional phase change memory, and the lower electrodes 118a, 118b are respectively the odd bit lines and even bit lines of the three-dimensional phase change memory. In addition, an insulating material such as silicon oxide may be filled into the hole 121 to form an isolation structure 122 to cut and separate the lower electrodes 118a, 118b and the phase change layers 116a, 116b.

Now please refer to Figures 8 and 18, which respectively show a top view and a cross-sectional view of a three-dimensional phase change memory according to another embodiment of the present invention, wherein the plane shown in Figure 8 is a horizontal cross-section with an upper electrode layer 212, and Figure 18 is a cross-sectional view taken along the line A-A' in Figure 8, so that readers can understand the plane layout of the phase change memory of the present invention and the relative positions and connection relationships of the main components of each layer. The main difference between this embodiment and the aforementioned embodiment is that the bidirectional valve switch layer 214 is filled in the lateral groove 210, and the upper electrode layer 212 replaces the second layer 206 in the original stacked structure 202 at the end of the process.

First, the three-dimensional phase change memory is constructed on a substrate 200. The material of the substrate 200 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-coated substrates (such as GaN-on-silicon) or silicon-coated insulator (SOI) substrates, or other doped types of substrates, but are not limited thereto. In other embodiments, the substrate 200 may also be one of the intermetallic dielectric layers (IMD) in the semiconductor back-end process. A stacked structure 202 is formed on the substrate 200, which is composed of a plurality of alternating first layers 204 and upper electrode layers 212. The number of stacked layers can be as high as hundreds of layers to increase the number of storage units. In this embodiment, the material of the first layer 204 may be silicon oxide, and the material of the upper electrode layer 212 may be metal such as tungsten, copper, aluminum, or alloys thereof. In the embodiment of the present invention, the upper electrode layer 212 is the word line of the three-dimensional phase change memory, which is located at different levels and separated by the electrically insulated first layer 204. The extended word line 212 may form a step-like structure and be connected to the external circuit above through the contacts thereon (not shown).

Still referring to FIG. 8 and FIG. 18 . A trench 208 extends from the substrate 200 to a vertical direction D _V perpendicular to the substrate, through the entire stacked structure 202, and extends to a horizontal second direction D2. Furthermore, each upper electrode layer 212 is recessed from the trench 208 to a horizontal first direction D1 to form a lateral groove 210, and the first direction D1 is preferably orthogonal to the second direction D2. In this way, a trench 208 and a plurality of lateral grooves 210 extending from both sides of the trench 208 and alternately located at different layers with the first layer 204 are formed in the stacked structure 202. The space of each lateral groove 210 is filled with a bidirectional valve switch layer 214. The bidirectional valve switch layer 214 is used as a selector of the phase change memory. The material of the bidirectional valve switch layer 214 can be an amorphous chalcogenide, such as selenium (Se) doped germanium telluride (GeTe), which has the characteristics of high selectivity, fast switching speed and bidirectional operation, and will not crystallize at the operating temperature of the phase change memory. Preferably, the bidirectional valve switch layers 214 and the first layer 204 are flush on the side in the first direction D1, and together constitute the two opposite side walls of the groove 208 in the first direction D1. With this arrangement, in the embodiment of the present invention, the two side walls of the trench 208 in the first direction D1 are formed by the two-way valve switch layer 214 and the first layer 204 . The multiple two-way valve switch layers 214 are located at different levels and extend horizontally in the second direction D2 like the trench 208 .

Still referring to FIG. 8 and FIG. 18 . A plurality of phase change layers 216a, 216b are formed on the two sidewalls of the trench 208 in the first direction D1 as odd memory cells and even memory cells of the phase change memory. In the embodiment of the present invention, a plurality of phase change layers 216a, 216b are formed on the sidewalls of the bidirectional valve switch layer 214 and are spaced and alternately arranged along the second direction D2. The material of the phase change layers 216a, 216b can be a germanium antimony telluride (GeSbTe, GST) alloy, such as nitrogen-doped germanium antimony telluride, antimony telluride ( _Sb2Te ), germanium antimony (GeSb) or indium-doped antimony telluride, which has the characteristics of stable structure, stable resistance and fast crystallization speed. It will crystallize at the operating temperature of the phase change memory, causing its resistance to change, thereby achieving a resistive storage mechanism.

Still referring to FIG. 8 and FIG. 18. A plurality of lower electrodes 218a, 218b are respectively located between the phase change layers 216a, 216b of the odd/even memory cells and fill the trench 208. In the embodiment of the present invention, the lower electrodes 218a, 218b are respectively the odd bit lines and the even bit lines of the three-dimensional phase change memory, which are in a columnar shape extending from the substrate 200 in the vertical direction D _V to the surface of the stacked structure 202, and are separated and alternately arranged along the second direction D2. In the read operation, the function of the lower electrodes 218a, 218b is to detect the resistance values of the phase change layers 216a, 216b corresponding to the two sides thereof, so as to know the storage state, such as 0 or 1 bit. Furthermore, in the embodiment of the present invention, a plurality of holes 221 are formed in the stacked structure 102, as shown in FIG. 19 (a cross-sectional view taken along the section line BB' in FIG. 8), which extend from the substrate 200 in the vertical direction D _V to the surface of the stacked structure 202. In the embodiment of the present invention, the holes 221 are components for separating the lower electrodes 218a, 218b from each other and the phase change layers 216a, 216b from each other. The holes 221 extend in the first direction D1 through the bidirectional valve switch layer 214 to the upper electrode layers 212 on both sides, and are arranged and aligned at equal intervals in the second direction D2, thereby separating the plurality of lower electrodes 218a, 218b and the phase change layers 216a, 216b. In other embodiments, the hole 221 may be filled with an insulating material, such as silicon oxide, to form an isolation structure 222, which may also cut and separate the lower electrodes and separate the phase change layers. In addition, although the hole 221 in FIG. 8 extends to the upper electrode layer 212, in other embodiments, the hole 221 may also extend only to the bidirectional valve switch layer 214, as long as the lower electrodes 218a, 218b and the phase change layers 216a, 216b are separated by the hole 221.

Refer to FIG. 8 and FIG. 18 again. In addition to the above components, in the embodiment of the present invention, a heating layer 220 can be formed between the upper electrode layer 212 and the bidirectional valve switch layer 214, or between the bidirectional valve switch layer 214 and the phase change layers 216a, 216b, or between the phase change layers 216a, 216b and the lower electrodes 218a, 218b. The function of the heating layer 220 is to heat the bidirectional valve switch layer 214 and the phase change layers 216a, 216b, so that the phase change layers 216a, 216b produce phase conversion, thereby achieving memory storage operation. The material of the heating layer 220 may be amorphous carbon (σ-C), titanium nitride (TiN), titanium oxynitride (TiN _x O _y ), tantalum nitride (TaN), or titanium aluminum nitride (TiAlN) with good thermal conductivity.

Next, please refer to Figures 9 to 12 in sequence, which illustrate cross-sectional schematic diagrams of the manufacturing process of the three-dimensional phase change memory in the above-mentioned embodiment of the present invention.

Please refer to FIG. 9. First, a substrate 200 is provided. The material of the substrate 200 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-covered substrates (such as GaN-on-silicon) or silicon-covered insulator (SOI) substrates, or other doped substrates, but are not limited thereto. In other embodiments, the substrate 200 may also be one of the intermetallic dielectric layers (IMD) in the semiconductor back-end process. Next, a plurality of first layers 204 and a plurality of second layers 206 are alternately formed on the substrate 200, so as to form a stacked structure 202. The material of the first layer 204 may be silicon oxide, and the material of the second layer 206 may be silicon nitride. Both may be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and may have a significant etching selectivity under a specific etching process. After the stacked structure 202 is formed, a photolithography process is then performed to form a trench 208 in the stacked structure 202, which extends from the substrate 200 in a vertical direction D _V through the entire stacked structure 202, and extends in a horizontal second direction D2. It should be noted that compared with the prior art of forming holes, the formation of trenches is easier to achieve a uniform aspect ratio, which is its advantage.

Please refer to Figure 10. After the trench 208 is formed, a selective etching process is then performed to remove the portion of the second layer 206 exposed from the trench 208. The first layer 204 will not be removed in this process, so that each second layer 206 is recessed from the trench 208 in the horizontal first direction D1 to form a lateral groove 210. The lateral groove 210 extends from both sides of the trench 208 and is located at a different layer in an alternating manner with the first layer 204.

Please refer to FIG. 11. After the lateral groove 210 is formed, a bidirectional valve switch layer 214 is then formed in the lateral groove 210 on both sides of the trench 208 in the first direction D1. The bidirectional valve switch layer 214 can be formed by first forming a bidirectional valve switch layer 214 in the lateral groove 210 and on the side wall of the first layer 204, and then performing a lateral etching process to horizontally remove the bidirectional valve switch layer 214 on both sides of the trench 208 until the first layer 204 is exposed, thereby forming a bidirectional valve switch layer 214 located only in the lateral groove 210. Due to this process, the bidirectional valve switch layer 214 and the first layer 204 are preferably aligned with each other on the side surface in the first direction D1. In the embodiment of the present invention, the material of the bidirectional valve switch layer 214 can be an amorphous chalcogenide, such as selenium (Se) doped germanium telluride (GeTe), which can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes.

Please refer to FIG. 12. Then, a phase change layer 216 is formed on both side walls of the trench 208 in the first direction D1, and the lower electrode 218 is filled in the remaining space of the trench 208 between the two side walls. The step of forming the phase change layer 216 may include first forming a conformal phase change layer 216 on both side walls of the trench 208, the surface of the substrate 200, and the surface of the stacked structure 202, and then performing an anisotropic etching process to remove the phase change layer 216 on the horizontal plane, so that the stacked structure 202 and the substrate 200 are exposed and two phase change layers 216 are left on both side walls of the trench 208. In the embodiment of the present invention, the material of the phase change layer 216 can be a germanium antimony telluride (GeSbTe, GST) alloy, such as nitrogen-doped germanium antimony telluride, antimony telluride (Sb ₂ Te), germanium antimony (GeSb) or indium-doped antimony telluride, etc., and can be formed by physical vapor deposition (PVD) or atomic layer deposition (ALD) processes. The material of the lower electrode 218 can be a metal such as tungsten, copper, aluminum or an alloy thereof, and can be formed by atomic layer deposition (ALD). It should be noted that in this process, compared to the conventional technology, since the present invention uses trenches rather than holes to form memory cells, it is easier to maintain a consistent film aspect ratio. In this way, only when forming the lower electrode portion, a relatively expensive atomic layer deposition process and equipment are required, which can greatly reduce the manufacturing cost and time, and realize the mass production and application of phase change memory in the storage level memory (SCM) field.

Next, please refer to FIG. 13 and FIG. 14 at the same time, where FIG. 13 is a top view schematic diagram of the three-dimensional phase change memory in the process of this embodiment, and FIG. 14 is a cross-sectional schematic diagram made by the section line BB' in FIG. 13, and the previous FIG. 12 is a cross-sectional schematic diagram made by the section line AA' in FIG. 13. After the bidirectional valve switch layer 214, the phase change layer 216 and the lower electrode 218 are formed, a photolithography process is then performed to form a plurality of holes 221 in the stacked structure 202. The holes 221 pass through a portion of the phase change layer 216 and the bottom electrode 218 and extend from the substrate 200 in the vertical direction D _V to the surface of the stacked structure 202. The holes 221 extend in the first direction D1 through the bidirectional valve switch layer 214 to the second layer 206 on both sides. Thus, the holes 221 will separate the original phase change layer 216 and the lower electrode 218 into a plurality of phase change layers 216a, 216b and a plurality of lower electrodes 218a, 218b, wherein the phase change layers 216a, 216b are respectively the odd memory cells and even cells of the three-dimensional phase change memory, and the lower electrodes 218a, 218b are respectively the odd bit lines and even bit lines of the three-dimensional phase change memory. In addition, an insulating material such as silicon oxide may be filled into the holes 221 to form an isolation structure 222 to separate the lower electrodes 218a, 218b and the phase change layers 216a, 216b.

After the isolation structure 222 is completed, an etching process is then performed to remove the second layer 206 in the stacked structure 202. Please refer to Figures 15 to 17 for the steps of the etching process, wherein Figure 15 is a top view schematic diagram of the three-dimensional phase change memory in this embodiment, and Figures 16 and 17 are cross-sectional schematic diagrams made according to the section line C-C' in Figure 15.

First, as shown in FIG. 15 and FIG. 16 , a photolithography process is performed to form a trench 224 in the stacked structure 202 between the trenches 208 (the previous process has formed the lower electrode 218, the phase change layer 216, the heating layer 220 and other structures in the trenches 208). The trench 224 will vertically extend through all the first layers 204 and the second layers 206 in the stacked structure 202 to reach the substrate 200. From the top view, the trench 224 extends in the second direction D2 through multiple trenches 208 (i.e., memory cells). In the first direction D1, there may be multiple grooves 208 between the grooves 224, such as a group of four grooves 208 as shown in the figure, depending on the design of the product.

As shown in FIGS. 15 and 17 , after the trench 224 is formed, a selective etching process is then performed to completely remove the second layer 206 exposed from the trench 224, while the first layer 204 is not removed in this process, thereby forming a lateral groove 226 defined by the first layer 204 and the bidirectional valve switch layer 214. The lateral groove 226 is recessed from the trench 224 in a horizontal first direction D1 and is located at different levels in the stacked structure 202 in alternation with the first layer 204. Finally, please refer to FIGS. 18 and 19 , which are schematic cross-sectional views taken along the lines A-A’ and B-B’ in FIG. 8 , respectively. After the second layer 206 is removed, metal materials such as tungsten, copper, aluminum or alloys thereof are then filled into the lateral grooves 226 by atomic layer deposition or the like, thereby forming an upper electrode layer 212. The formed upper electrode layer 212 will contact the bidirectional valve switch layer 214 in the stacked structure 202 to complete the final structure of the present invention. In this embodiment, the second layer 206 in the final stacked structure 202 will be replaced by the upper electrode layer 212, which can effectively reduce the parasitic capacitance in the device structure and is suitable for high storage density memory architecture.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

106: Second level

108: Groove

110: Lateral groove

111: Adhesive layer

112: Upper electrode (word line)

114: Bidirectional valve switch layer

116a,116b: Phase change layer

118a,118b: Lower electrode

120: Heating layer

121: Hole

122: Isolation structure

D1: First direction

D2: Second direction

Claims (12)

A method for manufacturing a three-dimensional phase change memory comprises: providing a substrate; forming a plurality of first layers and a plurality of second layers alternately stacked on the substrate to form a stacked structure; performing a first photolithography process to form a trench in the stacked structure, wherein the trench extends from the substrate in a vertical direction perpendicular to the substrate and passes through the entire stacked structure, and the trench extends in a horizontal second direction; performing an etching process to remove portions of the second layers exposed from the trench, Thus, each of the second layers is recessed from the groove in a first horizontal direction to form a lateral groove, wherein the first direction is orthogonal to the second direction; a conformal first adhesion layer and an upper electrode layer are sequentially formed along the side surfaces of the first layers exposed from the groove and the surfaces of the lateral grooves, wherein each of the upper electrode layers fills the lateral grooves and covers the side surfaces of the first layers; a lateral etching process is performed to remove part of the upper electrode layer and the The first adhesive layer is formed by bonding the first adhesive layer to the first layer until the first layers are exposed, so that the first adhesive layer is divided into a plurality of second adhesive layers and the upper electrode layer is divided into a plurality of upper electrodes, wherein each of the second adhesive layers is located on a surface of the side groove, and each of the upper electrodes is located on a second adhesive layer and fills a side groove, wherein the side surfaces of the second adhesive layers and the upper electrodes are flush with the side surfaces of the first layers exposed from the groove, and together constitute the groove at the first adhesive layer. Two side walls opposite to each other in one direction; a bidirectional valve switch layer and a phase change layer are sequentially formed on the two side walls of the trench respectively; a lower electrode is formed between the two phase change layers in the trench to fill the trench; and a second photolithography process is performed to remove part of the lower electrode and part of the two phase change layers to form a plurality of holes extending from the substrate to the vertical direction to the surface of the stacked structure, and the holes are arranged in the trench along the second direction. The method for manufacturing a three-dimensional phase change memory as described in Item 1 of the patent application further includes filling the holes with insulating materials, thereby forming multiple isolation structures that cut off and separate the lower electrode and the two phase change layers. The method for manufacturing a three-dimensional phase change memory as described in item 1 of the patent application, wherein the steps of sequentially forming the two bidirectional valve switch layers and the two phase change layers on the two side walls of the trench include: sequentially forming conformal bidirectional valve switch layers and the phase change layers on the two side walls of the trench, the surface of the substrate, and the surface of the stacked structure; and performing an anisotropic etching process to remove the bidirectional valve switch layers and the phase change layers on the horizontal plane, so that the stacked structure and the substrate are exposed and the two bidirectional valve switch layers and the two phase change layers on the two side walls of the trench remain. The method for manufacturing a three-dimensional phase change memory as described in Item 1 of the patent application further includes forming a heating layer between the upper electrodes and the bidirectional valve switch layers. The method for manufacturing a three-dimensional phase change memory as described in Item 1 of the patent application further includes forming a heating layer between the bidirectional valve switch layers and the phase change layers. The method for manufacturing a three-dimensional phase change memory as described in Item 1 of the patent application further includes forming a heating layer between the phase change layers and the lower electrodes. A method for manufacturing a three-dimensional phase change memory comprises: providing a substrate; forming a plurality of first layers and a plurality of second layers stacked alternately on the substrate to form a stacked structure; performing a first photolithography process to form a first trench in the stacked structure, wherein the first trench extends from the substrate in a vertical direction perpendicular to the substrate and passes through the entire stacked structure, and the first trench extends in a horizontal second direction; performing an etching process to remove a portion of the first trench; The second layers exposed from the first groove are each recessed from the first groove in a first horizontal direction to form a first lateral groove, wherein the first direction is orthogonal to the second direction; a bidirectional valve switch layer is formed in each of the first lateral grooves, each of the bidirectional valve switch layers fills one of the first lateral grooves, wherein the side surfaces of the bidirectional valve switch layers are aligned with the side surfaces of the first layers exposed from the first groove The first trench is provided with a first substrate and a second substrate. The first substrate is provided with a first phase change layer and a second phase change layer. The first substrate is provided with a first phase change layer and a second phase change layer. The first substrate is provided with a first phase change layer and a second phase change layer. The first substrate is provided with a first phase change layer and a second phase change layer. The first substrate is provided with a first phase change layer and a second phase change layer. The first substrate is provided with a first phase change layer and a second phase change layer. The second phase change layer and the second phase change layer are provided with ... Arrange along the second direction in the first trench; perform a third photolithography process to form a plurality of second trenches between the plurality of first trenches; perform a selective etching process to completely remove the second layers exposed from the second trenches, thereby forming a plurality of second lateral grooves defined by the first layers and the bidirectional valve switch layers; and fill the second lateral grooves with metal material, thereby forming a plurality of upper electrode layers. The method for manufacturing a three-dimensional phase change memory as described in Item 7 of the patent application further includes filling the holes with insulating materials to form an isolation structure that cuts off and separates the lower electrode and the two phase change layers. As described in item 7 of the patent application scope, the step of forming a bidirectional valve switch layer in each of the first lateral grooves includes: forming the bidirectional valve switch layer on the side surfaces of the first layers exposed by the first grooves and in the first lateral grooves; and performing a lateral etching process to remove part of the bidirectional valve switch layer in the horizontal direction until the first layers are exposed. As described in item 7 of the patent application, the steps of forming the phase change layer on the two side walls of the first trench include: forming a conformal phase change layer on the two side walls of the first trench, the substrate surface and the surface of the stacked structure; and performing an anisotropic etching process to remove the phase change layer on the horizontal plane, so that the stacked structure and the substrate are exposed and the two phase change layers on the two side walls of the first trench remain. The method for manufacturing a three-dimensional phase change memory as described in Item 7 of the patent application further includes forming a heating layer between the bidirectional valve switch layers and the phase change layers. The method for manufacturing a three-dimensional phase change memory as described in Item 7 of the patent application further includes forming a heating layer between the phase change layers and the lower electrodes.

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