TWI858941B - Electronic device - Google Patents

Abstract

An electronic device includes a first base, electrodes, traces, an insulating layer, a second base and an electrochromic layer. The electrodes are disposed on the first base. Each of the electrodes includes a mesh conductive pattern and a transparent conductive pattern. The mesh conductive pattern has network lines and meshes defined by the network lines. The transparent conductive pattern covers the network lines and the meshes, and is electrically connected to the mesh conductive pattern. The traces are disposed on the first base and are electrically connected to the electrodes respectively. The insulating layer is disposed on the first base and at least covers the traces. The second base is disposed opposite the first base.

Description

Electronic devices

The present invention relates to an electronic device.

A transparent display panel refers to a display device that can provide a transparent display state for the user to view the scene behind it. The transparent display panel has a display area and a transparent area, wherein the display area can provide a display screen for the user to view, and the transparent area is transparent so that the user can view the scene behind it. Pixels are arranged in the display area to emit image beams toward the display surface of the transparent display panel to provide a picture. Affected by the background light, generally speaking, the contrast of the transparent display panel is not high. In order to improve the contrast of the transparent display panel, a dimming panel can be arranged behind the transparent display panel. The dimming panel can be switched to a light-shielding mode to block the background light, thereby improving the contrast.

The dimming panel includes a first substrate, a second substrate disposed opposite to the first substrate, and an electrochromic layer disposed between the first substrate and the second substrate. By controlling the voltage difference between the electrodes of the first substrate and the second substrate, the electrochromic layer can be changed from a transparent state to a light-absorbing state, thereby switching the dimming panel to a light-shielding mode. However, when the electrochromic layer changes from a transparent state to a light-absorbing state, its resistance also decreases. At this time, if the resistance of the electrodes of the first substrate/the electrodes of the second substrate is too high, the driving current will tend to flow through the part of the electrochromic layer that has changed to the light-absorbing state, and it is not easy to flow through the other part of the electrochromic layer that has not yet changed to the light-absorbing state, thereby causing the dimming panel to be unable to turn black in the entire area.

The present invention provides an electronic device with good performance.

The electronic device of the present invention includes a first substrate, a plurality of electrodes, a plurality of wirings, an insulating layer, a second substrate and an electrochromic layer. The plurality of electrodes are disposed on the first substrate. Each electrode includes a mesh conductive pattern and a transparent conductive pattern. The mesh conductive pattern has a plurality of meshes and a plurality of meshes defined by the plurality of meshes. The transparent conductive pattern covers the plurality of meshes and the plurality of meshes and is electrically connected to the mesh conductive pattern. The plurality of wirings are disposed on the first substrate and are electrically connected to the plurality of electrodes respectively. The insulating layer is disposed on the first substrate and at least covers the plurality of wirings. The second substrate is disposed opposite to the first substrate.

In one embodiment of the present invention, each of the above-mentioned traces includes a first metal layer and a second metal layer, the second metal layer covers the top surface and side walls of the first metal layer, the second metal layer is arranged between the insulating layer and the first metal layer, the insulating layer is arranged between the electrochromic layer and the second metal layer, and the insulating layer covers the top surface and side walls of the second metal layer.

In one embodiment of the present invention, the above-mentioned insulating layer is disposed between the transparent conductive pattern of the electrode and the second metal layer of the wiring.

In one embodiment of the present invention, each mesh of the above-mentioned mesh conductive pattern includes a first metal layer and a second metal layer, the second metal layer covers the top surface and side walls of the first metal layer, the second metal layer is disposed between the transparent conductive pattern and the first metal layer, and the transparent conductive pattern is disposed between the electrochromic layer and the second metal layer.

In one embodiment of the present invention, the above-mentioned insulating layer has multiple openings, and multiple transparent conductive patterns of multiple electrodes fill the multiple openings and are electrically connected to multiple mesh conductive patterns of multiple electrodes.

In one embodiment of the present invention, each of the above-mentioned openings overlaps with multiple network wires and multiple meshes of a corresponding electrode.

In one embodiment of the present invention, each of the above-mentioned openings overlaps with a plurality of meshes of a corresponding electrode, and the insulating layer covers a plurality of meshes of the electrode.

In one embodiment of the present invention, the above-mentioned multiple mesh cables include a first segment, a second segment, a third segment and a fourth segment that define a mesh and are connected in series with each other. The first segment, the second segment, the third segment and the fourth segment have a first angle, a second angle, a third angle and a fourth angle with the reference line respectively. The first angle, the second angle, the third angle and the fourth angle are θ1, θ2, θ3 and θ4 respectively, and θ4>θ3>θ2>θ1.

In an embodiment of the present invention, the above-mentioned multiple traces respectively have multiple signal input terminals, the multiple signal input terminals are arranged near the edge of the first substrate, the first direction intersects with the edge of the first substrate, the multiple electrodes include a first electrode and a second electrode arranged in the first direction, the first electrode is farther from the edge of the first substrate than the second electrode, the multiple traces include a first trace and a second trace electrically connected to the first electrode and the second electrode, the second direction intersects with the first direction, the first trace and the second trace have a first line width and a second line width in the second direction, and the first line width is greater than the second line width.

In an embodiment of the present invention, the above-mentioned multiple traces respectively have multiple signal input terminals, the multiple signal input terminals are arranged beside the edge of the first substrate, the first direction intersects with the edge of the first substrate, the multiple electrodes include a first electrode and a second electrode arranged in the first direction, the first electrode is farther from the edge of the first substrate than the second electrode, the multiple traces include a first trace and a second trace electrically connected to the first electrode and the second electrode respectively, and the voltage input to the signal input terminal of the first trace is greater than the voltage input to the signal input terminal of the second trace.

In one embodiment of the present invention, the first substrate has a first surface and a second surface facing each other, the first surface faces the electrochromic layer, and the second surface faces away from the electrochromic layer. The first substrate has a plurality of through holes penetrating the first surface and the second surface. The electronic device further includes a plurality of conductive materials respectively filling the plurality of through holes, the plurality of conductive materials are respectively electrically connected to a plurality of electrodes, and a plurality of traces are arranged on the second surface of the first substrate and are respectively electrically connected to the plurality of conductive materials.

10, 10A, 10B, 10C: dimming panel

20: Transparent display panel

100: First substrate

110: First base

110a, 210a: edge

110s1: First surface

110s2: Second surface

110h: Through hole

120, 220: Electrode

120-1, 220-1: first electrode

120-2, 220-2: Second electrode

120-3, 220-3: Third electrode

120-4, 220-4: Fourth electrode

122, 222: Mesh conductive pattern

122a, 222a: Network cable

122a-1, 222a-1: first paragraph

122a-2, 222a-2: Second paragraph

122a-3, 222a-3: The third paragraph

122a-4, 222a-4: The fourth paragraph

122b, 222b: mesh

124, 224: Transparent conductive pattern

130, 130B, 130C, 230: routing

130a, 230a: signal input terminal

130-1, 230-1: First route

130-2, 230-2: Second route

130-3, 230-3: The third route

130-4, 230-4: The fourth route

140, 140A, 240, 240A: Insulation layer

142, 142A, 242, 242A: Opening

200: Second substrate

210: Second base

300:Electrochromic layer

400: Frame glue

500: Conductive material

A1, B1: First line width

A2, B2: Second line width

A3, B3: Third line width

A4, B4: Fourth line width

B: Background

C: Dimming zone

c: Light control area

d1: first direction

d2: second direction

E: Electronic devices

L: Reference line

l: Line width

M1, M1’: first metal layer

M1a, M1c, M2c, M1a’, M1c’, M2c’: top surface

M1b, M1d, M2d, M1b’, M1d’, M2d’: side wall

M2, M2’: Second metal layer

P:Electrode group

P1: mesh arrangement cycle

R: Storage space

U: User

y: horizontal direction

z: vertical direction

I-I’, II-II’, III-III’, IV-IV’, V-V’, VI-VI’: hatching line

θ1: first angle

θ2: Second angle

θ3: The third angle

θ4: the fourth angle

Figure 1 is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present invention.

Figure 2 is a cross-sectional schematic diagram of a dimming panel according to an embodiment of the present invention.

Figure 3 is a schematic top view of the first substrate of the dimming panel of an embodiment of the present invention.

Figure 4 is a schematic top view of the second substrate of the dimming panel of an embodiment of the present invention.

Figure 5 is a schematic cross-sectional view of the first substrate of the dimming panel of an embodiment of the present invention.

Figure 6 is a schematic cross-sectional view of the second substrate of the dimming panel of an embodiment of the present invention.

Figure 7 is a cross-sectional and enlarged schematic diagram of the network cable and network of an embodiment of the present invention.

Figure 8 is a cross-sectional schematic diagram of a dimming panel in another embodiment of the present invention.

Figure 9 is a schematic top view of the first substrate of the dimming panel of another embodiment of the present invention.

Figure 10 is a schematic top view of the second substrate of the dimming panel of another embodiment of the present invention.

Figure 11 is a cross-sectional schematic diagram of a dimming panel in another embodiment of the present invention.

Figure 12 is a top view schematic diagram of the first substrate, conductive material and wiring of the dimming panel of another embodiment of the present invention.

Figure 13 is a cross-sectional schematic diagram of a dimming panel in another embodiment of the present invention.

FIG14 is a top view schematic diagram of the first substrate, conductive material and wiring of the dimming panel of another embodiment of the present invention.

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and description to represent the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, "electrical connection" or "coupling" may mean the presence of other elements between two elements.

As used herein, "approximately", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of a specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "approximately", "approximately", or "substantially" as used herein can select a more acceptable deviation range or standard deviation based on the optical properties, etching properties, or other properties, and can apply to all properties without using one standard deviation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly so defined herein.

FIG1 is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present invention. Referring to FIG1 , the electronic device E includes a transparent display panel 20 and a dimming panel 10 disposed behind the transparent display panel 20. The dimming panel 10 can be switched to a transparent mode, a light-shielding mode, or a partially transparent and partially light-shielding mode. When the dimming panel 10 is switched to the transparent mode, the user U can not only view the display screen of the transparent display panel 20, but also view the background B behind the transparent display panel 20. When the dimming panel 10 is switched to the light-shielding mode, the user U can view the display screen with a higher contrast more clearly, but cannot view the background B behind. When the dimming panel 10 switches to the partially transparent and partially shading mode, the dimming area of the dimming panel 10 includes a first light control area (not marked) and a second light control area (not marked), the first light control area is light-transmissive, and the second light control area is light-shielding. The display area (not marked) of the transparent display panel 20 includes a first display area (not marked) and a second display area (not marked) respectively overlapping the first light control area and the second light control area. The electronic device E can provide a transparent display effect at the first display area, and can provide an opaque but higher contrast display screen at the second display area.

The dimming panel 10 includes a first substrate 100, a second substrate 200, an electrochromic layer 300 and a frame 400. The frame 400 connects the first substrate 100 and the second substrate 200, and defines a receiving space R together with the first substrate 100 and the second substrate 200, and the electrochromic layer 300 is encapsulated in the receiving space R. By controlling the voltage of at least one of the electrodes (not shown) of the first substrate 100 and the second substrate 200, the dimming panel 10 can be switched to a transparent mode, a shading mode or a partially transparent and partially shading mode. The following is an example of the structure and operation of the dimming panel 10 with other diagrams.

FIG2 is a cross-sectional schematic diagram of a dimming panel according to an embodiment of the present invention. FIG3 is a top view schematic diagram of a first substrate of a dimming panel according to an embodiment of the present invention. FIG4 is a top view schematic diagram of a second substrate of a dimming panel according to an embodiment of the present invention. FIG2 corresponds to the section line I-I' of FIG3 and the section line II-II' of FIG4. FIG5 is a cross-sectional schematic diagram of a first substrate of a dimming panel according to an embodiment of the present invention. FIG5 corresponds to the section line III-III' of FIG3. FIG6 is a cross-sectional schematic diagram of a second substrate of a dimming panel according to an embodiment of the present invention. FIG6 corresponds to the section line IV-IV' of FIG4.

Referring to FIG. 2 and FIG. 3 , the first substrate 100 of the dimming panel 10 includes a first base 110 and a plurality of electrodes 120 . The first base 110 is light-transmissive. The plurality of electrodes 120 are disposed on the first base 110 and are separated from each other in structure. Each electrode 120 includes a mesh conductive pattern 122 and a transparent conductive pattern 124 , wherein the mesh conductive pattern 122 has a plurality of mesh lines 122a and a plurality of meshes 122b defined by the plurality of mesh lines 122a , and the transparent conductive pattern 124 covers the plurality of mesh lines 122a and the plurality of meshes 122b and is electrically connected to the mesh conductive pattern 122 .

In one embodiment, each mesh line 122a of the mesh conductive pattern 122 may include a first metal layer M1 and a second metal layer M2, the second metal layer M2 of the mesh line 122a covers the top surface M1a and the side wall M1b of the first metal layer M1 of the mesh line 122a, the second metal layer M2 of the mesh line 122a is disposed between the transparent conductive pattern 124 and the first metal layer M1 of the mesh line 122a, and the transparent conductive pattern 124 is disposed between the electrochromic layer 300 and the second metal layer M2 of the mesh line 122a.

For example, in one embodiment, the material of the transparent conductive pattern 124 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.

3 and 5 , the first substrate 100 further includes a plurality of traces 130 disposed on the first base 110 and electrically connected to the plurality of electrodes 120. In one embodiment, each trace 130 may include a first metal layer M1 and a second metal layer M2, and the second metal layer M2 of the trace 130 covers the top surface M1c and the sidewall M1d of the first metal layer M1 of the trace 130. In one embodiment, the first metal layer M1 of each trace 130 and the first metal layer M1 of the mesh line 122a of a corresponding electrode 120 belong to the same film layer and can be directly connected, and the second metal layer M2 of each trace 130 and the second metal layer M2 of the mesh line 122a of a corresponding electrode 120 belong to the same film layer and can be directly connected, but the present invention is not limited to this.

2 , 3 and 5 , the first substrate 100 further includes an insulating layer 140 disposed on the first base 110 and covering at least a plurality of traces 130 . The insulating layer 140 can isolate the traces 130 from the electrochromic layer 300 to prevent the electrochromic layer 300 from damaging the traces 130 . In one embodiment, the insulating layer 140 covers the top surface M2c and the side wall M2d of the second metal layer M2 of the trace 130, the second metal layer M2 of the trace 130 is disposed between the insulating layer 140 and the first metal layer M1 of the trace 130, and the insulating layer 140 is located between the electrochromic layer 300 and the second metal layer M2 of the trace 130.

Please refer to Figures 2, 3 and 5. In one embodiment, the insulating layer 140 has a plurality of openings 142, and the plurality of transparent conductive patterns 124 of the plurality of electrodes 120 are filled into the plurality of openings 142 of the insulating layer 140 and electrically connected to the plurality of mesh conductive patterns 122 of the plurality of electrodes 120. For example, in one embodiment, each opening 142 of the insulating layer 140 overlaps with the plurality of mesh lines 122a and the plurality of meshes 122b of a corresponding electrode 120, and each transparent conductive pattern 124 is filled into an opening 142 of the corresponding insulating layer 140 and electrically connected to a corresponding mesh conductive pattern 122.

Please refer to FIG. 3 and FIG. 5. In one embodiment, a portion of the insulating layer 140 may be disposed between the transparent conductive pattern 124 of the electrode 120 and the second metal layer M2 of the wiring 130. In one embodiment, the outer edge of each transparent conductive pattern 124 may selectively cover a portion of the insulating layer 140 located on the wiring 130, but does not completely cover the entire wiring 130. However, the present invention is not limited thereto. In other embodiments not shown, each transparent conductive pattern 124 may also completely cover a corresponding wiring 130, and multiple transparent conductive patterns 124 covering different wirings 130 are disconnected from each other; for example, multiple transparent conductive patterns 124 covering different wirings 130 may be at least 5μm to 15μm apart.

Please refer to FIG. 3. In one embodiment, the electrode 120 that is farther from the edge 110a (i.e., the side where the signal input terminal 130a is located) needs to be electrically connected to a longer trace 130. The longer trace 130 has a larger resistance, and the electrode 120 electrically connected to the longer trace 130 faces a higher resistance and capacitance loss. In order to make the electrochromic layer 300 on the electrode 120 that is closer to the edge 110a feel the same or similar voltage, the voltage input to the signal input terminal 130a can be adjusted.

For example, in one embodiment, the plurality of traces 130 respectively have a plurality of signal input terminals 130a, the plurality of signal input terminals 130a are disposed beside an edge 110a of the first substrate 110, and the first direction d1 intersects with the edge 110a of the first substrate 110, and the plurality of electrodes 120 include a first electrode 120-1, a second electrode 120-2, and a second electrode 120-3 arranged in the first direction d1. , a third electrode 120-3 and a fourth electrode 120-4, the first electrode 120-1 is farther from the edge 110a of the first substrate 110 than the second electrode 120-2, the second electrode 120-2 is farther from the edge 110a of the first substrate 110 than the third electrode 120-3, and the third electrode 120-3 is farther from the edge 110a of the first substrate 110 than the fourth electrode 120-4. The plurality of traces 130 include a first trace 130-1, a second trace 130-2, a third trace 130-3 and a fourth trace 130-4 which are electrically connected to the first electrode 120-1, the second electrode 120-2, the third electrode 120-3 and the fourth electrode 120-4 respectively. The voltage of the signal input terminal 130a input to the first trace 130-1 may be greater than that of the signal input terminal 130a input to the second trace 130-1. The voltage of the signal input terminal 130a of the routing 130-2 may be greater than the voltage of the signal input terminal 130a of the third routing 130-3, and the voltage of the signal input terminal 130a of the third routing 130-3 may be greater than the voltage of the signal input terminal 130a of the fourth routing 130-4. In one embodiment, the voltage of the signal input terminal 130a input to the first wiring 130-1, the voltage of the signal input terminal 130a input to the second wiring 130-2, the voltage of the signal input terminal 130a input to the third wiring 130-3, and the voltage of the signal input terminal 130a input to the fourth wiring 130-4 are, for example, 3.5V, 3V, 2.5V, and 1.9V, respectively, but the present invention is not limited thereto.

In addition, in one embodiment, in order to reduce the resistance difference between the wirings 130 of different lengths and to reduce the difference in resistance and capacitance losses faced by the electrodes 120 that are different in distance from the edge 110a, the wirings 130 may have different line widths. For example, in one embodiment, the wirings 130 each have a plurality of signal input terminals 130a, and the plurality of signal input terminals 130a are disposed beside an edge 110a of the first substrate 110, and the first direction d1 intersects with the edge 110a of the first substrate 110. The plurality of electrodes 120 include first electrodes 130a arranged in the first direction d1. 20-1, a second electrode 120- 2, a third electrode 120-3 and a fourth electrode 120-4, the first electrode 120-1 is farther from the edge 110a of the first substrate 110 than the second electrode 120-2, the second electrode 120-2 is farther from the edge 110a of the first substrate 110 than the third electrode 120-3, and the third electrode 120- The fourth electrode 120-4 is farther away from the edge 110a of the first substrate 110. The plurality of traces 130 include a first trace 130-1, a second trace 130-2, a third trace 130-3 and a fourth trace 130-4 which are electrically connected to the first electrode 120-1, the second electrode 120-2, the third electrode 120-3 and the fourth electrode 120-4, respectively. The second direction d2 is interlaced with the first direction d1. The first trace 130-1, the second trace 130-2, the third trace 130-3 and the fourth trace 130-4 have a first line width A1, a second line width A2, a third line width A3 and a fourth line width A4 in the second direction d2, respectively, and A1>A2>A3>A4. However, the present invention is not limited to this. In other embodiments not shown, A1=A2=A3=A4 may also be true.

Please refer to Figures 2 to 6. In one embodiment, the second substrate 200 of the dimming panel 10 may selectively have the same or similar structure as the first substrate 100. The structure of the second substrate 200 is illustrated as follows.

2 and 4 , the second substrate 200 of the dimming panel 10 includes a second substrate 210 and a plurality of electrodes 220. The second substrate 210 of the second substrate 200 is disposed opposite to the first substrate 110 of the first substrate 100. The electrochromic layer 300 is disposed between the first substrate 110 and the second substrate 210. The second substrate 210 is light-transmissive. The plurality of electrodes 220 are disposed on the second substrate 210 and are separated from each other in structure. Each electrode 220 includes a mesh conductive pattern 222 and a transparent conductive pattern 224, wherein the mesh conductive pattern 222 has a plurality of mesh lines 222a and a plurality of meshes 222b defined by the plurality of mesh lines 222a, and the transparent conductive pattern 224 covers the plurality of mesh lines 222a and the plurality of meshes 222b and is electrically connected to the mesh conductive pattern 222.

In one embodiment, each mesh line 222a of the mesh conductive pattern 222 may include a first metal layer M1' and a second metal layer M2', the second metal layer M2' of the mesh line 222a covers the top surface M1a' and the side wall M1b' of the first metal layer M1' of the mesh line 222a, the second metal layer M2' of the mesh line 222a is disposed between the transparent conductive pattern 224 and the first metal layer M1' of the mesh line 222a, and the transparent conductive pattern 224 is disposed between the electrochromic layer 300 and the second metal layer M2' of the mesh line 222a.

For example, in one embodiment, the material of the transparent conductive pattern 224 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.

4 and 6 , the second substrate 200 further includes a plurality of traces 230 disposed on the second base 210 and electrically connected to the plurality of electrodes 220. In one embodiment, each trace 230 may include a first metal layer M1′ and a second metal layer M2′, and the second metal layer M2′ of the trace 230 covers the top surface M1c′ and the sidewall M1d′ of the first metal layer M1′ of the trace 230. In one embodiment, the first metal layer M1' of each trace 230 and the first metal layer M1' of the mesh line 222a of a corresponding electrode 220 belong to the same film layer and can be directly connected, and the second metal layer M2' of each trace 230 and the second metal layer M2' of the mesh line 222a of a corresponding electrode 220 belong to the same film layer and can be directly connected, but the present invention is not limited to this.

2, 4 and 6, the second substrate 200 further includes an insulating layer 240 disposed on the second base 210 and covering at least a plurality of traces 230. The insulating layer 240 can isolate the traces 230 from the electrochromic layer 300 to prevent the electrochromic layer 300 from damaging the traces 230. In one embodiment, the insulating layer 240 covers the top surface M2c' and the side wall M2d' of the second metal layer M2' of the trace 230, the second metal layer M2' of the trace 230 is disposed between the insulating layer 240 and the first metal layer M1' of the trace 230, and the insulating layer 240 is located between the electrochromic layer 300 and the second metal layer M2' of the trace 230.

Please refer to FIG. 4 and FIG. 6. In one embodiment, the insulating layer 240 has a plurality of openings 242. The plurality of transparent conductive patterns 224 of the plurality of electrodes 220 are filled into the plurality of openings 242 of the insulating layer 240 and are electrically connected to the plurality of mesh conductive patterns 222 of the plurality of electrodes 220. For example, in one embodiment, each opening 242 of the insulating layer 240 overlaps with the plurality of mesh lines 222a and the plurality of meshes 222b of a corresponding electrode 220. Each transparent conductive pattern 224 is filled into an opening 242 of the corresponding insulating layer 240 and is electrically connected to a corresponding mesh conductive pattern 222.

In one embodiment, part of the insulating layer 240 may be disposed between the transparent conductive pattern 224 of the electrode 220 and the second metal layer M2' of the trace 230. In one embodiment, the outer edge of each transparent conductive pattern 224 may selectively cover part of the insulating layer 240 located on the trace 230, but does not completely cover the entire trace 230. However, the present invention is not limited thereto. In other embodiments not shown, each transparent conductive pattern 224 may also completely cover a corresponding trace 230, and multiple transparent conductive patterns 224 covering different traces 230 are disconnected from each other; for example, multiple transparent conductive patterns 224 covering different traces 230 are at least 5μm to 15μm apart.

Referring to FIG. 4 , in one embodiment, the plurality of traces 230 respectively have a plurality of signal input terminals 230a, the plurality of signal input terminals 230a are disposed beside an edge 210a of the second substrate 210, and intersect with the edge 210a of the second substrate 210 in a first direction d1. The plurality of electrodes 220 include a first electrode 220-1, a second electrode 220-2, a third electrode 220-3, and a fourth electrode 220-4 arranged in the first direction d1, the first electrode 220-1 being farther from the second substrate 210 than the second electrode 220-2. 10, the second electrode 220-2 is farther from the edge 210a of the second substrate 210 than the third electrode 220-3, the third electrode 220-3 is farther from the edge 210a of the second substrate 210 than the fourth electrode 220-4, and the plurality of traces 230 include a first trace 230-1, a second trace 230-2, a third trace 230-3 and a fourth trace 230-4 which are electrically connected to the first electrode 220-1, the second electrode 220-2, the third electrode 220-3 and the fourth electrode 220-4 respectively.

The electrode 220 that is farther from the edge 210a (i.e., the side where the signal input terminal 230a is located) needs to be electrically connected to a longer trace 230. A longer trace 230 has a larger resistance. In one embodiment, in order to reduce the resistance difference between traces 230 of different lengths and to reduce the difference in resistance and capacitance losses faced by electrodes 220 that are closer to the edge 210a, multiple traces 230 can have different line widths. For example, in one embodiment, the second direction d2 is interlaced with the first direction d1, and the first routing line 230-1, the second routing line 230-2, the third routing line 230-3, and the fourth routing line 230-4 have a first line width B1, a second line width B2, a third line width B3, and a fourth line width B4 in the second direction d2, respectively, and B1>B2>B3>B4. However, the present invention is not limited to this, and in other embodiments not shown, B1=B2=B3=B4 may also be.

Referring to FIG. 2, FIG. 3 and FIG. 4, the first substrate 100 and the second substrate 200 can be assembled to form a dimming panel 10. In one embodiment, after the first substrate 100 and the second substrate 200 are assembled, the plurality of electrodes 120 of the first substrate 100 are overlapped with the plurality of electrodes 220 of the second substrate 200. Each electrode 120 of the first substrate 100 and an electrode 220 of the second substrate 200 overlapped therewith form an electrode group P. The plurality of electrode groups P respectively occupy the plurality of light control areas c of the dimming panel 10. The plurality of light control areas c constitute a dimming area C of the dimming panel 10. By controlling the voltage difference between the two electrodes 120 and 220 of each electrode group P, the partial electrochromic layer 300 in the light control area c can be controlled to transmit light or absorb light, thereby making the light control area c transparent or light-shielding. If all the light control areas c of the dimming panel 10 are transparent, the electronic device E is in the aforementioned transparent mode. If all the light control areas c of the dimming panel 10 are light-shielding, the electronic device E is in the aforementioned light-shielding mode. If part of the light control areas c of the dimming panel 10 are light-shielding and the other part of the light control areas c are transparent, the electronic device E is in the aforementioned partial transparent and partial light-shielding mode. In Figures 3 and 4, the dimming panel 10 includes 9 light control areas c as an example. However, the present invention is not limited to this, and the number and arrangement of the light control areas c of the dimming panel 10 can be designed in other ways according to actual needs.

It is worth noting that the dimming panel 10 includes multiple electrodes 120/220 disposed in multiple light control areas c. The multiple light control areas c are in a transparent state or a light absorption state and are controlled by multiple electrodes 120/220 respectively rather than by the same large electrode. Each electrode 120/220 is composed of a mesh conductive pattern 122/222 and a transparent conductive pattern 124/224 and has a low resistance. In this way, when the light control area c of the dimming panel 10 is switched from a light shielding state to a light absorption state, the light control area c is not prone to the problem of not being able to turn black in the entire area due to the resistance of the electrochromic layer 300 becoming lower than the resistance of the corresponding electrode 120/220.

FIG7 is a cross-sectional and enlarged schematic diagram of a network cable and mesh of an embodiment of the present invention. Referring to FIG3, FIG4 and FIG7, in an embodiment, the network cable 122a/222a includes a first section 122a-1/222a-1, a second section 122a-2/222a-2, a third section 122a-3/222a-3 and a fourth section 122a-4/222a-4 that define a mesh 122b/222b and are connected in series with each other, and the first section 122a-1/222a-1, the second section 122a-2/222a-2, the third section 122a-3/222a-3 and the fourth section 122a-4/222a-4 have a first angle θ1, a second angle θ2, a third angle θ3 and a fourth angle θ4 with the reference line L, and θ4>θ3>θ2>θ1. This can reduce the intensity of diffracted light in the horizontal and vertical directions, thereby improving the visual effect.

For example, in one embodiment, a mesh line 122a/222a defining a mesh 122b/222b may selectively enclose a hexagon, and the reference line L may be a straight line passing through two opposite vertices of the hexagon, but the present invention is not limited thereto. In one embodiment, θ4=81.7 ° ±2 ° , θ3=51.6 ° ±2 ° , θ2=38.3 ° ±2 ° , θ1=8.3 ° ±2 ° , but the present invention is not limited thereto.

In one embodiment, the multiple meshes 122b/222b of the dimming panel 10 have a mesh arrangement period P1, and the multiple pixels (not shown) of the transparent display panel 20 have a pixel arrangement period (not shown). The mesh arrangement period P1 may be greater than twice the pixel arrangement period to avoid interference between the dimming panel 10 and the transparent display panel 20 and the appearance of obvious Murray stripes. In one embodiment, the mesh lines 122a/222a defining a mesh 122b/222b may selectively enclose a hexadecagon, and the mesh arrangement period P1 may be substantially equal to the distance between two opposite vertices of the hexadecagon, but the present invention is not limited thereto.

In one embodiment, the area coverage of the mesh cable 122a/222a on the first substrate 110/the second substrate 210 may be less than 4%. In one embodiment, the line width l of the mesh cable 122a/222a may change with the mesh arrangement period P1. Specifically, the larger the mesh arrangement period P1, the wider the line width l of the mesh cable 122a/222a may be.

It must be noted here that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the previous embodiments, and the following embodiments will not be repeated.

FIG8 is a cross-sectional schematic diagram of a dimming panel of another embodiment of the present invention. FIG9 is a top view schematic diagram of a first substrate of a dimming panel of another embodiment of the present invention. FIG10 is a top view schematic diagram of a second substrate of a dimming panel of another embodiment of the present invention. FIG8 corresponds to the section line V-V' of FIG9 and the section line VI-VI' of FIG10.

Referring to FIG. 8 , FIG. 9 and FIG. 10 , the dimming panel 10A of the present embodiment is similar to the dimming panel 10 of the aforementioned embodiment, and the difference between the two is that the insulating layer 140A of the first substrate 100 of the dimming panel 10 of the present embodiment is different from the insulating layer 140 of the first substrate 100 of the dimming panel 10 of the aforementioned embodiment, and the insulating layer 240A of the second substrate 200 of the dimming panel 10A of the present embodiment is different from the insulating layer 240 of the second substrate 200 of the dimming panel 10A of the aforementioned embodiment.

Please refer to Figures 8 and 9. Specifically, in this embodiment, each opening 142A of the insulating layer 140A of the first substrate 100 overlaps with the mesh 122a of a corresponding electrode 120, and the insulating layer 140A of the first substrate 100 covers a plurality of meshes 122b of the electrode 120. In short, in this embodiment, except for the opening 142A where the mesh 122a is located, the insulating layer 140A almost covers the entire surface of the first base 110.

Please refer to FIG. 8 and FIG. 10. Similarly, in this embodiment, each opening 242A of the insulating layer 240A of the second substrate 200 overlaps the mesh 222a of a corresponding electrode 220, and the insulating layer 240A of the second substrate 200 covers the multiple meshes 222b of the electrode 220. In short, in this embodiment, except for the opening 142A where the mesh 222a is located, the insulating layer 240A almost covers the entire surface of the second base 210.

Figure 11 is a cross-sectional schematic diagram of a dimming panel in another embodiment of the present invention. Figure 12 is a top view schematic diagram of the first substrate, conductive material and wiring of a dimming panel in another embodiment of the present invention.

11 and 12 , the dimming panel 10B of this embodiment is similar to the dimming panel 10 of the aforementioned embodiment, and the difference between the two lies in: the positions of the traces 130 , 130B and the ways in which the traces 130 , 130B are electrically connected to the electrode 120 are different. Specifically, in this embodiment, the first substrate 110 has a first surface 110s1 and a second surface 110s2 opposite to each other, the first surface 110s1 faces the electrochromic layer 300, and the second surface 110s2 faces away from the electrochromic layer 300. The first substrate 110 has a plurality of through holes 110h penetrating the first surface 110s1 and the second surface 110s2. A plurality of conductive materials 500 are respectively filled into the plurality of through holes 110h of the first substrate 110. The plurality of conductive materials 500 are respectively electrically connected to the plurality of electrodes 120. A plurality of traces 130B are disposed on the second surface 110s2 of the first substrate 110 and are respectively electrically connected to the plurality of conductive materials 500. The plurality of traces 130C are respectively electrically connected to the plurality of electrodes 120 through the plurality of conductive materials 500.

In one embodiment, the conductive material 500 is, for example, silver glue, but the present invention is not limited thereto. In one embodiment, the plurality of traces 130C are, for example, modular wires, the first substrate 100 and the second substrate 200 are stacked in the vertical direction z, and the plurality of traces 130C electrically connected to the plurality of electrodes 120 in the same row can also be stacked in the vertical direction z, but the present invention is not limited thereto.

FIG13 is a cross-sectional schematic diagram of a dimming panel in another embodiment of the present invention. FIG14 is a top view schematic diagram of the first substrate, conductive material and wiring of a dimming panel in another embodiment of the present invention.

Please refer to FIG. 13 and FIG. 14. The dimming panel 10C of this embodiment is similar to the dimming panel 10B of the aforementioned embodiment. The difference between the two is that the formation method of the wiring 130C of the dimming panel 10C is different from the formation method of the wiring 130B of the dimming panel 10C, and the setting method of the wiring 130B of the dimming panel 10C is also different from the setting method of the wiring 130B of the dimming panel 10C. Specifically, in this embodiment, the wiring 130C of the dimming panel 10C is formed on the second surface 110s2 of the first substrate 110 using a lithography process. In addition, in this embodiment, a plurality of wirings 130C can be arranged on the same plane (i.e., the second surface 110s2), and the plurality of wirings 130C are spaced apart from each other in a horizontal direction y parallel to the first substrate 110.

10: Dimming panel

100: First substrate

110: First base

120, 220: Electrode

122, 222: Mesh conductive pattern

122a, 222a: Network cable

122b, 222b: mesh

124, 224: Transparent conductive pattern

200: Second substrate

210: Second base

300:Electrochromic layer

M1, M1’: first metal layer

M1a, M1a’: top surface

M1b, M1b’: side wall

M2, M2’: Second metal layer

P:Electrode group

I-I’, II-II’: section line

Claims (10)

An electronic device includes: a first substrate; a plurality of electrodes disposed on the first substrate, wherein each of the electrodes includes: a mesh conductive pattern having a plurality of meshes and a plurality of meshes defined by the meshes; and a transparent conductive pattern covering the meshes and the meshes and electrically connected to the mesh conductive pattern; a plurality of traces disposed on the first substrate and electrically connected to the electrodes respectively; an insulating layer disposed on the first substrate and at least covering the traces; a second substrate disposed on the first substrate; Opposite; and an electrochromic layer disposed between the first substrate and the second substrate, wherein the mesh lines include a first segment, a second segment, a third segment and a fourth segment that define the mesh and are connected in series with each other, the first segment, the second segment, the third segment and the fourth segment have a first angle, a second angle, a third angle and a fourth angle with a reference line respectively, the first angle, the second angle, the third angle and the fourth angle are θ1, θ2, θ3 and θ4 respectively, and θ4>θ3>θ2>θ1. An electronic device as described in claim 1, wherein each of the traces includes a first metal layer and a second metal layer, the second metal layer covers a top surface and a side wall of the first metal layer, the second metal layer is disposed between the insulating layer and the first metal layer, the insulating layer is disposed between the electrochromic layer and the second metal layer, and the insulating layer covers a top surface and a side wall of the second metal layer. An electronic device as described in claim 2, wherein a portion of the insulating layer is disposed between the transparent conductive pattern of the electrode and the second metal layer of the wiring. An electronic device as described in claim 1, wherein each of the mesh lines of the mesh conductive pattern includes a first metal layer and a second metal layer, the second metal layer covers a top surface and a side wall of the first metal layer, the second metal layer is disposed between the transparent conductive pattern and the first metal layer, and the transparent conductive pattern is disposed between the electrochromic layer and the second metal layer. An electronic device as described in claim 1, wherein the insulating layer has a plurality of openings, and the plurality of transparent conductive patterns of the electrodes fill the openings and are electrically connected to the plurality of mesh conductive patterns of the electrodes. An electronic device as described in claim 5, wherein each of the openings overlaps the network wires and the network meshes of a corresponding electrode. An electronic device as described in claim 5, wherein each of the openings overlaps the meshes of a corresponding electrode, and the insulating layer covers the meshes of the electrode. An electronic device as described in claim 1, wherein the traces have a plurality of signal input terminals respectively, the signal input terminals are arranged beside an edge of the first substrate, a first direction intersects with the edge of the first substrate, the electrodes include a first electrode and a second electrode arranged in the first direction, the first electrode is farther from the edge of the first substrate than the second electrode, the traces include a first trace and a second trace electrically connected to the first electrode and the second electrode respectively, a second direction intersects with the first direction, the first trace and the second trace have a first line width and a second line width respectively in a second direction, and the first line width is greater than the second line width. An electronic device as described in claim 1, wherein the traces have a plurality of signal input terminals respectively, the signal input terminals are arranged beside an edge of the first substrate, a first direction intersects with the edge of the first substrate, the electrodes include a first electrode and a second electrode arranged in the first direction, the first electrode is farther from the edge of the first substrate than the second electrode, the traces include a first trace and a second trace electrically connected to the first electrode and the second electrode respectively, a voltage input to one of the signal input terminals of the first trace is greater than a voltage input to one of the signal input terminals of the second trace. An electronic device as described in claim 1, wherein the first substrate has a first surface and a second surface relative to each other, the first surface faces the electrochromic layer, and the second surface faces away from the electrochromic layer, the first substrate has a plurality of through holes penetrating the first surface and the second surface, the electronic device further includes a plurality of conductors respectively filled in the through holes, the conductors are respectively electrically connected to the electrodes, and the traces are arranged on the second surface of the first substrate and are respectively electrically connected to the conductors.