TWI773971B - Integrated circuit chip, package substrate and electronic assembly - Google Patents

Abstract

An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along the side edge of the active surface. The two pairs of chip pads of the four pairs of chip pads are a first transmitting differential pair chip pad and a first receiving differential pair chip pad respectively, wherein the positions of the two pairs of chip pads are not adjacent to each other and are not in the same row. The other two pairs of chip pads of the four pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively, wherein the positions of the other two pairs of chip pads are not adjacent to each other and are not in the same row. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.

Description

Integrated circuit chips, package substrates and electronic assemblies

The present invention relates to a pad arrangement, and more particularly, to an integrated circuit chip and a package substrate having the pad arrangement, and an electronic assembly having the integrated circuit chip and the package substrate.

The USB interface is widely used in the interconnection of computing and mobile devices. As computing and mobile devices move toward smaller, thinner, and lighter weight, USB Type-C has grown in interface connectivity systems. Additionally, USB Type-C meets both usability and durability requirements. It can support the existing USB2.0, USB3.1 and USB power delivery specifications and has multi-channel and reversible functions. Reversible here means that users do not need to consider the directionality when plugging and unplugging the USB Type-C interface, which is more convenient. Due to the reversible function, two pairs of TX and RX signals are required in USB TYPE-C Serdes (serializer/deserializer), such as USB3.1 Gen1 (5Gbps) and Gen2 (10Gbps) specifications. Two pairs of TX and RX signals, but only one pair of TX and RX is connected to the transmit signal. Although the paired device may only have a pair of TX and RX, it must be connected to the host IC (host integrated circuit) through a pair of host-side TX and RX for signal transmission. down port) IC (integrated circuit) design must still include a pinout with two pairs of TX and RX.

The present invention provides an integrated circuit chip, which is used for reducing the crosstalk generated by differential transmission during signal transmission.

The present invention provides a package substrate for reducing crosstalk generated by differential transmission of signals.

The present invention provides an electronic assembly for reducing crosstalk generated by differential transmission during signal transmission.

An integrated circuit chip of an embodiment of the present invention has an active surface and a first chip pad arrangement on the active surface. The first wafer pad arrangement includes a first pair of wafer pads, a second pair of wafer pads, a third pair of wafer pads, and a fourth pair of wafer pads. The first pair of chip pads and the second pair of chip pads are sequentially arranged in a first row along a side edge of the active surface. The third pair of chip pads and the fourth pair of chip pads are sequentially arranged in a second row along the side edge of the active surface. The first pair of wafer pads are located between the side edge of the active surface and the third wafer pad. The second pair of wafer pads is located between the side edge of the active surface and the fourth wafer pad. The first pair of wafer pads is one of a first transfer differential pair wafer pad and a first receiver differential pair wafer pad, and the fourth pair of wafer pads is a first transfer differential pair wafer pad and a first receiver differential pair the other of the wafer pads. The second pair of wafer pads is one of a second transfer differential pair wafer pad and a second receiver differential pair wafer pad, and the third pair of wafer pads is a second transfer differential pair wafer pad and a second receiver differential pair the other of the wafer pads.

A package substrate according to an embodiment of the present invention is suitable for mounting an integrated circuit chip by flip-chip bonding, and has a chip area and a first substrate pad arranged in the chip area. The first substrate pad arrangement includes a first pair of substrate pads, a second pair of substrate pads, a third pair of substrate pads and a fourth pair of substrate pads. The first pair of substrate pads and the second pair of substrate pads are sequentially arranged in a first row along a side edge of the wafer area. The third pair of substrate pads and the fourth pair of substrate pads are sequentially arranged in a second row along the side edge of the wafer area. The first pair of substrate pads are located between the side edge of the wafer area and the third pair of substrate pads. The second pair of substrate pads is located between the side edge of the wafer area and the fourth pair of substrate pads. The first pair of substrate pads is one of a first transmitting differential pair substrate pad and a first receiving differential pair substrate pad, and the fourth pair of substrate pads is the first transmitting differential pair substrate pad and the first receiving differential pair The other one of the substrate pads. The second pair of substrate pads is one of a second transfer differential pair substrate pad and a second receiver differential pair substrate pad, and the third pair of substrate pads is the second transfer differential pair substrate pad and the second receiver differential pair The other one of the substrate pads.

An electronic assembly according to an embodiment of the present invention includes a package substrate and an integrated circuit chip. The package substrate has a chip area and a first substrate pad array located in the chip area. The first substrate pad arrangement includes a first pair of substrate pads, a second pair of substrate pads, a third pair of substrate pads and a fourth pair of substrate pads. The first pair of substrate pads and the second pair of substrate pads are sequentially arranged in a first row along a side edge of the wafer area. The third pair of substrate pads and the fourth pair of substrate pads are sequentially arranged in a second row along the side edge of the wafer area. The first pair of substrate pads are located between the side edge of the wafer area and the third pair of substrate pads. The second pair of substrate pads is located between the side edge of the wafer area and the fourth pair of substrate pads. The first pair of substrate pads is one of a first transmitting differential pair substrate pad and a first receiving differential pair substrate pad, and the fourth pair of substrate pads is the first transmitting differential pair substrate pad and the first receiving differential pair The other one of the substrate pads. The second pair of substrate pads is one of a second transfer differential pair substrate pad and a second receiver differential pair substrate pad, and the third pair of substrate pads is the second transfer differential pair substrate pad and the second receiver differential pair The other one of the substrate pads. The integrated circuit chip is mounted on the chip area of the package substrate by flip-chip bonding.

Based on the above, in the above-mentioned embodiments of the present invention, in terms of integrated circuit chips, by arranging two groups of transmit and receive (TX and RX) differential pair chip pads in two rows, and the same group of transmit and receive The differential pair wafer pads are arranged in non-adjacent, different row positions to reduce crosstalk between the same group of transmitting and receiving differential pair wafer pads. As far as the package substrate is concerned, by arranging the two groups of transmit and receive (TX and RX) differential pair substrate pads in two rows, and the same group of transmit and receive differential pair substrate pads are arranged in non-adjacent, different row positions , to reduce crosstalk between the same set of transmit and receive differential pair substrate pads.

Flip-Chip (FC) package (package) is an integrated circuit (IC) package that uses bumps (such as solder or copper pillar bumps) instead of bonding wires to realize IC chip and Connections to the package substrate. Flip chip packaging eliminates the high parasitic inductance caused by thin bond wires and can significantly improve package performance, especially for Serdes signals above 10 Gbps. Flip chip packaging can benefit designs for USB 3.1 Gen 2 (10 Gbps data rate) and even the upcoming USB 4 (20 Gbps data rate). The flip chip bumps can be arranged in an in-line or staggered array, depending on requirements.

For the USB TYPE-C port (port), based on the requirement that it can be flipped, at least 8 transmit/receive differential signals are required, including: the first transmit differential pair signal TX1 +/-, the first receive differential pair signal RX1 + /-, the second transmit differential pair signal TX2 +/- and the second receive differential pair signal RX2 +/-, and the above differential pair signal is a full-duplex transmission mode, that is, the transmission or reception of the signal can be simultaneously. In chip design, the pads corresponding to the transmit/receive differential pair signals are usually placed in the same row on the outer side of the pad array, so the fan-out of these signals on the package (that is, from the Wiring inside and outside the wafer area 202 ) does not need to be changed to other metal layers of the package substrate 200 for wiring. However, USB Type-C IC components, such as USB hubs, usually have multiple Type-C ports, so all the pads connecting the TX/RX differential pair signals are placed on the outer side of the pad array. The same row would make the size of the wafer too large and greatly increase the cost.

Since USB Type-C supports reversible function, each time an electrical connection is made, only the first transmit/receive differential pair of TX1/RX1 or the second transmit/receive differential pair of TX2/RX2 will be present. Carry out signal transmission. That is to say, when the first transmit/receive differential pair of TX1+/- and RX1+/- is turned on, the second transmit/receive differential pair of TX2+/- and RX2+/- is not turned on or remains in the original state, and vice versa Of course. Therefore, considering the above factors, the present invention proposes to use a multi-row pad array for the TX/RX differential pair signal in the USB Type-C port. Further, the pads electrically connected to the TX/RX differential pair signals are arranged in non-adjacent, different rows, and staggered from each other to prevent them from approaching each other and affecting the signal quality. It will be explained in detail below.

FIG. 1 shows an electronic assembly 50 of an embodiment of the present invention. In this embodiment, the electronic assembly 50 includes an integrated circuit chip 100 and a package substrate 200 , and the integrated circuit chip 100 is mounted on the package substrate 200 by flip-chip bonding. Specifically, the integrated circuit chip 100 has an active surface 102 and a plurality of die pads 104 located on the active surface 102 , and the package substrate 200 has a die area 202 and a plurality of die pads 104 located on the die area 202 . a substrate pad 204 . The integrated circuit chip 100 is mounted on the die area 202 of the package substrate 200 by flip-chip bonding (eg, through a plurality of conductive bumps 52 ), so that the die pads 104 of the integrated circuit chip 100 are electrically connected to the package substrate 200 , respectively. Substrate pads 204 . In addition, the electronic assembly 50 may also include a plurality of conductive media (eg, a plurality of solder balls 54 ) for mounting to next level components, such as a motherboard or the like.

2A-2D show the chip pad arrangement for the differential pair signal of the USB Type-C port. FIGS. 2A to 2D are the top-down top views viewed from the back of the integrated circuit chip 100 . Therefore, the chip pads 104 are represented by dotted lines, and the chip pads 104 are disposed on the active surface of the integrated circuit chip 100 . 102 on.

Please refer to FIG. 1 and FIG. 2A , the integrated circuit chip 100 includes a first chip pad array 110 , which is composed of some of the chip pads 104 , in the present embodiment, for example, an 8 chip supporting a USB Type-C port. A wafer pad 104 . The first wafer pad array 110 includes a first pair of wafer pads 111 , a second pair of wafer pads 112 , a third pair of wafer pads 113 and a fourth pair of wafer pads 114 . The first pair of chip pads 111 and the second pair of chip pads 112 are sequentially arranged in a first row R1 along one side edge of the active surface 102 . The third pair of die pads 113 and the fourth pair of die pads 114 are sequentially arranged in a second row R2 along the side edges of the active surface 102 . The first pair of wafer pads 111 are located between the side edge of the active surface 102 and the third wafer pad 104 . The second pair of wafer pads 112 are located between the side edges of the active surface 102 and the fourth wafer pad 104 . In addition, compared with the above-mentioned second row R2 , the first row R1 is farther away from the middle area of the integrated circuit chip 100 , that is, closer to the outer side of the integrated circuit chip 100 . In addition, in this embodiment, "row" is used to represent the positional relationship of the four pairs of wafer pads, but it is not used to limit the present invention. Positional relationship.

In addition, the first pair of wafer pads 111 includes a first transfer differential pair wafer pad 111 a ( TX1 + ) and another first transfer differential pair wafer pad 111 b ( TX1 − ). The second pair of wafer pads 112 includes a second receiving differential pair wafer pad 112a (RX2+) and another second receiving differential pair wafer pad 112b (RX2-). Therefore, the first row R1 is a plurality of differential pair wafer pads 112a (RX2+), 112b (RX2-), 111a (TX1+), 111b (TX1-) in sequence from left to right in the figure. The fourth pair of wafer pads 114 includes a first receiving differential pair wafer pad 114a (RX1+) and another first receiving differential pair wafer pad 114b (RX1-). The third pair of wafer pads 113 includes a second transfer differential pair wafer pad 113 a ( TX2 + ) and another second transfer differential pair wafer pad 113 b ( TX2 − ). Therefore, the second row R2 is a plurality of differential pair wafer pads 114a (RX1+), 114b (RX1-), 113a (TX2+), 113b (TX2-) in sequence from left to right in the figure. It should be noted that the above-mentioned order of the plurality of differential pair wafer pads from left to right is only a description manner, but is not limited to this description manner. In addition, the positions of the wafer pads 104 of the same pair of differential wafer pads 111-1142 can be interchanged with each other, for example: the first transfer differential pair wafer pad 111a (TX1+) and the first transfer differential pair wafer pad 111b ( TX1-), in this embodiment, it is only one of the description methods, and is not used to limit the present invention.

Because USB TYPE-C ports can be flipped, each port needs to be configured with at least 2 sets of transmit/receive differential pair signals, but when electrically connected, only one set of transmit/receive differential pair signals will be turned on. According to the above-mentioned embodiment, the first transmit differential pair wafer pads 111a and 111b (TX1+, TX1-) and the first receive differential pair wafer pads 114a and 114b (RX1+, RX1-) are arranged in non-adjacent, different rows to each other , but at approximately diagonal positions to ensure unnecessary coupling. Likewise, the second transmit differential pair wafer pads 113a and 113b (TX2+, TX2-) and the second receive differential pair wafer pads 112a and 112b (RX2+, RX2-) are arranged not adjacent to each other, in different rows, but instead at approximately diagonal positions to ensure unnecessary coupling. Further, from the perspective of mutually perpendicular XY coordinates, the projections of the first pair of wafer pads 111 and the fourth pair of wafer pads 114 on the X-axis or the Y-axis do not overlap each other, which means that the first pair of wafer pads 111 and the fourth pair of wafer pads 114 do not overlap each other. The projections of the four pairs of wafer pads 114 on a line parallel to the first row R1 or on another line perpendicular to the first row R1 do not overlap each other. The projections of the third pair of wafer pads 113 and the second pair of wafer pads 112 on the X-axis or the Y-axis do not overlap each other, which means that the third pair of wafer pads 113 and the second pair of wafer pads 112 are parallel to the first row R1 The projections on a line or another line perpendicular to the first row R1 do not overlap each other. The projections of the first pair of wafer pads 111 and the third pair of wafer pads 113 on the X-axis partially overlap or completely overlap each other; the projections of the fourth pair of wafer pads 114 and the second pair of wafer pads 112 on the X-axis partly overlap each other or completely overlapping, that is, the projections of the first pair of wafer pads 111 and the third pair of wafer pads 113 on a line parallel to the first row R1 partially overlap or completely overlap each other, and the fourth pair of wafer pads 114 and the second pair of wafer pads 114 and the second pair The projections of the wafer pads 112 on the aforementioned lines partially or completely overlap each other. The projections of the first pair of wafer pads 111 and the second pair of wafer pads 112 on the Y-axis partially overlap or completely overlap each other. The projections of the third pair of wafer pads 113 and the fourth pair of wafer pads 114 on the Y-axis partially overlap or completely overlap with each other, which means that the first pair of wafer pads 111 and the second pair of wafer pads 112 are perpendicular to the first row R1. The projections on the straight line partially overlap or completely overlap each other, and the projections of the third pair of wafer pads 113 and the fourth pair of wafer pads 114 on the aforementioned straight line partially overlap or completely overlap each other. In addition, the above-mentioned differential pair pads 111 to 114 are compatible with USB 4 or below.

Please refer to FIG. 2B , compared with the embodiment of FIG. 2A , in this embodiment, the positions of the first pair of chip pads 111 and the fourth pair of chip pads 114 in FIG. 2A are exchanged, and the original second pair of chip pads in FIG. 2A The positions of 112 and the third pair of wafer pads 113 are interchanged. That is, the third pair of wafer pads 113 (the second transmit differential pair of wafer pads 113a (TX2+) and 113b (TX2-)) and the fourth pair of wafer pads 114 (the first receive differential pair of wafer pads 114a (RX1+) and 114b (RX1-)) are sequentially arranged in the first row R1 along the side edge of the active surface 102 . The second pair of wafer pads 112 (the second receive differential pair of wafer pads 112a (RX2+) and 112b (RX2-)) and the first pair of wafer pads 111 (the first transmit differential pair of wafer pads 111a (TX1+) and 111b (TX1) -)) The second row R2 is sequentially arranged along the side edge of the active surface 102 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the integrated circuit chip 100 , that is, closer to the outer side of the integrated circuit chip 100 . Similar to FIG. 2A, the same set of transmit differential pair wafer pads and receive differential pair wafer pads are arranged in non-adjacent, different rows, approximately diagonally. Since the projections of the same group of T/R differential pair wafer pads on the X-axis or Y-axis do not overlap each other, the projections of different groups of T/R differential pair wafer pads on the X-axis or Y-axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

Referring to FIG. 2C , compared with the embodiment of FIG. 2A , in this embodiment, only the positions of the second pair of wafer pads 112 and the third pair of wafer pads 113 in FIG. 2A are exchanged. That is, the third pair of wafer pads 113 (the second transfer differential pair of wafer pads 113a (TX2+) and 113b (TX2-)) and the first pair of wafer pads 111 (the first transfer differential pair of wafer pads 111a (TX1+) and 111b ( TX1 − )) are sequentially arranged in a first row R1 along one side edge of the active surface 102 . A fourth pair of die pads 114 (first receive differential pair of die pads 114a (RX1+) and 114b (RX1-)) and a second pair of die pads 112 (second receive differential pair of die pads 112a (RX2+) and 112b (RX2 -)) The second row R2 is sequentially arranged along the side edge of the active surface 102 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the integrated circuit chip 100 , that is, closer to the outer side of the integrated circuit chip 100 . Similar to FIG. 2A, the same set of transmit differential pair wafer pads and receive differential pair wafer pads are arranged in different rows, not adjacent, approximately diagonally. Since the projections of the same group of T/R differential pair wafer pads on the X-axis or Y-axis do not overlap each other, the projections of different groups of T/R differential pair wafer pads on the X-axis or Y-axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

Referring to FIG. 2D , compared with the embodiment of FIG. 2A , in this embodiment, only the positions of the first pair of wafer pads 111 and the fourth pair of wafer pads 114 in FIG. 2A are exchanged. That is, the second pair of die pads 112 (the second receive differential pair of die pads 112a (RX2+) and 112b (RX2-)) and the fourth pair of die pads 114 (the first receive differential pair of die pads 114a (RX1+) and 114b (RX1-)) are sequentially arranged in the first row R1 along the side edge of the active surface 102 . The first pair of wafer pads 111 (the first transfer differential pair of wafer pads 111a (TX1+) and 111b (TX1-)) and the third pair of wafer pads 113 (the second transfer differential pair of wafer pads 113a (TX2+) and 113b (TX2) -)) The second row R2 is sequentially arranged along the side edge of the active surface 102 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the integrated circuit chip 100 , that is, closer to the outer side of the integrated circuit chip 100 . Similar to FIG. 2A, the same set of transmit differential pair wafer pads and receive differential pair wafer pads are arranged in different rows, not adjacent, approximately diagonally. Since the projections of the same group of T/R differential pair wafer pads on the X-axis or Y-axis do not overlap each other, the projections of different groups of T/R differential pair wafer pads on the X-axis or Y-axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

FIGS. 3A to 3C show an embodiment based on the die pad arrangement of FIG. 2A with an additional ground (GND/VSS) die pad, so that the transmit differential pair pads and the receive differential pair die pads are in the same set. achieve more isolation between them. Likewise, FIGS. 3A to 3C are viewed from the back side of the integrated circuit chip 100 , that is, a top-down plan view, so the die pads 104 are indicated by dotted lines, and the die pads 104 are disposed on the integrated circuit chip. 100 active side.

In Figure 3A, a grounded wafer pad is inserted in the center of the wafer pad array. In other words, the first die pad array 110 includes a first ground die pad 115 located between the first pair of die pads 111 , the second pair of die pads 112 , the third pair of die pads 113 and the fourth pair of die pads 114 between. In detail, when electrically conducting, the ground chip pad 115 isolates the first transmit differential pair chip pads 111a and 111b (TX1+ and TX1-) from the first receive differential pair chip pads 114a and 114b (RX1+ and RX1). -). In other words, the grounded wafer pads 115 are disposed between the first transfer differential pair wafer pads 111a and the first receive differential pair wafer pads 114b, wherein the same group of transfer/receive differential pair wafer pads (the first pair of wafer pads 111 and For the fourth pair of wafer pads 114), the first transfer differential pair wafer pad 111a and the first receiving differential pair wafer pad 114a have the shortest distance. Similarly, in another embodiment, when electrically conducting, the ground chip pad 115 isolates the second transmit differential pair chip pads 113a and 113b (TX2+ and TX2-) from the second receive differential pair chip pad 112a and 112b (RX2+ and RX2-). In other words, the grounded wafer pads 115 are disposed between the second transfer differential pair wafer pads 113a and the second receive differential pair wafer pads 112b, wherein the same group of transfer/receive differential pair wafer pads (the third pair of wafer pads 113 and the For the second pair of wafer pads 112), the second differential pair of wafer pads 113a for transfer and the second pair of wafer pads for reception 112b have the shortest distance. Compared with FIG. 2A , the configuration of the grounded chip pads 115 can further avoid the problem of signal coupling between the same group of transmit/receive differentials to the chip pads.

Compared with FIG. 3A , FIG. 3B additionally adds two second ground chip pads 116 and third ground chip pads 117 , that is, there are three ground chip pads in this embodiment. In this embodiment, the additionally added second ground wafer pads 116 and third ground wafer pads 117 are disposed on the right and left sides of the first wafer pad array 110 , respectively. In other words, viewed from left to right in the X direction, the pads are the third ground die pad 117 , the second/fourth pair of die pads 112/114 , the first ground die pad 115 , the first/fourth die pad Three pairs of wafer pads 111 / 113 and a second ground wafer pad 116 . Viewed from bottom to top in the Y direction, the pads are the first/second pair of chip pads 111/112, the first/second/third ground chip pads 115/116/117, and the third/fourth pair of chip pads 113/114. That is to say, the second ground die pads 116 are located on the side of the first pair of die pads 111 and the third pair of die pads 113 that are farther from the first ground die pads 115 . The third ground die pads 117 are located on the side of the second pair of die pads 112 and the fourth pair of die pads 114 that are farther from the first ground die pads 115 . Such a chip pad configuration can also further avoid the problem of signal coupling between the same group of transmit/receive differentials to the chip pads.

Compared with FIG. 3A , FIG. 3C additionally adds two second ground chip pads 116 and third ground chip pads 117 , that is, there are three ground chip pads in this embodiment. In this embodiment, the additional second ground wafer pads 116 and the third ground wafer pads 117 are respectively disposed between the first pair of wafer pads 111 and the third pair of wafer pads 113 , and between the second pair of wafer pads 112 and the third pair of wafer pads 112 , respectively. between the four pairs of wafer pads 114 . In other words, viewed from left to right in the X direction, the pads are the second receiving differential pair die pad 112a (RX2+)/the first receiving differential pair die pad 114a (RX1+), and the third grounding die in sequence. Pad 117 , second receiving differential pair wafer pad 112b (RX2-)/first receiving differential pair wafer pad 114b (RX1-), first ground wafer pad 115, first transmitting differential pair wafer pad 111a (TX1+) /The second transmission differential pair wafer pad 113a (TX2+), the second ground wafer pad 116, the first transmission differential pair wafer pad 111b (TX1-)/the second transmission differential pair wafer pad 113b (TX2-). Viewed from bottom to top in the Y direction, the pads are the first/second pair of chip pads 111/112, the first/second/third ground chip pads 115/116/117, and the third/fourth pair of chip pads 113/114. That is, the second ground die pads 116 are located between the first pair of die pads 111 and the third pair of die pads 113 . The third ground die pads 117 are located between the second pair of die pads 112 and the fourth pair of die pads 114 . Such a chip pad configuration can also further avoid the problem of signal coupling between the same group of transmit/receive differentials to the chip pads.

FIG. 4 shows another embodiment, viewed from the backside, top-down top view. The integrated circuit chip 100 also includes a second die pad array 120 . The second wafer pad array 120 is located on the active surface 102 and is aligned with the first wafer pad array 110 along the side edge of the active surface 102 . The wafer pad 104 layout of the second wafer pad arrangement 120 and the wafer pad 104 layout of the first wafer pad arrangement 110 are symmetrical to each other. That is to say, based on the symmetry line Z, the first wafer pad array 110 and the second wafer pad array 120 have a mirror image relationship. In this embodiment, two Type-C ports are used as an example, which is not intended to limit the application of the present invention. In addition, the first chip pad array 110 and the second chip pad array 120 respectively support a single Type-C port and are compatible with USB 4 or below specifications.

In the above embodiments, the first transmit differential pair of wafer pads 111a and 111b (TX1+ and TX1-), the first receive differential pair of wafer pads 114a and 114b (RX1+ and RX1-), the second transmit differential pair The die pads 113a and 113b (TX2+ and TX2-) and the second receive differential pair die pads 112a and 112b (RX2+ and RX2-) can be used as down ports of the USB hub.

5A-5D show the substrate pad arrangement for the differential pair signal of the USB Type-C port.

Please refer to FIG. 1 and FIG. 5A , the package substrate 200 includes a first substrate pad array 210 , which is composed of some of the substrate pads 204 , in this embodiment, for example, eight substrates supporting USB Type-C ports pad 204. The first substrate pad array 210 includes a first pair of substrate pads 211 , a second pair of substrate pads 212 , a third pair of substrate pads 213 and a fourth pair of substrate pads 214 . The first pair of substrate pads 211 and the second pair of substrate pads 212 are sequentially arranged in a first row R1 along a side edge of the wafer area 202 . The third pair of substrate pads 213 and the fourth pair of substrate pads 214 are sequentially arranged in a second row R2 along the side edge of the wafer area 202 . The first pair of substrate pads 211 are located between the side edge of the wafer area 202 and the third substrate pad 204 . The second pair of substrate pads 212 are located between the side edges of the wafer area 202 and the fourth substrate pads 204 . In addition, compared with the above-mentioned second row R2 , the first row R1 is farther away from the middle region of the package substrate 200 , that is, closer to the outer side of the package substrate 200 . In addition, in this embodiment, "row" is used to represent the positional relationship of the four pairs of substrate pads, but it is not used to limit the present invention. Positional relationship. Furthermore, if the electronic assembly 50 in FIG. 1 is viewed from top to bottom, the first pair of die pads 111 are electrically connected to the first pair of substrate pads 211 , and the second pair of die pads 112 are electrically connected to The second pair of substrate pads 212 is electrically connected, the third pair of die pads 113 is electrically connected to the third pair of substrate pads 213 , and the fourth pair of die pads 114 is electrically connected to the second pair of substrate pads 214 . The above-mentioned electrical connection can be accomplished through the conductive bumps 52 of FIG. 1 .

In addition, the first pair of substrate pads 211 includes a first transmission differential pair substrate pad 211 a ( TX1 + ) and another first transmission differential pair substrate pad 211 b ( TX1 − ). The second pair of substrate pads 212 includes a second receiving differential pair substrate pad 212a (RX2+) and another second receiving differential pair substrate pad 212b (RX2-). Therefore, from left to right in the figure, the first row R1 is a plurality of differential pair substrate pads 212a (RX2+), 212b (RX2-), 211a (TX1+), 211b (TX1-) in sequence. The fourth pair of substrate pads 214 includes a first receiving differential pair substrate pad 214a (RX1+) and another first receiving differential pair substrate pad 214b (RX1-). The third pair of substrate pads 213 includes a second transmission differential pair substrate pad 213 a ( TX2 + ) and another second transmission differential pair substrate pad 213 b ( TX2 − ). Therefore, the second row R2 is a plurality of differential pair substrate pads 214a (RX1+), 214b (RX1-), 213a (TX2+), 213b (TX2-) in sequence from left to right in the figure. It should be noted that the above-mentioned order of the plurality of differential pair substrate pads from left to right is only a description manner, but is not limited to this description manner. In addition, the positions of the substrate pads 214 of the same pair of differential substrate pads 211-214 can be interchanged with each other, for example, the first transmission differential pair substrate pad 211a (TX1+) and the first transmission differential pair substrate pad 211b ( TX1-), in this embodiment, it is only one of the description methods, and is not used to limit the present invention.

Because USB TYPE-C ports can be flipped, each port needs to be configured with at least 2 sets of transmit/receive differential pair signals, but when electrically connected, only one set of transmit/receive differential pair signals will be turned on. According to the above-described embodiment, the first transmit differential pair substrate pads 211a and 211b (TX1+, TX1-) and the first receive differential pair substrate pads 214a and 214b (RX1+, RX1-) are not adjacent to each other and in different rows, while is approximately diagonal to ensure unnecessary coupling. Likewise, the second transmit differential pair substrate pads 213a and 213b (TX2+, TX2-) and the second receive differential pair substrate pads 212a and 212b (RX2+, RX2-) are not adjacent to each other, in different rows, but at approximately Diagonal position to ensure unnecessary coupling. Further, from the perspective of mutually perpendicular XY coordinates, the projections of the first pair of substrate pads 211 and the fourth pair of substrate pads 214 on the X-axis or the Y-axis do not overlap each other, which means that the first pair of substrate pads 211 and the fourth pair of substrate pads 214 do not overlap each other. The projections of the four pairs of substrate pads 214 on a straight line parallel to the first row R1 or on another straight line perpendicular to the first row R1 do not overlap each other. The projections of the third pair of substrate pads 213 and the second substrate pads 212 on the X-axis or the Y-axis do not overlap each other, which means that the third pair of substrate pads 213 and the second pair of substrate pads 212 are parallel to the first row R1 The projections on a line or another line perpendicular to the first row R1 do not overlap each other. The projections of the first pair of substrate pads 211 and the third pair of substrate pads 213 on the X-axis partially overlap or completely overlap each other; the projections of the fourth pair of substrate pads 214 and the second pair of substrate pads 212 on the X-axis partially overlap each other or completely overlapped, that is, the projections of the first pair of substrate pads 211 and the third pair of substrate pads 213 on a line parallel to the first row R1 partially overlap or completely overlap each other, and the fourth pair of substrate pads 214 and the second pair of substrate pads The projections of the substrate pads 212 on the aforementioned straight lines partially or completely overlap each other. The projections of the first pair of substrate pads 211 and the second pair of substrate pads 212 on the Y-axis partially overlap or completely overlap each other. The projections of the third pair of substrate pads 213 and the fourth pair of substrate pads 214 on the Y-axis partially overlap or completely overlap each other, which means that the first pair of substrate pads 211 and the second pair of substrate pads 212 are perpendicular to the first row R1 The projections on the straight line partially or completely overlap each other, and the projections of the third pair of substrate pads 213 and the fourth pair of substrate pads 214 on the aforementioned straight line partially overlap or completely overlap each other. In addition, the above-mentioned differential pair substrate pads 211 to 214 are compatible with USB 4 or lower specifications.

Please refer to FIG. 5B , compared with the embodiment of FIG. 5A , in this embodiment, the positions of the first pair of substrate pads 211 and the fourth pair of substrate pads 214 in FIG. 5A are exchanged, and the second pair of substrate pads in FIG. 5A are originally The positions of 212 and the third pair of substrate pads 213 are interchanged. That is, the third pair of substrate pads 213 (the second transmit differential pair substrate pads 213a (TX2+) and 213b (TX2-)) and the fourth pair of substrate pads 214 (the first receive differential pair substrate pad 214a (RX1+)) and 214b (RX1-)) are sequentially arranged in a first row R1 along the side edge of the wafer region 202. The second pair of substrate pads 212 (second receive differential pair substrate pads 214a (RX2+) and 214b (RX2-)) and the first pair of substrate pads 211 (first transmit differential pair substrate pads 211a (TX1+) and 211b (TX1) -)) The second row R2 is sequentially arranged along the side edge of the wafer area 202 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the package substrate 200 , that is, closer to the outer side of the package substrate 200 . Similar to Figure 5A, the same set of transmit differential pair substrate pads and receive differential pair substrate pads are arranged in non-adjacent, different rows, approximately diagonally. Since the projections of the transmit/receive differential pair substrate pads of the same group on the X axis or the Y axis do not overlap each other, the projections of the transmit/receive differential pair substrate pads of different groups on the X axis or the Y axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

Please refer to FIG. 5C , compared with the embodiment of FIG. 5A , in this embodiment, only the positions of the second pair of substrate pads 212 and the third pair of substrate pads 213 in FIG. 5A are exchanged. That is, the third pair of substrate pads 213 (second transmission differential pair substrate pads 213a (TX2+) and 213b (TX2-)) and the first pair of substrate pads 211 (first transmission differential pair substrate pad 211a (TX1+) and 211b (TX1-)) are sequentially arranged in a first row R1 along one side edge of the wafer area 202. A fourth pair of substrate pads 214 (first receive differential pair substrate pads 214a (RX1+) and 214b (RX1-)) and a second pair of substrate pads 212 (second receive differential pair substrate pads 212a (RX2+) and 212b (RX2) -)) The second row R2 is sequentially arranged along the side edge of the wafer area 202 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the package substrate 200 , that is, closer to the outer side of the package substrate 200 . Similar to Figure 5A, the same set of transmit differential pair substrate pads and receive differential pair substrate pads are arranged in non-adjacent, different rows, approximately diagonally. Since the projections of the transmit/receive differential pair substrate pads of the same group on the X axis or the Y axis do not overlap each other, the projections of the transmit/receive differential pair substrate pads of different groups on the X axis or the Y axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

Referring to FIG. 5D , compared with the embodiment of FIG. 5A , in this embodiment, only the positions of the first pair of substrate pads 211 and the fourth pair of substrate pads 214 in FIG. 5A are exchanged. That is, the second pair of substrate pads 212 (the second receiving differential pair substrate pads 212a (RX2+) and 212b (RX2-)) and the fourth pair of substrate pads 214 (the first receiving differential pair substrate pad 214a (RX1+)) and 214b (RX1-)) are sequentially arranged in a first row R1 along the side edge of the wafer region 202. The first pair of substrate pads 211 (first transmission differential pair substrate pads 211a (TX1+) and 211b (TX1-)) and the third pair of substrate pads 213 (second transmission differential pair substrate pads 213a (TX2+) and 213b (TX2 -)) The second row R2 is sequentially arranged along the side edge of the wafer area 202 . Compared with the above-mentioned second row R2 , the first row R1 is further away from the middle area of the package substrate 200 , that is, closer to the outer side of the package substrate 200 . Similar to Figure 5A, the same set of transmit differential pair substrate pads and receive differential pair substrate pads are arranged in non-adjacent, different rows, approximately diagonally. Since the projections of the transmit/receive differential pair substrate pads of the same group on the X axis or the Y axis do not overlap each other, the projections of the transmit/receive differential pair substrate pads of different groups on the X axis or the Y axis partially overlap each other and Completely overlapping, so also avoid unnecessary coupling.

FIGS. 6A to 6C show an embodiment based on the substrate pad arrangement of FIG. 5A with the addition of ground (GND/VSS) substrate pads to transmit differential pair substrate pads and receive differential pair substrate pads in the same set. achieve more isolation between them. Similarly, these FIGS. 6A to 6C are viewed from the back of the package substrate 200 , that is, a top-down plan view, so the substrate pads 204 are represented by dotted lines, and the substrate pads 204 are arranged in the chip area of the package substrate 200 . 202. In some embodiments, the ground wafer pads of FIGS. 3A to 3C may be electrically connected to the corresponding ground substrate pads of FIGS. 6A to 6C through conductive bumps.

In Figure 6A, a grounded substrate pad is inserted in the center of the substrate pad array. In other words, the first substrate pad array 210 includes a first ground substrate pad 215 located between the first pair of substrate pads 211 , the second pair of substrate pads 212 , the third pair of substrate pads 213 and the fourth pair of substrate pads 214 between. Specifically, when electrically conducting, the ground substrate pad 215 isolates the first transmit differential pair substrate pads 211a and 211b (TX1+ and TX1-) from the first receive differential pair substrate pads 214a and 214b (RX1+ and RX1). -). In other words, the ground substrate pad 215 is disposed between the first transmitting differential pair substrate pad 211a and the first receiving differential pair substrate pad 214b, wherein the same group of transmit/receive differential pair substrate pads (the first pair of substrate pads 211 and the For the fourth pair of substrate pads 214), the first transmission differential pair substrate pad 211a and the first receiving differential pair substrate pad 214b have the shortest distance. Similarly, in another embodiment, the ground substrate pad 215 isolates the second transmit differential pair substrate pads 213a and 213b (TX2+ and TX2-) from the second receive differential pair substrate pad 212a when electrically conducting and 212b (RX2+ and RX2-). In other words, the ground substrate pads 215 are disposed between the second transmitting differential pair substrate pads 213a and the second receiving differential pair substrate pads 212b, wherein the same group of transmit/receive differential pair substrate pads (the third pair of substrate pads 213 and the For the second pair of substrate pads 212), the second transfer differential pair substrate pad 213a and the second receiving differential pair substrate pad 212b have the shortest distance. Compared with FIG. 5A , the configuration of the ground substrate pads 215 can further avoid the problem of signal coupling of the same group of transmit/receive differentials to the chip pads.

Compared with FIG. 6A , FIG. 6B additionally adds two second ground substrate pads 216 and third ground substrate pads 217 , that is, there are three ground substrate pads in this embodiment. In this embodiment, the additionally added second ground substrate pads 216 and third ground substrate pads 217 are disposed on the right and left sides of the first substrate pad array 210 , respectively. In other words, viewed from left to right in the X direction, the pads are the third grounded substrate pad 217, the second/fourth pair of substrate pads 212/214, the first grounded substrate pad 215, the first/third grounded substrate pad Three pairs of substrate pads 211 / 213 and a second ground substrate pad 216 . Viewed from bottom to top in the Y direction, the pads are the first/second pair of substrate pads 211/212, the first/second/third ground substrate pads 215/216/217, and the third/fourth pair of substrate pads 213/214. That is to say, the second ground substrate pads 216 are located on the side of the first pair of substrate pads 211 and the third pair of substrate pads 213 farther from the first ground substrate pads 215 . The third ground substrate pads 217 are located on the side of the second pair of substrate pads 212 and the fourth pair of substrate pads 214 that are farther from the first ground substrate pads 215 . Such a substrate pad configuration can also further avoid the problem of signal coupling of the same group of transmit/receive differentials to the chip pads.

Compared with FIG. 6A , FIG. 6C additionally adds two second ground substrate pads 216 and third ground substrate pads 217 , that is, there are three ground substrate pads in this embodiment. In this embodiment, the additional second ground substrate pads 216 and the third ground substrate pads 217 are respectively disposed between the first pair of substrate pads 211 and the third pair of substrate pads 213 , and between the second pair of substrate pads 212 and the third pair of substrate pads 213 , respectively. between the four pairs of substrate pads 214 . In other words, viewed from left to right in the X direction, the pads are the second receiving differential pair substrate pad 212a (RX2+)/the first receiving differential pair substrate pad 214a (RX1+), the third ground substrate in sequence Pad 217, second receiving differential pair substrate pad 212b (RX2-)/first receiving differential pair substrate pad 214b (RX1-), first ground substrate pad 215, first transmitting differential pair substrate pad 211a (TX1+) /The second transmission differential pair substrate pad 213a (TX2+), the second ground substrate pad 216, the first transmission differential pair substrate pad 211b (TX1-)/the second transmission differential pair substrate pad 213b (TX2-). Viewed from bottom to top in the Y direction, the pads are the first/second pair of substrate pads 211/212, the first/second/third ground substrate pads 215/216/217, and the third/fourth pair of substrate pads 213/214. That is, the second ground substrate pads 216 are located between the first pair of substrate pads 211 and the third pair of substrate pads 213 . The third ground substrate pads 217 are located between the second pair of substrate pads 212 and the fourth pair of substrate pads 214 . Such a substrate pad configuration can also further avoid the problem of signal coupling of the same group of transmit/receive differentials to the chip pads.

FIG. 7 shows another embodiment, viewed from the backside, top-down top view. The package substrate 200 further includes a second substrate pad array 220 . The second substrate pad array 220 is located on the wafer area 202 and is side by side with the first substrate pad array 210 along the side edges of the wafer area 202 . The substrate pad 204 layout of the second substrate pad array 220 and the substrate pad 204 layout of the first substrate pad array 210 are symmetrical to each other. That is to say, taking the symmetry line Z as a reference, the first substrate pad array 210 and the second substrate pad array 220 have a mirror image relationship. In this embodiment, two Type-C ports are used as an example, which is not intended to limit the application of the present invention. In addition, the first substrate pad array 210 and the second substrate pad array 220 respectively support a single Type-C port and are compatible with USB 4 or below specifications.

In the above embodiments, the first transmit differential pair substrate pads 211a and 211b (TX1+ and TX1-), the first receive differential pair substrate pads 214a and 214b (RX1+ and RX1-), the second transmit differential pair The substrate pads 213a and 213b (TX2+ and TX2-) and the second receive differential pair substrate pads 212a and 212b (RX2+ and RX2-) can be used as down ports of the USB hub.

FIG. 7 shows another embodiment, the package substrate 200 further includes a second substrate pad array 220 . The second substrate pad array 220 is located on the wafer area 202 and is side by side with the first substrate pad array 210 along the side edges of the wafer area 202 . The substrate pad 204 layout of the second substrate pad array 220 and the substrate pad 204 layout of the first substrate pad array 210 are symmetrical to each other. That is to say, taking the symmetry line Z as a reference, the first substrate pad array 210 and the second substrate pad array 220 have a mirror image relationship. In this embodiment, two Type-C ports are used as an example, which is not intended to limit the application of the present invention. In addition, the first substrate pad array 210 and the second substrate pad array 220 respectively support a single Type-C port and are compatible with USB 4 or below specifications.

Referring to FIGS. 5A and 8 , in this embodiment, the packaging substrate 200 may include a plurality of patterned conductive layers 231 (patterned conductive layers), a plurality of dielectric layers 232 (dielectric layers), and a plurality of conductive vias 233 ( conductive via). The patterned conductive layers 231 include a first patterned conductive layer 231a, a second patterned conductive layer 231b and one or more third patterned conductive layers 231c, wherein the first substrate pad arrangement 210 is formed from the first patterned Conductive layer 231a. The dielectric layers 232 are alternately stacked with the patterned conductive layers 231a-c. The conductive vias 233 pass through the dielectric layers 232 to connect the patterned conductive layers 231a-c.

In addition, the package substrate 200 may further include a first differential pair wiring 241 , a second differential pair wiring 242 and one or more ground planes 243 . The first differential pair wirings 241 are formed from the first patterned conductive layer 231 a and are respectively connected to the first pair of substrate pads 211 or/and the second pair of substrate pads 212 of the first row R1 closer to the side edge of the wafer region 202 . The second differential pair traces 242 are formed from the second patterned conductive layer 231b and are electrically connected to the third pair of the second row R2 farther from the side edge of the wafer region 202 through the patterned conductive layers 231c and the conductive vias 233 The substrate pads 213 or/and the fourth pair of substrate pads 214 . One or more ground planes 243 are formed from the third patterned conductive layer 231 c and are located between the first differential pair wiring 241 and the second differential pair wiring 242 . Thus, the same set of differential pair substrate pads 204 (eg, the first transmit differential pair substrate pads 211a, 211b in row R1 and the first receive differential pair substrate pads 214a, 214b in row R2) can pass through electrical conduction. The holes 233 are routed on the two different patterned conductive layers 231a, 231b of the package substrate 200, and the ground plane 243 is further located between the first differential pair wiring 241 and the second differential pair wiring 242, thereby reducing the same Crosstalk between differential pairs of group transmit and receive (TX and RX). In addition, the ground substrate pads in the embodiments of FIGS. 6A to 6C can also be electrically connected to the ground planes 243 .

To sum up, in the above-mentioned embodiments of the present invention, as far as the integrated circuit chip is concerned, by arranging the two groups of transmit and receive (TX and RX) differential pair chip pads along the side edge of the active surface in two row, and place the same group of transmitting and receiving differential pair wafer pads in different row positions to reduce crosstalk between the same group of transmitting and receiving differential pair wafer pads. In addition, by arranging the two sets of transmit and receive (TX and RX) differential pair die pads in two rows, it can reduce the size of the integrated circuit die, thereby reducing the cost.

For package substrates, by arranging two sets of transmit and receive (TX and RX) differential pair substrate pads in two rows along the side edge of the wafer area, and placing the same set of transmit and receive differential pair substrate pads in two rows Different row positions to reduce crosstalk between the same set of transmit and receive differential pair substrate pads.

50: Electronic assembly 52: Conductive bumps 54: Conductive ball 100: Integrated circuit chip 102: Active side 104: Wafer pad 110: First wafer pad arrangement 111: The first pair of wafer pads 111a, 111b: first transfer differential pair wafer pads 112: Second pair of wafer pads 112a, 112b: second receive differential pair wafer pads 113: The third pair of wafer pads 113a, 113b: second transfer differential pair wafer pads 114: Fourth pair of wafer pads 114a, 114b: first receive differential pair wafer pads 115: First ground wafer pad 116: Second ground wafer pad 117: Third Ground Die Pad 120: Second wafer pad arrangement 200: Package substrate 202: Wafer area 204: Substrate pad 210: First substrate pad arrangement 211: The first pair of substrate pads 211a, 211b: first transfer differential pair substrate pad 212: Second pair of substrate pads 212a, 212b: second receiving differential pair substrate pads 213: The third pair of substrate pads 213a, 213b: the second transfer differential pair substrate pad 214: Fourth pair of substrate pads 214a, 214b: first receiving differential pair substrate pads 215: First ground substrate pad 216: Second ground substrate pad 217: Second ground substrate pad 220: Second substrate pad arrangement 231: Patterned conductive layer 231a: the first patterned conductive layer 231b: the second patterned conductive layer 231c: third patterned conductive layer 232: Dielectric layer 233: Conductive Vias 241: The first differential pair routing 242: Second differential pair routing 243: Ground Plane R1: first row R2: Second row

FIG. 1 is a schematic side view of an electronic assembly according to an embodiment of the present invention. FIG. 2A is a partial top schematic view of the integrated circuit chip of FIG. 1 . FIG. 2B is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. FIG. 2C is a partial top plan view of an integrated circuit chip according to another embodiment of the present invention. FIG. 2D is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. FIG. 3A is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. 3B is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. FIG. 3C is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. 4 is a partial top schematic view of an integrated circuit chip according to another embodiment of the present invention. FIG. 5A is a partial top schematic view of the package substrate of FIG. 1 . FIG. 5B is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 5C is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 5D is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 6A is a partial top schematic view of a package substrate according to another embodiment of the present invention. FIG. 6B is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 6C is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 7 is a partial top plan view of a package substrate according to another embodiment of the present invention. FIG. 8 is a partially enlarged schematic cross-sectional view of the electronic assembly of FIG. 1 .

100: Integrated circuit chip

102: Active side

104: Wafer pad

110: First wafer pad arrangement

111: The first pair of wafer pads

111a, 111b: first transfer differential pair wafer pads

112: Second pair of wafer pads

112a, 112b: second receive differential pair wafer pads

113: The third pair of wafer pads

113a, 113b: second transfer differential pair wafer pads

114: Fourth pair of wafer pads

114a, 114b: first receive differential pair wafer pads

R1: first row

R2: Second row

Claims (26)

An integrated circuit chip has an active surface and a first array of chip pads located on the active surface, the first array of chip pads includes: a first pair of chip pads; a second pair of chip pads; a third pair of chips pads; and a fourth pair of chip pads, wherein the first pair of chip pads and the second pair of chip pads are sequentially arranged in a first row along a side edge of the active surface, the third pair of chip pads and the The fourth pair of chip pads are sequentially arranged in a second row along the side edge of the active surface, the first pair of chip pads are located between the side edge of the active surface and the third pair of chip pads, the second pair of chip pads The pair of wafer pads is located between the side edge of the active surface and the fourth pair of wafer pads, the first pair of wafer pads is one of a first transfer differential pair wafer pad and a first receiving differential pair wafer pad , the fourth pair of wafer pads is the other of the first transfer differential pair of wafer pads and the first receiving differential pair of wafer pads, the second pair of wafer pads is a second transfer differential pair of wafer pads and a One of the second receiving differential pair of wafer pads, the third pair of wafer pads is the other of the second transfer differential pair of wafer pads and the second receiving differential pair of wafer pads. The integrated circuit chip of claim 1, wherein projections of the first pair of die pads and the fourth pair of die pads on a line parallel to the first row or on another straight line perpendicular to the first row do not overlap. The integrated circuit chip of claim 1, wherein projections of the third pair of die pads and the second pair of die pads on a line parallel to the first row or on another straight line perpendicular to the first row do not overlap. The integrated circuit chip of claim 1, wherein projections of the first pair of die pads and the third pair of die pads on a line parallel to the first row partially or completely overlap each other, and the fourth The projections of the wafer pads and the second pair of wafer pads on the straight line are partially or completely overlapped with each other. The integrated circuit chip of claim 1, wherein projections of the first pair of die pads and the second pair of die pads on a line perpendicular to the first row partially overlap or completely overlap each other, and the third The projections of the wafer pads and the fourth pair of wafer pads on the straight line are partially or completely overlapped with each other. The integrated circuit chip of claim 1, wherein the first chip pad arrangement further comprises: a grounded chip pad located on the first pair of chip pads, the second pair of chip pads, the third pair of chip pads and the between the fourth pair of wafer pads. The integrated circuit chip of claim 1, wherein the first die pad arrangement further comprises: a first grounded die pad located on the first pair of die pads, the second pair of die pads, and the third pair of die pads and between the fourth pair of wafer pads; a second ground chip pad on the side of the first pair of chip pads and the third pair of chip pads farther from the first ground chip pad; and a third ground chip pad on the second pair of chip pads and the The fourth pair of chip pads is further away from the side of the first grounded chip pad. The integrated circuit chip of claim 1, wherein the first die pad arrangement further comprises: a first grounded die pad located on the first pair of die pads, the second pair of die pads, and the third pair of die pads and between the fourth pair of chip pads; a second ground chip pad between the first pair of chip pads and the third pair of chip pads; and a third ground chip pad between the second pair of chip pads and the third pair of chip pads between four pairs of wafer pads. The integrated circuit chip of claim 1, further comprising: an array of second chip pads located on the active surface and arranged side by side with the first chip pads along the side edge of the active surface, wherein the second The wafer pad arrangement of the wafer pad arrangement and the wafer pad arrangement of the first wafer pad arrangement are symmetrical to each other. The integrated circuit chip of claim 9, wherein the die pad layout of the second die pad arrangement has a mirror image relationship with the die pad layout of the first die pad arrangement. A package substrate, suitable for mounting an integrated circuit chip by flip-chip bonding, has a chip area and a first substrate pad arrangement located in the chip area, the first substrate pad arrangement comprising: a first pair of substrate pads; a second pair of substrate pads; a third pair of substrate pads; and a fourth pair of substrate pads, wherein the first pair of substrate pads and the second pair of substrate pads are along a The side edges are sequentially arranged in a first row, the third pair of substrate pads and the fourth pair of substrate pads are sequentially arranged in a second row along the side edges of the chip area, and the first pair of substrate pads are located in the between the side edge of the wafer area and the third pair of substrate pads, the second pair of substrate pads is located between the side edge of the wafer area and the fourth pair of substrate pads, the first pair of substrate pads is a first pair of substrate pads one of a transfer differential pair substrate pad and a first receiving differential pair substrate pad, the fourth pair substrate pad is the other of the first transfer differential pair substrate pad and the first receiving differential pair substrate pad , the second pair of substrate pads is one of a second transmission differential pair substrate pad and a second receiving differential pair substrate pad, and the third pair of substrate pads is the second transmission differential pair substrate pad and the first differential pair substrate pad Two receive the other of the differential pair of substrate pads. The package substrate of claim 11, wherein projections of the first pair of substrate pads and the fourth pair of substrate pads on a line parallel to the first row or on another straight line perpendicular to the first row do not overlap each other . The package substrate of claim 11, wherein projections of the third pair of substrate pads and the second pair of substrate pads on a line parallel to the first row or on another straight line perpendicular to the first row do not overlap each other . The package substrate of claim 11, wherein projections of the first pair of substrate pads and the third pair of substrate pads on a line parallel to the first row partially overlap or completely overlap each other, and the fourth pair of substrates The projections of the pads and the second pair of substrate pads on the straight line partially or completely overlap each other. The package substrate of claim 11, wherein projections of the first pair of substrate pads and the second pair of substrate pads on a line perpendicular to the first row partially overlap or completely overlap each other, and the third pair of substrates The projections of the pads and the fourth pair of substrate pads on the straight line partially overlap or completely overlap each other. The package substrate of claim 11, wherein the first substrate pad arrangement further comprises: a grounded substrate pad located on the first pair of substrate pads, the second pair of substrate pads, the third pair of substrate pads and the fourth pair of substrate pads between the substrate pads. The package substrate of claim 11, wherein the first substrate pad arrangement further comprises: a first ground substrate pad located on the first pair of substrate pads, the second pair of substrate pads, the third pair of substrate pads and the between the fourth pair of substrate pads; a second ground substrate pad located on the side of the first pair of substrate pads and the third pair of substrate pads farther from the first ground substrate pad; and a third ground substrate pad located on the second pair of substrate pads and the The fourth pair of substrate pads is farther from the side of the first ground substrate pad. The package substrate of claim 11, wherein the first substrate pad arrangement further comprises: a first ground substrate pad located on the first pair of substrate pads, the second pair of substrate pads, the third pair of substrate pads and the between the fourth pair of substrate pads; a second ground substrate pad between the first pair of substrate pads and the third pair of substrate pads; and a third ground substrate pad between the second pair of substrate pads and the fourth pair between substrate pads. The packaging substrate of claim 11, further comprising: a second substrate pad array, located on the chip area and arranged side by side with the first substrate pad along the side edge of the chip area, wherein the second substrate pad The arrayed substrate pad layout and the first substrate pad arrayed substrate pad layout are symmetrical to each other. The package substrate of claim 19, wherein the substrate pad layout of the second substrate pad arrangement has a mirror-image relationship with the substrate pad layout of the first substrate pad arrangement. The packaging substrate of claim 11, further comprising: a plurality of patterned conductive layers, including a first patterned conductive layer, a second patterned conductive layer and a third patterned conductive layer, wherein the first substrate The pads are arranged from the first patterned conductive layer; a plurality of dielectric layers alternately stacked with the patterned conductive layers; a plurality of conductive vias passing through the dielectric layers to connect the patterned conductive layers; a first A differential pair wiring formed from the first patterned conductive layer and connected to the first pair of substrate pads or/and the second pair of substrate pads respectively; and a second differential pair wiring formed from the second pair of substrate pads The patterned conductive layer is electrically connected to the third pair of substrate pads or/and the fourth pair of substrate pads through the patterned conductive layers and the conductive through holes, respectively. The package substrate of claim 21, further comprising: a ground plane formed from the third patterned conductive layer and located between the first differential pair wiring and the second differential pair wiring. The package substrate of claim 22, wherein the first substrate pad arrangement further comprises: a grounded substrate pad located on the first pair of substrate pads, the second pair of substrate pads, the third pair of substrate pads and the fourth pair of substrate pads between the pair of substrate pads, and the ground substrate pad is electrically connected to the ground plane. An electronic assembly, comprising: a package substrate having a chip area and a first substrate pad array located in the chip area, the first substrate pad array comprising: a first pair of substrate pads; a second pair of substrate pads; a third pair of substrate pads; and A fourth pair of substrate pads, wherein the first pair of substrate pads and the second pair of substrate pads are sequentially arranged in a first row along a side edge of the wafer area, the third pair of substrate pads and the fourth pair The substrate pads are sequentially arranged in a second row along the side edge of the wafer area, the first pair of substrate pads are located between the side edge of the wafer area and the third pair of substrate pads, the second pair of substrate pads Located between the side edge of the wafer area and the fourth pair of substrate pads, the first pair of substrate pads is one of a first transfer differential pair substrate pad and a first receiving differential pair substrate pad, the first pair of substrate pads is The four pairs of substrate pads are the other of the first transfer differential pair substrate pad and the first receiver differential pair substrate pad, and the second pair of substrate pads are a second transfer differential pair substrate pad and a second receiver pair one of the differential pair substrate pads, the third pair of substrate pads is the other one of the second transfer differential pair substrate pad and the second receiving differential pair substrate pad; and an integrated circuit chip to flip chip The chip area of the package substrate is mounted in a bonding manner. The electronic assembly of claim 24, wherein the integrated circuit chip has an active surface and a first die pad arrangement on the active surface, the first die pad arrangement comprising: A first pair of wafer pads; a second pair of wafer pads; a third pair of wafer pads; and a fourth pair of wafer pads, wherein the first pair of wafer pads and the second pair of wafer pads are along a The side edges are sequentially arranged in a first row, the third pair of chip pads and the fourth pair of chip pads are sequentially arranged in a second row along the side edges of the active surface, and the first pair of chip pads are located in the between the side edge of the active surface and the third pair of chip pads, the second pair of chip pads is located between the side edge of the active surface and the fourth pair of chip pads, wherein the first pair of chip pads and the first pair of chip pads A pair of substrate pads is electrically connected, the second pair of chip pads is electrically connected to the second pair of substrate pads, the third pair of chip pads is electrically connected to the third pair of substrate pads, and the fourth pair of chip pads is electrically connected to The fourth pair of substrate pads are electrically connected. The electronic assembly of claim 25, wherein the first substrate pad arrangement further comprises: a grounded substrate pad located on the first pair of substrate pads, the second pair of substrate pads, the third pair of substrate pads and the first pair of substrate pads Between the four pairs of substrate pads, the first chip pad arrangement further includes: a ground chip pad located between the first pair of chip pads, the second pair of chip pads, the third pair of chip pads and the fourth pair of chip pads between, The ground chip pad is electrically connected to the ground substrate pad.

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