TWI761140B - Memmory chip - Google Patents

Abstract

The present invention discloses a memory chip. The memory chip includes a PUF block. The PUF block includes a number of memory cells. Each of the memory cells includes a transistor, a first resistor and a second resistor. A first terminal of the transistor is coupled to a source line. A second terminal of the transistor is coupled to a bit line. A first terminal of the first resistor is coupled to the first terminal of the transistor. The second terminal of the first resistor is coupled to a third terminal of the transistor. A first terminal of the second resistor is coupled to the third terminal of the transistor. A second terminal of the second resistor is coupled to the second terminal of the transistor.

Description

memory chip

The present invention relates to a memory device.

Physically Unclonable Function (PUF) is an important functional block in a memory chip, and its main contribution is in terms of security. The PUF block of the memory chip can provide the memory chip with a secure and unique PUF code (PUF code), which can be used as a security key for encryption/decryption, for example. As users pay more and more attention to security, PUF will become one of the important topics in future memory chip research and development.

An embodiment of the present invention discloses a memory chip. The memory chip includes a physically non-replicable block. The physical non-copyable block includes a plurality of bit lines, a plurality of source lines and a plurality of memory cells. The memory cells are divided into multiple columns and multiple rows, wherein the memory cells in the ith row and the jth column are coupled to the ith source line and the jth bit line, and i and j are positive integers. Each memory cell includes a transistor, a first resistor and a second resistor. A first end of the transistor is coupled to the source line corresponding to the memory cell, and a second end of the transistor is coupled to To the bit line corresponding to the memory cell, a first end of the first resistor is coupled to the first end of the transistor, and a second end of the first resistor is coupled to a first end of the transistor Three terminals, a first terminal of the second resistor is coupled to the third terminal of the transistor, and a second terminal of the second resistor is coupled to the second terminal of the transistor.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

10: Memory chip

102:PUF block

104: Control circuit

C11~Cmn, Cij: memory cells

BL1~BLn, BLj: bit line

SL1~SLm, SLi: source line

Tij: Transistor

Ra-ij: first resistor

Rb-ij: second resistor

Dij: Diode

30: Structure

G: gate metal

S: source layer

D: drain layer

M1-1~M1-3: The first metal layer

M2-1~M2-3: The second metal layer

M3: third metal layer

VA1: The first pilot hole

VA2: Second via hole

Ra: first resistive layer

Rb: second resistive layer

FIG. 1 shows a block diagram of a memory chip according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a memory cell of a PUF block according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating an IC layout structure of a memory cell of a PUF block according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a memory cell of a PUF block according to another embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a block diagram of a memory chip according to an embodiment of the present invention. The memory chip 10 includes a physically non-replicable functional block 102 and a control circuit 104 . For the sake of brevity of description, a Physically Unclonable Function (PUF) block will be referred to as a PUF block hereinafter. The PUF block 102 includes a plurality of memory cells C11 ˜Cmn, a plurality of source lines SL1 ˜SLm, and a plurality of bit lines BL1 ˜BLn, wherein m and n are positive integers. The memory cells C11-Cmn are divided into a plurality of rows and columns, wherein the memory cells in the i-th row are coupled to the i-th source line SLi, and the memory cells in the j-th column are coupled to the j-th bit line BLj, where i and j are positive integers and i=1~m, j=1~n. In one embodiment, the memory cells C11-Cmn are read only. The control circuit 104 is configured to operate the PUF block 102 .

Please refer to FIG. 2, which illustrates a block diagram of a memory cell of a PUF block according to an embodiment of the present invention. This embodiment is described by taking the memory cell Cij in the i-th row and the j-th column as an example. The memory cell Cij includes a transistor Tij, a first resistor Ra-ij and a second resistor Rb-ij. A first end (eg, drain) of the transistor Tij is coupled to the source line SLi, and a second end (eg, the source) of the transistor Tij is coupled to the bit line BLj. A first end of the first resistor Ra-ij is coupled to the first end of the transistor Tij and the source line SLi, and a second end of the first resistor Ra-ij is coupled to a third end of the transistor Tij terminal (eg gate). A first end of the second resistor Rb-ij is coupled to the third end of the transistor Tij, and a second end of the first resistor Ra-ij is coupled to the second end of the transistor Tij and the bit line BLj .

The operating principle is detailed below. When the memory cell Cij is to be read, a bias voltage Vb is applied to the bit line BLj by the control circuit 104, and the source line SLi is referenced to ground. At this time, the voltage at the third end of the transistor Tij is Vg=Vb*Ra-ij/(Ra-ji+Rb-ij). The voltage Vg of the third terminal of the transistor Tij is used as the gate voltage of the transistor Tij, which determines the magnitude of the current (ie, the drain current) Id flowing through the second terminal of the transistor Tij. In one embodiment, a reference voltage value Vref and/or a reference current value Vref are determined according to the characteristics of the transistor Tij, such as the relationship between the gate voltage and the drain current. When the gate voltage Vg is greater than or equal to the reference voltage value Vref, the drain current Id is greater than or equal to the reference current value Iref; when the gate voltage Vg is less than the reference voltage value Vref, the drain current Id is less than the reference current value Iref. With an appropriate configuration of Vd, the proportional relationship or magnitude relationship of the resistance values between the first resistor Ra-ij and the second resistor Rb-ij can be reflected in the magnitude between the drain current Id and the reference current value Iref relationship. In one embodiment, the bias voltage Vd is twice the threshold voltage Vt of the transistor Tij (ie, Vd=2*Vt), and the reference voltage value Vref is the voltage value of the threshold voltage Vt of the transistor Tij (eg For example, 0.6 volts), the reference current value Iref is the corresponding drain current (eg, 1 microampere) when the gate voltage is the threshold voltage. Therefore, when the resistance value of the first resistor Ra-ij is greater than or equal to the resistance value of the second resistor Rb-ij, the gate voltage Vg will be greater than or equal to Vt, and the drain current Id will be greater than or equal to the reference voltage value Iref , and determine that the memory cell Cij stores a first value (eg 1); when the resistance value of the first resistor Ra-ij is greater than or equal to the resistance value of the second resistor Rb-ij, the gate voltage Vg will be less than Vt, the drain current Id will be less than the reference voltage value Iref, and it is determined that the memory cell Cij stores a second value (eg, 0). The first resistor Ra-ij and the second resistor Rb-ij are implemented by, for example, one layer of conductive film respectively. In fact, due to the limitation of process technology, the resistance values of the first resistor Ra-ij and the second resistor Rb-ij are usually not completely the same as the expected ideal values. That is to say, although the ideal situation is that the resistance values of the first resistor Ra-ij and the second resistor Rb-ij are equal to each other, in practice, the first resistor Ra-ij is limited by the process technology. It is difficult to be equal to the resistance value of the second resistor Rb-ij, and for different memory cells, the magnitude relationship between the resistance values of the first resistor Ra-ij and the second resistor Rb-ij is difficult to rely on artificially. controlling. In other words, for each memory cell, the resistance value relationship between the first resistor Ra-ij and the second resistor Rb-ij is randomly determined. Therefore, for the PUF blocks of different memory chips, the values stored in these memory cells can form a randomly formed numerical pattern. Based on the randomness generated by this numerical pattern, it is difficult to predict and replicate by artificial force, which is in line with the core spirit of the inimitable function of physics.

It should be noted that the transistor Tij may be an NMOS or a PMOS, which is not limited in the present invention.

Please refer to FIG. 3 , which is a cross-sectional view illustrating an integrated circuit layout of a memory cell of a PUF block according to an embodiment of the present invention. Structure 30 in FIG. 3 shows a cross-sectional view of the IC layout structure of one memory cell Cij in the PUF block. The structure 30 includes a transistor structure region 302, a plurality of first metal layers M1-1~M1-3, a plurality of second metal layers M2-1~M2~3, a first resistance layer Ra, and a second resistance layer Rb and a third metal layer M3.

The transistor structure region 302 includes a drain layer D, a source layer S, and a gate metal layer G. The first metal layers M1-1 to M1-33 are insulated from each other and are respectively disposed/stacked on the drain layer D, the source layer S and the gate metal layer G, and are respectively connected to the drain layer D and the drain layer D through a conductive material , source layer S and gate metal layer G. The second metal layers M2-1 to M2-33 are insulated from each other and are respectively disposed/stacked on the first metal layers M1-1 to M1-3, and are respectively connected to the first metal through a first via VA1 and a conductive material. Layers M1-1~M1-3. The first resistance layer Ra is disposed/stacked on the second metal layer M2-3, the first metal layer M1-3 and the source layer S, and is connected to the second metal layer M2 through a second via VA2 and conductive material -1. The second resistance layer Rb is disposed/stacked on the second metal layer M2-1, the first metal layer M1-1 and the drain layer D, and is connected to the second metal layer through another second via VA2 and conductive material M2-1. The third metal layer M3 is disposed/stacked on the first resistance layer Ra and the second resistance layer Rb, and is connected to the first resistance layer Ra and the second resistance layer Rb through a conductive material, and passes through another second via VA2 and The conductive material is connected to the second metal layer M2-2. In the structure 30, the first metal layer M1-1 is used as the bit line BLj, and the second metal layer M2-3 is used as the source line SLi.

It should be noted that any transistor structure known in the art can be used to realize the transistor region structure 302 , and the present invention does not limit its manufacturing method.

Please refer to FIG. 4 . FIG. 4 illustrates a block diagram of a memory cell of a PUF block according to an embodiment of the present invention. The memory cell C'ij is similar to the memory cell Cij, except that the memory cell C'ij further includes a diode Dij. One end of the diode Dij is coupled to the first end of the transistor Tij, and a second end of the diode Dij is coupled to the first end of the first resistor Ra-ij. Generally speaking, the temperature of the memory chip may increase with the operation time during the operation, and the temperature change will cause the threshold voltage Vt of the transistor Tij to change accordingly. In terms of the influence of temperature change on the components, the transistor is a component with a positive temperature coefficient, and the diode is a component with a negative temperature coefficient. Therefore, by connecting the diode Dij to the transistor Tij in series, the temperature change can be compensated. The impact on the transistor Tij helps to improve the reliability of the memory cell C'ij.

In an alternative embodiment, in order to compensate for the effects of temperature changes, the control circuit 104 of the memory chip can adjust the bias voltage Vb according to the temperature of the memory chip. Specifically, according to the relationship between the threshold voltage Vt of the transistor Tij and the temperature, it can be known how the threshold voltage Vt changes with temperature, that is, the magnitude of the threshold voltage Vt at a specific temperature can be known. Therefore, in an alternative embodiment, the bias voltage Vb is changed according to the temperature of the memory chip, so that the predetermined proportional relationship between the bias voltage Vb and the threshold voltage Vt is maintained, that is, the critical point Vg=Vt=Vb *A/(A+B) proportional relationship, where A is the ideal resistance value of the first resistor, and B is the ideal resistance value of the second resistor. It should be noted that the ideal resistance value of the first resistor/the ideal resistance value of the second resistor here is different from the resistance value of the first resistor/the resistance value of the second resistor in the actual memory cell. , due to the limitation of the process technology, the actual resistance values of the first resistor and the second resistor may not be equal to their ideal resistance values, which is also the reason why they have physical inimitable characteristics.

In one embodiment, before the memory chip is shipped from the factory, multiple read tests are performed on the PUF block, so as to find unreliable memory cells in the PUF block. For example, during testing, the memory cells in the PUF block can be read multiple times (for example, a thousand times), and the memory cells whose output values are not all 1 or 0 can be recorded in a record table , since the output of these memory cells may change with the increase of the number of reads, they are regarded as unreliable memory cells. When the memory chip is operated by the user after leaving the factory, the memory cells recorded in the record table will be excluded from the security operation of the PUF block. For example, when generating a hardware security key based on a PUF block, the unreliable memory cells recorded in the record table will not be used.

In an alternative embodiment, in order to find unreliable memory cells, an upper limit value and a lower limit value can be set for the reference current value Iref. For each memory cell, perform read operation one or more times, and observe whether the output between the upper limit value and the lower limit value of the reference current value Iref is all 1 or 0, otherwise it is judged as an unreliable memory cell. For example, assuming that the upper limit value of the reference current value Iref is 10uA, the lower limit value is 1uA, the drain current Id obtained by a certain memory cell after the read operation is 9uA, and the range of the reference current value Iref is 1uA~10uA For example, 9uA is not always greater than or equal to the reference current value Iref, nor is it always less than the reference current value Iref, which means that the memory cell may be judged to store 1 in the range of possible reference current values, or it may be judged that it stores is 0 and thus is considered an unreliable memory cell. That is, during the read operation, the drain current of the transistor does not all fall outside the range formed by the upper limit value and the lower limit value of the reference current, and the memory cell is unreliable.

The present invention proposes a circuit and an integrated circuit layout structure of a memory cell of a PUF block, which effectively utilizes the limit of the process technology to generate a random variation of the value stored in the memory cell. organic. In addition, the present invention also provides various ways to effectively improve the reliability of the PUF block. Disposing the PUF block proposed by the present invention in the memory chip is equivalent to making the memory chip have a randomly generated numerical pattern, and the numerical pattern is difficult to be copied artificially due to the limitations of the process technology. In application, the hardware key can be generated as required by extracting all or part of the numerical pattern through a specific circuit and/or algorithm (eg, a hash function). Hardware keys can be used for security purposes such as encrypting/decrypting memory chips and connecting/locking memory chips with other hardware.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Cij: memory cell

BLj: bit line

SLi: source line

Tij: Transistor

Ra-ij: first resistor

Rb-ij: second resistor

Claims (10)

A memory chip, comprising: a physical block that cannot be imitated, including: a plurality of bit lines; a plurality of source lines; The memory cell is coupled to the i-th source line and the j-th bit line, where i and j are positive integers, and each memory cell includes a transistor, a first resistor and a second resistor , a first end of the transistor is coupled to the source line corresponding to the memory cell, a second end of the transistor is coupled to the bit line corresponding to the memory cell, the first resistor A first end of the transistor is coupled to the first end of the transistor, a second end of the first resistor is coupled to a third end [gate] of the transistor, and a second end of the second resistor The first end is coupled to the third end of the transistor, and a second end of the second resistor is coupled to the second end of the transistor. The memory chip of claim 1, wherein for each of the memory cells, during a read operation, a bias voltage is applied to the bit line corresponding to the memory cell, to the bit line corresponding to the memory cell The source line is referenced to ground. When a current flowing through the transistor is greater than a reference current value, it is determined that the memory cell stores a first value. When a current flowing through the transistor is less than a reference current value, It is judged that the memory cell stores a second value. The memory chip of claim 2, wherein the reference current value is determined according to a relationship between the gate voltage and the drain current of the transistor. The memory chip of claim 2, wherein the bias voltage is twice a threshold voltage of the transistor. The memory chip of claim 2, wherein the bias voltage is dynamically adjusted according to a temperature of the memory chip. The memory chip of claim 1, wherein for each of the memory cells, in the IC layout structure of the memory cell, the first resistor and the second resistor are disposed between a first metal layer above and below a second metal layer. The memory chip of claim 1, wherein each of the memory cells further comprises a diode, and the first end of the transistor is coupled to the source line and the first resistor through the diode the first end of the device. The memory chip of claim 1, wherein one or more of the memory cells are judged to be unreliable and not used, and for each of the memory cells, performing a plurality of read operations is equivalent to that of the memory cells. During the reading operation, a current flowing through the first end of the transistor in the memory cell is not all larger than a reference current value or not all smaller than the reference current value, so that the memory cell is judged to be unreliable. The memory chip of claim 1, wherein one or more of the memory cells are judged to be unreliable and not used, and for each of the memory cells, performing a plurality of read operations is equivalent to that of the memory cells. In the read operation, a current flowing through the first end of the transistor in the memory cell is not all outside a range formed by an upper limit value of a reference current value and a lower limit value of the reference current value, and determine the Memory cells are unreliable. The memory chip of claim 1, wherein for each of the memory cells, the resistance values between the first resistor and the second resistor have a proportional relationship, and the proportional relationships of the memory cells are: not fixed.

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