TWI759703B - Circuit layout structure and memory storage device - Google Patents

Abstract

A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.

Description

Circuit layout structure and memory storage device

The present invention relates to a circuit layout technique, and more particularly, to a circuit layout structure and a memory storage device.

In some types of volatile memory layouts, clock signal lines, command address signal lines, and clock enable signal lines are all routed in a fly-by topology. For example, in a fly-by topology, the clock signal line, the command address signal line, and the clock enable signal line can pass through multiple volatile memory modules respectively, so as to control all the volatile memory modules in the signal transmission path at the same time. memory module. However, such a wiring method may cause signal transmission errors between different volatile memory modules because the signal transmission path is too long.

The present invention provides a circuit layout structure and a memory storage device, which can reduce the signal transmission error between different volatile memory modules.

An exemplary embodiment of the present invention provides a circuit layout structure including a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, and a first clock The enable signal line and the second clock enable signal line. The first data line is coupled to the plurality of first volatile memory modules to access at least one of the plurality of first volatile memory modules through a first consecutive bit group . The second data line is coupled to the plurality of second volatile memory modules to access at least one of the plurality of second volatile memory modules through a second group of consecutive bits . The first clock enable signal line is coupled to the plurality of first volatile memory modules to control the plurality of first volatile memory modules to enter a self-refresh mode in parallel. The second clock enable signal line is coupled to the plurality of second volatile memory modules to control the plurality of second volatile memory modules to enter the self-update mode in parallel.

In an exemplary embodiment of the present invention, the circuit layout structure further includes at least one clock signal line and an instruction address signal line. The at least one clock signal line is coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules. The command address signal line is coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a rewritable non-volatile memory module, a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first A data line, a second data line, a first clock enable signal line, a second clock enable signal line and a memory control circuit unit. The first data line is coupled to the plurality of first volatile memory modules for A contiguous group of bits accesses at least one of the plurality of first volatile memory modules. The second data line is coupled to the plurality of second volatile memory modules to access at least one of the plurality of second volatile memory modules through a second group of consecutive bits . The first clock enable signal line is coupled to the plurality of first volatile memory modules to control the plurality of first volatile memory modules to enter the self-update mode in parallel. The second clock enable signal line is coupled to the plurality of second volatile memory modules to control the plurality of second volatile memory modules to enter the self-update mode in parallel. The memory control circuit unit is coupled to the rewritable non-volatile memory module, the first data line, the second data line, the first clock enable signal line and the The second clock enable signal line.

In an exemplary embodiment of the present invention, the plurality of first volatile memory modules are not controlled by the second clock enable signal line, and the plurality of second volatile memory modules are not Controlled by the first clock enable signal line.

In an exemplary embodiment of the present invention, the first contiguous group of bits includes a plurality of contiguous first data bits transmitted via the first data line, and the second contiguous group of bits includes A plurality of consecutive second data bits transmitted via the second data line.

In an exemplary embodiment of the present invention, when the plurality of first volatile memory modules enter the self-refresh mode, the first clock enable signal line is at a low voltage level. When the plurality of second volatile memory modules enter the self-refresh mode, the second clock enable signal line is at the low voltage level.

In an exemplary embodiment of the present invention, the memory storage device is more It includes at least one clock signal line and command address signal line. The at least one clock signal line is coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules. The command address signal line is coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules.

In an exemplary embodiment of the present invention, the at least one clock signal line and the command address signal line are both coupled to a termination impedance circuit.

In an exemplary embodiment of the present invention, neither the first clock-enable signal line nor the second clock-enable signal line is coupled to the termination impedance circuit.

Exemplary embodiments of the present invention further provide a circuit layout structure including a plurality of volatile memory modules and a clock enable signal line. The plurality of volatile memory modules include a plurality of volatile memory modules belonging to the first order and a plurality of volatile memory modules belonging to the second order. At a certain point in time, only a plurality of volatile memory modules belonging to one of the first stage and the second stage are activated. The clock enable signal line is coupled to one of the plurality of volatile memory modules belonging to the first stage and the plurality of volatile memory modules belonging to the second stage one of them.

An exemplary embodiment of the present invention further provides a memory storage device including a rewritable non-volatile memory module, a plurality of volatile memory modules, a clock enable signal line and a memory control circuit unit. The plurality of volatile memory modules include a plurality of volatile memory modules belonging to the first order and a plurality of volatile memory modules belonging to the second order. At a certain point in time, only a plurality of volatile memory modules belonging to one of the first stage and the second stage are activated. the clock enable message The signal line is coupled to one of the plurality of volatile memory modules belonging to the first order and one of the plurality of volatile memory modules belonging to the second order. The memory control circuit unit is coupled to the rewritable non-volatile memory module, the plurality of volatile memory modules and the clock enable signal line.

In an exemplary embodiment of the present invention, the clock enable signal line is not coupled to the termination impedance circuit.

Based on the above, after using the same or similar wiring method between the data line and the volatile memory module to configure the clock-enable signal line, the clock-enable signal line is used for the wiring of the plurality of volatile memory modules. Control can be more precise.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

10: Circuit layout structure

11(1)~11(8), 12(1)~12(8): Volatile memory modules

13: Substrate

131, 132: Surface

201(1)~201(4): Data Line

202(1)~202(4): Clock enable signal line

DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24]: Consecutive bit groups

CKE(0)~CKE(3), CA: Signal

301(1), 301(2): Clock signal line

302: Command address signal line

31: Terminating impedance circuit

CK(0), CK(1): Clock signal

303(1)~303(4): Chip select signal line

50: Memory storage device

51,71: Host system

510: System busbar

511: Processor

512: Random Access Memory

513: read-only memory

514: Data transfer interface

52: Input/output (I/O) devices

60: Motherboard

601: pen drive

602: Memory Card

603: Solid State Drive

604: Wireless Memory Storage Device

605: GPS Module

606: Network Interface Card

607: Wireless Transmission Device

608: Keyboard

609: Screen

610: Horn

72: SD card

73: CF card

74: Embedded storage device

741: Embedded Multimedia Card

742: Embedded Multi-Chip Package Storage Devices

801: Connection interface unit

802: Memory control circuit unit

803: Rewritable non-volatile memory module

804: Volatile Memory Module

FIG. 1 is a schematic appearance diagram of a circuit layout structure according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a line coupling relationship among data lines, clock enable signal lines, and volatile memory modules according to an exemplary embodiment of the present invention.

FIG. 3A is a schematic diagram illustrating a line coupling relationship among a clock signal line, a command address signal line, and a volatile memory module according to an exemplary embodiment of the present invention.

FIG. 3B is a chip select signal according to an exemplary embodiment of the present invention. A schematic diagram of the line coupling relationship between lines and volatile memory modules.

4 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

7 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Several exemplary embodiments are presented below to illustrate the present invention, however, the present invention is not limited to the illustrated exemplary embodiments. Appropriate combinations are also permitted between the exemplary embodiments. The term "coupled" as used throughout this specification (including the scope of the claims) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or some connection means. Indirectly connected to the second device. Additionally, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

FIG. 1 is a schematic appearance diagram (ie, a side view) of a circuit layout structure according to an exemplary embodiment of the present invention. Referring to FIG. 1, the circuit layout structure 10 includes volatile memory modules 11(1)-11(8), volatile memory modules 12(1)-12(8) and Substrate 13 . Each of the volatile memory modules 11(1)-11(8) and 12(1)-12(8) may include a plurality of volatile memory cells. For example, when powered on, each memory cell can be used to store one or more bits. After the power is turned off, the data stored in the memory unit will disappear.

In an exemplary embodiment, each of the volatile memory modules 11(1)-11(8) and 12(1)-12(8) may include a rank or Management unit for other memory cells. Taking a stage as an example, at a single point in time, only volatile memory modules belonging to the same stage are allowed to operate. Taking FIG. 2 as an example, it is assumed that the volatile memory modules 11(1), 11(3), 11(5) and 11(7) belong to the same rank (for example, the first rank, marked as Rank1), the volatile memory The bulk modules 11(2), 11(4), 11(6), and 11(8) belong to the same rank (for example, the second rank, marked as Rank2), and the volatile memory modules 12(1), 12( 3), 12(5) and 12(7) belong to the same rank (for example, the third rank, marked as Rank3), and the volatile memory modules 12(2), 12(4), 12(6) and 12 (8) belong to the same order (for example, the fourth order, marked as Rank4). At a certain point of time, there are only a plurality of volatile memory modules belonging to one of the first to fourth orders (for example, the volatile memory modules 11(1) and 11(3) belonging to the first order , 11(5) and 11(7) or the volatile memory modules 11(2), 11(4), 11(6) and 11(8) belonging to the second order can be accessed in parallel. In an exemplary embodiment, a chip select (CS) signal and a control command can be used to select a volatile memory module belonging to a specific level for data access.

In an exemplary embodiment, the volatile memory modules 11(1)-11(8) and 12(1)-12(8) are dynamic random access Memory, DRAM) as an example. However, in another exemplary embodiment, the volatile memory modules 11(1)-11(8) and 12(1)-12(8) may also include other types of volatile memory modules, such as static Random access memory (Static Random Access Memory, SRAM).

In an exemplary embodiment, the volatile memory modules 11 ( 1 ) to 11 ( 8 ) are arranged side by side on the surface 131 of the substrate 13 , and the volatile memory modules 12 ( 1 ) to 12 ( 8 ) are arranged side by side on the surface 131 of the substrate 13 . Surface 132 of substrate 13 . If one of the surfaces 131 and 132 is regarded as the front surface of the substrate 13 , the other one of the surfaces 131 and 132 can be regarded as the back surface of the substrate 13 .

FIG. 2 is a schematic diagram illustrating a line coupling relationship among data lines, clock enable signal lines, and volatile memory modules according to an exemplary embodiment of the present invention. 1 and FIG. 2, in an exemplary embodiment, the circuit layout structure 10 further includes data lines 201(1)-201(4) and pulse enable signal lines 202(1)-202(4). Data line 201(1) is coupled to volatile memory modules 11(1), 11(2), 12(1), and 12(2) and used for access via contiguous bit group DQ[7:0] At least one of the volatile memory modules 11(1), 11(2), 12(1) and 12(2). For example, contiguous bit group DQ[7:0] contains 8 data bits transmitted via data line 201(1).

Data line 201(2) is coupled to volatile memory modules 11(3), 11(4), 12(3), and 12(4) and used for access via contiguous bit group DQ[15:8] At least one of the volatile memory modules 11(3), 11(4), 12(3) and 12(4). For example, contiguous bit group DQ[15:8] contains 8 data bits transmitted via data line 201(2).

Data line 201(3) is coupled to volatile memory modules 11(5), 11(6), 12(5) and 12(6) and are used to access at least one of the volatile memory modules 11(5), 11(6), 12(5) and 12(6) via the contiguous bit group DQ[23:16] one. For example, contiguous bit group DQ[23:16] contains 8 data bits transmitted via data line 201(3).

Data line 201(4) is coupled to volatile memory modules 11(7), 11(8), 12(7), and 12(8) and used for access via consecutive bit groups DQ[31:24] At least one of the volatile memory modules 11(7), 11(8), 12(7) and 12(8). For example, contiguous bit group DQ[31:24] contains 8 data bits transmitted via data line 201(4).

In an exemplary embodiment, the data lines 201(1)-201(4) may correspond to 4 channels. The memory control circuit unit or the memory controller (not shown) can use the 32 data bits DQ[31:0] to access the volatile memory model in parallel via the data lines 201(1)-201(4). Some volatile memory modules in groups 11(1)~11(8) and 12(1)~12(8). For example, in an exemplary embodiment, the volatile memory modules 11(1), 11(3), 11(5), and 11(7) belonging to the first stage can pass through the data lines 201(1)-201( 4) and are accessed in parallel.

The same or similar to the data line 201(1), the clock enable signal line 202(1) is also coupled to the volatile memory modules 11(1), 11(2), 12(1) and 12(2) The volatile memory modules 11(1), 11(2), 12(1) and 12(2) are controlled to enter the self-refresh mode in parallel. For example, when the volatile memory modules 11(1), 11(2), 12(1) and 12(2) enter the self-refresh mode, the signal CKE ( 0) will be at the low voltage level. In addition, the volatile memory modules 11(3)-11(8) and 12(3)-12(8) are not controlled by the clock enable signal line 202(1).

The same or similar to the data line 201(2), the clock enable signal line 202(2) is also coupled to the volatile memory modules 11(3), 11(4), 12(3) and 12(4) to control volatilization The sexual memory modules 11(3), 11(4), 12(3) and 12(4) enter the self-update mode in parallel. For example, when the volatile memory modules 11(3), 11(4), 12(3) and 12(4) enter the self-refresh mode, the signal CKE ( 1) will be at low voltage level. In addition, the volatile memory modules 11(1), 11(2), 11(5)~11(8) and 12(1), 12(2), 12(5)~12(8) are not subject to The pulse enable signal line 202(2) controls.

The same or similar to the data line 201(3), the clock enable signal line 202(3) is also coupled to the volatile memory modules 11(5), 11(6), 12(5) and 12(6) The volatile memory modules 11(5), 11(6), 12(5) and 12(6) are controlled to enter the self-update mode in parallel. For example, when the volatile memory modules 11(5), 11(6), 12(5) and 12(6) enter the self-refresh mode, the signal CKE ( 2) will be at low voltage level. In addition, the volatile memory modules 11(1)~11(4), 11(7), 11(8) and 12(1)~12(4), 12(7), 12(8) are not subject to The pulse enable signal line 202(3) controls.

The same or similar to the data line 201(4), the clock enable signal line 202(4) is also coupled to the volatile memory modules 11(7), 11(8), 12(7) and 12(8) The volatile memory modules 11(7), 11(8), 12(7) and 12(8) are controlled to enter the self-update mode in parallel. For example, when the volatile memory modules 11(7), 11(8), 12(7) and 12(8) enter the self-refresh mode, the signal CKE ( 3) will be at low voltage level. In addition, the volatile memory modules 11(1)-11(6) and 12(1)-12(6) are not controlled by the clock enable signal line 202(4).

In an exemplary embodiment, a plurality of volatile memory modules entering the self-refresh mode in parallel may mean that the plurality of volatile memory modules enter the self-refresh mode at the same time or that the plurality of volatile memory modules approach to enter the self-refresh mode at the same time Self-renewal mode. exist In an exemplary embodiment, the memory control circuit unit or the memory controller (not shown) may enable the signals CKE(0)˜CKE(3) transmitted by the clock enable signal lines 202(1)˜202(4). ) are controlled at a low voltage level, so that the volatile memory modules 11(1)-11(8) and 12(1)-12(8) enter the self-refresh mode at the same time.

In an exemplary embodiment, in a self-update mode, the volatile memory module can maintain and/or update the data it stores. In an exemplary embodiment, when the memory storage device (not shown) including the circuit layout structure 10 enters a power saving mode or a sleep mode, the memory control circuit unit or the memory controller (not shown) may instruct the volatilization The memory modules 11(1)~11(8) and 12(1)~12(8) simultaneously enter the self-update mode.

FIG. 3A is a schematic diagram illustrating a line coupling relationship among a clock signal line, a command address signal line, and a volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 1 and FIG. 3A , in an exemplary embodiment, the circuit layout structure 10 further includes a clock signal line 301 ( 1 ), a clock signal line 301 ( 2 ) and an instruction address signal line 302 . The clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302 are all connected by a fly-by coupling method (also called a fly-by topology) to connect the volatile Memory modules 11(1)~11(8) and 12(1)~12(8). For example, the clock signal line 301(1) is connected to the volatile memory modules 11(1)-11(8) in a fly-by coupling manner to transmit the clock signal CK(0) to the volatile memory Body modules 11(1)~11(8). For example, the clock signal line 301(2) is connected to the volatile memory modules 12(1)-12(8) in a fly-by manner to transmit the clock signal CK(1) to the volatile memory Body modules 12(1)~12(8). For example, the command address signal line 302 is The fly-by coupling method is connected to the volatile memory modules 11(1)~11(8) and 12(1)~12(8) at the same time, so as to convey the access address and/or the access command The signal CA of the volatile memory module 11(1)~11(8) and 12(1)~12(8).

In an exemplary embodiment, one end of the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302 can be coupled to the memory control circuit unit or the memory controller (not shown). shown), while the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302 span the volatile memory modules 11(1)~11(8) and 12(1)~ The other end of 12 ( 8 ) can be coupled to the terminating impedance circuit 31 . The termination impedance circuit 31 may be additionally coupled to the power supply VDD/2. The termination impedance circuit 31 may include at least one impedance element (eg, a resistor) to provide termination impedance to the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302. The termination impedance can make the signals transmitted by the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302 more stable (eg, reduce signal error).

In an exemplary embodiment, the circuit layout structure 10 of FIG. 1 may simultaneously include the data lines 201( 1 ) to 201( 4 ) and the clock enable signal lines 202( 1 ) to 202( 4 in FIGS. 2 and 3A . ), the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302. For the layout structure of these lines, reference may be made to the exemplary embodiments of FIG. 2 and FIG. 3A , and details are not repeated here.

In an exemplary embodiment, the memory control circuit unit or the memory controller (not shown) may send a signal CA with an instruction to enter the self-refresh mode and enable the clock signal lines 202(1)~202( 4) The transmitted signals CKE(0)~CKE(3) are all controlled at low voltage level. When the volatile memory modules 11(1)~11(8) and 12(1)~12(8) are connected The volatile memory module 11(1) receives the signal CA with the instruction to enter the self-refresh mode and simultaneously detects that the clock enable signal lines 202(1)~202(4) are at the low voltage level. ~11(8) and 12(1)~12(8) can enter self-update mode.

In an exemplary embodiment in conjunction with FIG. 2 and FIG. 3 , the clock signal line 301(1), the clock signal line 301(2) and the command address signal line 302 can be coupled to the termination impedance circuit 31 to improve the The stability of the transmitted signal. However, it should be noted that the clock enable signal lines 202(1)-202(4) are not coupled to the termination impedance circuit 31 to avoid leakage current when the voltage is at a low level. In addition, the clock enable signal lines 202( 1 ) to 202( 4 ) are not coupled to the termination impedance circuit 31 to achieve the effect of power saving.

From another perspective, in the exemplary embodiment of FIG. 2 , the clock enable signal lines 202(1)-202(4) are in the same or similar manner as the data lines 201(1)-201(4). To be coupled to the volatile memory modules 11(1)~11(8) and 12(1)~12(8), instead of using the fly-by coupling method. Therefore, even if it is not coupled to the termination impedance circuit 31, the signal quality of the signals transmitted by the clock enable signal lines 202(1)-202(4) can be maintained stable.

FIG. 3B is a schematic diagram illustrating the line coupling relationship between the chip select signal line and the volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 1 and FIG. 3B , in an exemplary embodiment, the circuit layout structure 10 further includes chip selection signal lines 303( 1 ) to 303( 4 ) for transmitting chip selection signals. The chip selection signal lines 303(1)-303(4) are respectively coupled to the volatile memory modules belonging to the first stage to the fourth stage.

In an exemplary embodiment, one of the chip select signal lines 303(1)-303(4) is The terminal can be coupled to a memory control circuit unit or a memory controller (not shown). The other ends of the chip select signal lines 303(1)-303(4) may not be coupled to the termination impedance (eg, the termination impedance circuit 31 in FIG. 3A).

At a single point in time, the memory control circuit unit or the memory controller (not shown) can send the chip selection signal to the chips belonging to the first to the second stage through one of the chip selection signal lines 303(1)-303(4). One of the four tiers of volatile memory modules to select and/or enable specific volatile memory modules. For example, at a certain point in time, the chip select signal line 303(1) may transmit the chip select signal to the volatile memory modules 11(1), 11(3), 11(5) and 11( 7), so that the volatile memory modules 11(1), 11(3), 11(5), and 11(7) start to operate (eg, access data).

In an exemplary embodiment, the circuit layout structure 10 of FIG. 1 may simultaneously include the data lines 201( 1 ) to 201( 4 ) and the clock enable signal lines 202( 1 ) to 202( 1 ) to 3B in FIGS. 2 , 3A and 3B 202(4), clock signal line 301(1), clock signal line 301(2), command address signal line 302 and chip select signal line 303(1)~303(4). For the layout structure of these lines, reference may be made to the exemplary embodiments of FIG. 2 , FIG. 3A and FIG. 3B , and details are not repeated here.

It should be noted that, in the exemplary embodiment of FIG. 1 to FIG. 3 , the total number of volatile memory modules 11(1)-11(8) and the volatile memory modules 12(1)-12(8) total number of data lines 201(1)~201(4), total number of clock enable signal lines 202(1)~202(4) and total number of chip select signal lines 303(1)~303(4) All can be more or less, and the present invention is not limited. In addition, the total number of volatile memory modules ( For example 4) can also be more or less, the present invention does not be restricted.

In an exemplary embodiment, the circuit layout structure 10 of FIG. 1 may be provided in a memory storage device. Generally, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

4 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 4 and FIG. 5 , the host system 51 generally includes a processor 511 , a random access memory (RAM) 512 , a read only memory (ROM) 513 and a data transmission interface 514 . The processor 511 , the random access memory 512 , the ROM 513 and the data transmission interface 514 are all coupled to a system bus 510 .

In this exemplary embodiment, the host system 51 is coupled to the memory storage device 50 through the data transmission interface 514 . For example, the host system 51 may store data to or read data from the memory storage device 50 via the data transfer interface 514 . In addition, the host system 51 is coupled to the I/O device 52 through the system bus 510 . For example, host system 51 may transmit output signals to and receive input signals from I/O device 52 via system bus 510 .

In an exemplary embodiment, the processor 511 , the random access memory 512 , the ROM 513 and the data transmission interface 514 may be disposed on the motherboard 60 of the host system 51 . The number of data transfer interfaces 514 may be one or more. Through the data transfer interface 514 , the motherboard 60 can be coupled to the memory storage device 50 via wired or wireless means. The memory storage device 50 can be, for example, a flash drive 601 , a memory card 602 , a solid state drive (SSD) 603 or a wireless memory storage device 604 . The wireless memory storage device 604 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory device. A storage device (eg, iBeacon) is a memory storage device based on various wireless communication technologies. In addition, the motherboard 60 can also be coupled to the global positioning system (GPS) module 605 , the network interface card 606 , the wireless transmission device 607 , the keyboard 608 , the screen 609 , the speaker 610 , etc. through the system bus 510 . Type I/O device. For example, in an exemplary embodiment, the motherboard 60 can access the wireless memory storage device 604 through the wireless transmission device 607 .

In an exemplary embodiment, the referenced host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 6 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 6 , in another exemplary embodiment, the host system 71 may also be a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 70 may be the Secure digits used Various non-volatile memory storage devices such as Digital, SD) card 72, Compact Flash (Compact Flash, CF) card 73 or embedded storage device 74. The embedded storage device 74 includes various types such as an embedded Multi Media Card (eMMC) 741 and/or an embedded Multi Chip Package (eMCP) storage device 742 to directly couple the memory module to the memory module. Embedded storage on the substrate of the host system.

7 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 7 , the memory storage device 80 includes a connection interface unit 801 , a memory control circuit unit (also referred to as a memory controller) 802 , a rewritable non-volatile memory module 803 and a volatile memory module 804. For example, the volatile memory module 804 may include the volatile memory modules 11( 1 ) to 11( 8 ) and 12( 1 ) to 12( 8 ) in FIGS. 1 to 3 .

In an exemplary embodiment, the connection interface unit 801 , the memory control circuit unit 802 , the rewritable non-volatile memory module 803 and the volatile memory module 804 can all be disposed on the substrate 13 of FIG. 1 . The memory control circuit unit 802 can pass through the data lines 201(1) to 201(4), the clock enable signal lines 202(1) to 202(4), the clock signal line 301(1), and the clock signal line 301 (2) and the command address signal line 302 to control or access the volatile memory modules 11(1)-11(8) and 12(1)-12(8).

The connection interface unit 801 is used for coupling the memory storage device 80 to the host system. In this exemplary embodiment, the connection interface unit 801 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 801 may also be a symbol Combined with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Peripheral Component Interconnect Express (PCI Express) standard, the general serial Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, integrated drive electronics Interface (Integrated Device Electronics, IDE) standard or other suitable standards. The connection interface unit 801 and the memory control circuit unit 802 may be packaged in a chip, or the connection interface unit 801 may be arranged outside a chip including the memory control circuit unit 802 .

The memory control circuit unit 802 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type and write data in the rewritable non-volatile memory module 803 according to the instructions of the host system access, read, and erase operations.

The rewritable non-volatile memory module 803 is coupled to the memory control circuit unit 802 and used to store the data written by the host system. The rewritable non-volatile memory module 803 may be a single-level cell (SLC) NAND type flash memory module (ie, a flash memory that can store 1 bit in one memory cell). module), Multi Level Cell (MLC) NAND type Flash memory modules (ie, a flash memory module that can store 2 bits in one memory cell), Triple Level Cell (TLC) NAND-type flash memory modules (ie, Flash memory modules that can store 3 bits in one memory cell), Quad Level Cell (QLC) NAND-type flash memory modules (that is, 4 bits can be stored in one memory cell) flash memory modules), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 803 stores one or more bits by changing the voltage (also referred to as the threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 803 constitute a plurality of physical programming units, and these physical programming units constitute a plurality of physical erasing units. Specifically, memory cells on the same word line form one or more physical programming units. If each memory cell can store more than two bits, the physical programming unit on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, a memory cell has the lowest The Least Significant Bit (LSB) belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the physical programming unit.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit in which data is written. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming unit is a physical page, the physical programming unit usually includes a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit region may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

To sum up, after using the same or similar wiring method between the data line and the volatile memory module to configure the clock-enable signal line, the clock-enable signal line is used for a plurality of volatile memory modules. Group control can be more precise. In addition, even if the clock The enable signal line is not connected to the termination impedance circuit, and the stability of the signal on the clock enable signal line can also be maintained.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

11(1)~11(8), 12(1)~12(8): Volatile memory modules

13: Substrate

131, 132: Surface

201(1)~201(4): Data Line

202(1)~202(4): Clock enable signal line

DQ[7:0], DQ[15:8], DQ[23:16], DQ[31:24]: Consecutive bit groups

CKE(0)~CKE(3): Signal

Claims (18)

A circuit layout structure includes: a plurality of first volatile memory modules, wherein the plurality of first volatile memory modules belong to different stages; a plurality of second volatile memory modules, wherein the plurality of first volatile memory modules The two volatile memory modules also belong to different levels; a first data line is coupled to the plurality of first volatile memory modules to access the plurality of first volatile memory modules through a first consecutive bit group at least one of the volatile memory modules, and the first data line does not cross the plurality of first volatile memory modules; a second data line is coupled to the plurality of second volatile memory modules a module to access at least one of the plurality of second volatile memory modules through a second consecutive bit group, and the second data line does not span the plurality of second volatile memory modules set; a first clock enable signal line coupled to the plurality of first volatile memory modules to control the plurality of first volatile memory modules to enter a self-update mode in parallel; and a second The clock enable signal line is coupled to the plurality of second volatile memory modules to control the plurality of second volatile memory modules to enter the self-refresh mode in parallel. The circuit layout structure of claim 1, wherein the plurality of first volatile memory modules are not controlled by the second clock enable signal line, and the plurality of second volatile memory modules are not The first clock enables signal line control. The circuit layout structure of claim 1, wherein the first contiguous bit group includes a plurality of contiguous first data bits transmitted via the first data line, and the second contiguous bit group includes via A plurality of consecutive second data bits transmitted by the second data line. The circuit layout structure of claim 1, wherein when the plurality of first volatile memory modules enter the self-refresh mode, the first clock enable signal line is at a low voltage level, and when the plurality of first volatile memory modules enter the self-refresh mode When the plurality of second volatile memory modules enter the self-refresh mode, the second clock enable signal line is at the low voltage level. The circuit layout structure of claim 1, further comprising: at least one clock signal line coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules; and an instruction The address signal lines are coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules. The circuit layout structure of claim 5, wherein the at least one clock signal line and the command address signal line are both coupled to a terminating impedance circuit. The circuit layout structure of claim 6, wherein neither the first clock-enable signal line nor the second clock-enable signal line is coupled to the termination impedance circuit. A memory storage device, comprising: a rewritable non-volatile memory module; a plurality of first volatile memory modules, wherein the plurality of first volatile memory modules belong to different stages; a plurality of second volatile memory modules, wherein the plurality of second volatile memory modules also belong to different stages; a first data line is coupled to the plurality of first volatile memory modules for at least one of the plurality of first volatile memory modules is accessed by a first continuous bit group, and the first data line does not cross the plurality of first volatile memory modules; a first two data lines coupled to the plurality of second volatile memory modules to access at least one of the plurality of second volatile memory modules through a second consecutive bit group, and the The second data line does not cross the plurality of second volatile memory modules; a first clock enable signal line is coupled to the plurality of first volatile memory modules to control the plurality of first volatile memory modules The volatile memory modules enter a self-update mode in parallel; a second clock enable signal line is coupled to the plurality of second volatile memory modules to control the plurality of second volatile memory modules in parallel entering the self-update mode; and a memory control circuit unit coupled to the rewritable non-volatile memory module, the first data line, the second data line, and the first clock enable signal line and the second clock enable signal line. The memory storage device of claim 8, wherein the plurality of first volatile memory modules are not controlled by the second clock enable signal line, and the plurality of second volatile memory modules are not Controlled by the first clock enable signal line. The memory storage device of claim 8, wherein the first group of consecutive bits includes a plurality of consecutive first data transmitted via the first data line bits, and the second group of consecutive bits includes a plurality of consecutive second data bits transmitted through the second data line. The memory storage device of claim 8, wherein when the plurality of first volatile memory modules enter the self-refresh mode, the first clock enable signal line is at a low voltage level, and when the plurality of first volatile memory modules enter the self-refresh mode When the plurality of second volatile memory modules enter the self-refresh mode, the second clock enable signal line is at the low voltage level. The memory storage device of claim 8, further comprising: at least one clock signal line coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules; and a The command address signal line is coupled to the plurality of first volatile memory modules and the plurality of second volatile memory modules. The memory storage device of claim 12, wherein the at least one clock signal line and the command address signal line are both coupled to a termination impedance circuit. The memory storage device of claim 13, wherein neither the first clock-enable signal line nor the second clock-enable signal line is coupled to the termination impedance circuit. A circuit layout structure includes: a plurality of volatile memory modules, wherein the plurality of volatile memory modules include a plurality of volatile memory modules belonging to a first stage and a plurality of volatile memory modules belonging to a second stage For a volatile memory module, at a specific time point, only a plurality of volatile memory modules belonging to one of the first stage and the second stage are activated; a clock enable signal line coupled to one of the plurality of volatile memory modules belonging to the first stage and one of the plurality of volatile memory modules belonging to the second stage; and a data line coupled to the one of the plurality of volatile memory modules belonging to the first stage and the one of the plurality of volatile memory modules belonging to the second stage, Wherein the data line does not cross the one of the volatile memory modules belonging to the first order and the one of the volatile memory modules belonging to the second order. The circuit layout structure of claim 15, wherein the clock enable signal line is not coupled to a terminating impedance circuit. A memory storage device includes: a rewritable non-volatile memory module; a plurality of volatile memory modules, including a plurality of volatile memory modules belonging to a first stage and a plurality of volatile memory modules belonging to a second stage of the plurality of volatile memory modules, wherein at a specific time point, only the plurality of volatile memory modules belonging to one of the first stage and the second stage actuate; a clock enable signal line, coupled to one of the plurality of volatile memory modules belonging to the first stage and one of the plurality of volatile memory modules belonging to the second stage; a data line coupled to the one of the plurality of volatile memory modules belonging to the first order and the other of the plurality of volatile memory modules belonging to the second order one of, wherein the data line does not span the one of the plurality of volatile memory modules belonging to the first order and the one of the plurality of volatile memory modules belonging to the second order 1; and a memory control circuit unit coupled to the rewritable non-volatile memory module, the plurality of volatile memory modules and the clock enabling signal line. The memory storage device of claim 17, wherein the clock enable signal line is not coupled to a terminating impedance circuit.

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