TWI688079B - Non-volatile memory device and method for manufacturing the same - Google Patents

Abstract

A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first poly silicon layer, a second poly silicon layer, and nitrogen dopant. A grain of the first poly silicon layer has a first grain size, and a grain of the second poly silicon layer has a second grain size greater than the first grain size. The nitrogen dopant is formed in an interstice between the grains of the first poly silicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.

Description

Non-volatile memory device and manufacturing method thereof

The present invention relates to a memory device, and particularly relates to a non-volatile memory device and a manufacturing method thereof.

In non-volatile memory, according to whether the data in the memory can be rewritten at any time when using the computer, it can be divided into two major categories of products, namely read-only memory (read-only memory, ROM) and flash memory. Among them, flash memory has gradually become the mainstream technology of non-volatile memory due to its low cost.

The floating gate of the existing flash memory includes a doped polysilicon layer. The grain size in the doped polysilicon layer is easily affected by the subsequent high temperature process. However, the larger the grain size in contact with the tunneling oxide layer, the more easily the dopants in the polysilicon layer will gather at the interface in contact with the tunneling oxide layer, which will result in abnormal conductivity in some areas Localization, thereby causing over programming and/or over erasing problems.

The so-called "over-programming" means that when no voltage is applied, electrons will still move from the substrate through the tunnel oxide layer to the floating gate. On the other hand, so-called "over-erase" means that when no voltage is applied, electrons will still move from the floating gate through the tunnel oxide layer to the substrate. When regions with high conductivity are generated at the interface between the floating gate and the tunnel oxide layer, these regions are very prone to over-programming and/or over-erasing. Both over-programming and over-erasing can cause errors in the operation of non-volatile memory devices. In addition, if over-programming and over-erasing occur, after the durability test, the threshold voltage of the flash memory will have a greater variation, so good reliability and durability cannot be obtained.

With the trend of miniaturization of electronic products, there is also a demand for miniaturization of non-volatile memory devices. Moreover, the reliability and durability problems of existing non-volatile memory devices will become more serious in the miniaturized design. Therefore, there is still a need for non-volatile memory devices with high durability, high reliability and high product yield.

An embodiment of the invention discloses a non-volatile memory device including: a tunneling oxide layer formed on a substrate; a floating gate formed on the tunneling oxide layer, wherein the floating gate includes: a first The polysilicon layer includes a plurality of first polysilicon grains having a first grain size; the second polysilicon layer is formed on the first polysilicon layer and includes a plurality of grains having a second grain size A second polysilicon grain, wherein the second grain size is larger than the first grain size, and wherein the second polysilicon layer includes dopants; and the nitrogen dopant is formed in the first polysilicon layer and is located in the first A gap between polysilicon crystal grains; a dielectric layer formed on the floating gate, wherein the dielectric layer includes: a first nitride film formed compliantly and covering the floating gate; and an oxide layer/ The nitride layer/oxide layer structure is conformally formed on the first nitride film; and the control gate is formed on the dielectric layer.

Another embodiment of the present invention discloses a method for manufacturing a non-volatile memory device, including: forming a tunneling oxide layer on a substrate; forming a floating gate on the tunneling oxide layer, wherein forming the floating gate includes : Perform a first deposition process to form a first polysilicon layer on the tunneling oxide layer, wherein the first polysilicon layer is an undoped polysilicon layer; perform an ion implantation process to include N ₂ Impurities are implanted on the surface of the first polysilicon layer; a second deposition process is performed to form a second polysilicon layer on the first polysilicon layer, wherein the second polysilicon layer is doped A polysilicon layer; and performing a heat treatment process to form a plurality of first polysilicon grains having a first grain size in the first polysilicon layer, and a plurality of first polysilicon grains having a first grain size in the second polysilicon layer A second polycrystalline silicon grain of two grain sizes, wherein the second grain size is larger than the first grain size; forming a dielectric layer on the floating gate; and forming a control gate on the dielectric layer.

100‧‧‧ Non-volatile memory device

102‧‧‧ substrate

104‧‧‧Tunnel oxide layer

110‧‧‧The first polysilicon layer

112‧‧‧N ₂ doped thin layer

115‧‧‧Ion implantation process

120‧‧‧Second polysilicon layer

121‧‧‧The first groove

122‧‧‧Isolated structure

123‧‧‧Second groove

131‧‧‧ First nitride film

132‧‧‧ oxide layer

133‧‧‧Nitride layer

134‧‧‧ oxide layer

135‧‧‧Second nitride film

140‧‧‧ polysilicon material

150‧‧‧The third polysilicon layer

D1, D2‧‧‧Depth

△D‧‧‧Depth difference

T1, T2‧‧‧thickness

W1‧‧‧Width

FIGS. 1A to 1G are schematic cross-sectional views of manufacturing processes of non-volatile memory devices according to some embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view of a non-volatile memory device according to other embodiments of the invention.

Figures 3A and 3B illustrate the experimental results of the dopant concentration distribution of the non-volatile memory devices of Test Example (A) and Test Example (B).

FIG. 4 plots the experimental results of the dopant concentration distribution of the non-volatile memory device of Test Example (C).

FIG. 5 shows the experimental results of the difference in threshold voltage of the nonvolatile memory devices of Comparative Example (A) and Example (A).

To make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically described below, and in conjunction with the accompanying drawings, detailed descriptions are as follows. However, anyone with ordinary knowledge in the art will understand that the various characteristic structures in the present invention are for illustration only and are not drawn to scale. In fact, in order to make the description more clear, the relative size ratio of various characteristic structures can be arbitrarily increased or decreased. Furthermore, different reference examples and/or words may be used in different examples of the present invention. These repeated symbols or words are used for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and/or the appearance structures.

Here, the terms "about" and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" and "approximately" can still be implied without specific instructions.

In the following, unless otherwise mentioned, the "%" indicating the content refers to "atomic %" or "ion %". For example, if the content of the X component is 10% and the content of the Y component is 90% in a material or structure, it means that there are 10 Xs in every 100 atoms (or ions) of the material or structure. Atom (or ion), 90 Y atoms (or ion).

The present invention provides a non-volatile memory device and a manufacturing method thereof. FIGS. 1A to 1G are schematic cross-sectional views of a manufacturing process of a non-volatile memory device 100 according to some embodiments of the present invention.

Referring to FIG. 1A, a tunnel oxide layer 104 is formed on the substrate 102. In some implementations, the tunnel oxide layer 104 may be formed by thermal oxidation, but the invention is not limited thereto. The substrate 102 may include an array area and a peripheral circuit area (not shown) adjacent to the array area. To simplify the description, FIGS. 1A to 1G only show schematic cross-sectional views of the array area. The substrate 102 may be a semiconductor substrate. In some embodiments, the material of the substrate 102 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon on insulator (SOI), other suitable materials, or a combination of the foregoing materials. In some embodiments, other structures may be formed in the substrate 102, for example, an N-type well region, a P-type well region, a P/N junction, or an isolation structure.

In some embodiments, after the tunnel oxide layer 104 is formed, the tunnel oxide layer 104 may be subjected to nitrogen plasma treatment if necessary, so that a thin nitride layer is formed on the surface of the tunnel oxide layer 104. Nitrogen plasma is electrically neutral overall, and including various forms of nitrogen, for example: cation _{^{(N +, N 2 +)}} , anions _{^{(N -, N 2 -)}} , a radical _{^{(N *, N 2 *)}} , Neutral N atoms and N ₂ molecules. These forms of nitrogen have the right energy and can produce weak bonds with silicon atoms.

In some embodiments, after the tunnel oxide layer 104 is formed, a high-temperature annealing process may be performed in a nitrogen-containing gas environment as needed. The nitrogen-containing gas may include nitrogen oxides, for example, nitric oxide, nitrogen dioxide, nitrous oxide, nitrous oxide, nitrous oxide, or a combination thereof. The temperature of the annealing process may be 70-1200°C. In some embodiments, after the tunnel oxide layer 104 is formed, a nitrogen plasma treatment may be performed if necessary, and then a high-temperature annealing process is performed in a nitrogen-containing gas environment. Performing the above-mentioned nitrogen plasma treatment and/or the above-mentioned annealing process can help to improve the threshold voltage of the non-volatile memory device 100. This section will be discussed in detail below.

Next, a first deposition process is performed to form a first polysilicon layer 110 with a thickness T1 on the tunnel oxide layer 104. The first deposition process may include a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination of the above processes. In some embodiments, low pressure chemical vapor deposition (LPCVD) may be performed in the furnace tube to form the first polysilicon layer 110.

The first polysilicon layer 110 is an undoped polysilicon layer, which serves as a buffer layer or a barrier layer to prevent the dopant (eg, phosphorus or arsenic) doped from another polysilicon layer deposited subsequently from diffusing into the tunnel The oxide layer 104 affects the electron tunneling effect. Thereby, the threshold voltage of the non-volatile memory device 100 can be improved. If the thickness of the first polysilicon layer 110 is too small, the threshold voltage cannot be significantly improved. On the other hand, since the undoped polysilicon layer has a higher resistance value, if the thickness of the first polysilicon layer 110 is too large, the resistance value of the non-volatile memory device 100 is too high and a higher Operating voltage. As a result, energy consumption will increase and the durability of the device will decrease. Therefore, the thickness of the first polysilicon layer 110 can be controlled within an appropriate range. In some embodiments, the thickness T1 of the first polysilicon layer 110 is 5-40 nm.

Still referring to FIG. 1A, an ion implantation process 115 is performed to implant impurities including N ₂ on the surface of the first polysilicon layer 110. As shown in FIG. 1B, after the ion implantation process 115 is performed, a thin layer 112 doped with N ₂ is formed on the surface of the first polysilicon layer 110. The ion implantation process 115 can use a high content of N ₂ ⁺ ions as an ion source. In some embodiments, the ion implantation process 115 uses N ₂ ⁺ ions with a content of 99% or more as an ion source, thereby helping to improve the threshold voltage of the non-volatile memory device 100 and greatly improve the reliability of the device With durability. In other embodiments, the ion implantation process 115 uses N ₂ ⁺ ions with a content of 99.9% or more or substantially 100% as an ion source. Any suitable method can be used to generate a source of high levels of N ₂ ⁺ ions. For example, nitrogen gas can be ionized in an ionizer to produce ions with different mass/charge ratios (m/e). Next, these ions are separated from each other by an electric field or a magnetic field, and N ₂ ⁺ ions are focused to form an ion beam, which can be used as an ion source for the ion implantation process 115. In one embodiment, when performing the ion implantation process 115, the ion implantation equipment will provide secondary electrons with the same amount of charge to neutralize the positively charged ion beam and then implant it onto the wafer, thereby preventing Positive ions accumulate in the wafer and cause wafer damage. It should be understood that the above method is only for illustration and is not intended to limit the present invention.

Next, as shown in FIG. 1C, a second deposition process is performed to form a second polysilicon layer 120 on the first polysilicon layer 110 and the thin layer 112 doped with N ₂ . In some embodiments, the second polysilicon layer 120 may be a doped polysilicon layer. In some embodiments, the second polysilicon layer 120 may be a polysilicon layer doped with N-type dopants. In some embodiments, the N-type dopant may include phosphorus or arsenic.

The second deposition process may include a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination of the above processes. In some embodiments, the second deposition process may be low-pressure chemical vapor deposition performed in a furnace tube, and the second deposition process may include an in-situ dopping process. In this way, the polysilicon layer can be deposited at the same time and doped in the polysilicon layer to form the doped second polysilicon layer 120. In some embodiments, the field doping process uses phosphine (PH ₃ ) as a doping gas, thereby doping the second polysilicon layer 120 with phosphorus as a dopant.

In some embodiments, the thickness T2 of the second polysilicon layer 120 is 20-200 nm. In a preferred embodiment, the thickness T2 of the second polysilicon layer 120 is greater than the thickness T1 of the first polysilicon layer 110. In a preferred embodiment, the thickness T2 of the second polysilicon layer 120 is at least twice the thickness T1 of the first polysilicon layer 110.

Next, as shown in FIG. 1D first, a first etching process to form the polysilicon layer 120 through the second doped N thin layer _1122, the first polysilicon layer 110, tunnel oxide layer 104 And a plurality of first trenches 121 of the substrate 102. The first etching process may include plasma etching, reactive ion etching, other suitable etching processes, or a combination of the above processes. In some embodiments, in order to form the first trench 121 with a higher aspect ratio, the first etching process uses reactive ion etching.

Referring to FIG. 1E, an insulating material is formed in the first trench 121, and a second etching process is performed to remove part of the insulating material. In this way, the isolation structure 122 is formed in the first trench 121 and the second trench 123 is formed on the isolation structure 122. The isolation structures 122 isolate multiple floating gates from each other. The floating gate includes a first polysilicon layer 110, a second polysilicon layer 120, and nitrogen doping.

FIG. 1E only shows the single-layer isolation structure 122. However, it is understandable that the purpose is only to simplify the description and not to limit the present invention. In other words, the isolation structure 122 may be a single-layer structure or a multi-layer structure. Furthermore, the isolation structure 122 may include silicon nitride, silicon oxide, silicon oxynitride, other suitable insulating materials, or a combination thereof.

Furthermore, before forming the insulating material in the first trench 121, a liner layer (not shown) may be formed on the inner wall of the first trench 121 first. In some embodiments, the oxide liner can be formed by a high temperature thermal oxidation process. In such an embodiment, the high temperature thermal oxidation process causes the second polysilicon layer 120 to include a plurality of second polysilicon grains having a second grain size. And the second grain size is larger than the first grain size of the first polysilicon grains in the first polysilicon layer 110.

It should be noted that the phosphorus dopant present in the second polysilicon layer 120 absorbs the heat energy in the high-temperature process and is easily converted into a gaseous state and out gasing, resulting in a decrease in the concentration of the phosphorus dopant, which leads to The resistance value of the second polysilicon layer 120 rises. On the other hand, since the nitrogen dopant is formed in the first polysilicon layer 110 of the present invention, the resistance value of the first polysilicon layer 110 will increase. Furthermore, when the volume-expanded phosphorus dopant escapes after absorbing heat energy, hill-like protrusions are left on the surface of the second polysilicon layer 120, and an uneven surface is left. As a result, the yield of the product will decrease. Especially for small devices, the impact will be more serious. In order to reduce the overall resistance value of the floating gate, the doping amount of phosphorus dopant can be increased. However, if the doping amount of phosphorus dopant is increased, the above-mentioned protrusion problem will become more serious.

In order to solve the above problem, as shown in FIG. 1F, after the isolation structure 122 is formed, a first nitrogen plasma treatment is performed at room temperature to conformally form the first nitride film 131 on the second polysilicon The layer 120 and the isolation structure 122 are on the surface.

In the present invention, since the process temperature for forming the first nitride film 131 is room temperature, the probability of the phosphorus dopant escaping outward can be significantly reduced. Furthermore, even if the phosphorus dopant escapes, the first nitride film 131 can block the phosphorus dopant escape, leaving most of the phosphorus dopant in the second polysilicon layer 120. Therefore, if the first nitride film 131 is formed, even if the doping amount of the phosphorus dopant is not increased, the resistance value of the second polysilicon layer 120 can be prevented from rising after the high temperature process.

In order to effectively block the escape of phosphorus dopants, the thickness of the first nitride film 131 may be controlled within a specific range. In some embodiments, the thickness of the first nitride film 131 is 1-5Å.

After the first nitride film 131 is formed, a three-layer structure of the oxide layer 132/nitride layer 133/oxide layer 134 is conformally formed on the first nitride film 131. The oxide layer 132/nitride layer 133/oxide layer 134 can be formed using any suitable material or deposition process, such as a high temperature furnace control process. In some embodiments, the oxide layer 132 and the oxide layer 134 may include silicon oxide.

Next, a second nitrogen plasma treatment is performed to conformally form a second nitride film 135 on the surface of the oxide layer 134. The second nitrogen plasma treatment may be the same as or similar to the first nitrogen plasma treatment, and the second nitride film 135 may be the same as or similar to the first nitride film 131, which will not be described in detail here.

In some embodiments, a first nitride film 131 and a second nitride film 135 are formed above and below the oxide layer 132/nitride layer 133/oxide layer 134, respectively, to block the diffusion of phosphorus dopants. Therefore, the second polysilicon layer 120 can maintain a stable resistance value, and can further reduce the variability of the threshold voltage.

Furthermore, the first nitride film 131 and the second nitride film 135 can reduce the equivalent oxide thickness (EOT). Therefore, only a lower voltage is required for programming/erasing. In other words, it is possible to reduce the threshold voltage and improve the durability of the non-volatile memory device.

In addition, the first nitride film 131 and the second nitride film 135 can prevent the tunnel oxide layer 104 from being re-oxidized in the portion of the tunnel oxide layer 104 closer to the edge during subsequent heat treatment, thereby causing the oxide layer to thicken (Also known as Bird's beak), which can make the operating voltage distribution of the non-volatile memory device more uniform.

In order to improve the reliability and durability of the non-volatile memory device, the thickness of the second nitride film 135 may be controlled within a specific range. In some embodiments, the thickness of the second nitride film 135 is 1-5Å.

Next, as shown in FIG. 1G, a polysilicon material 140 is deposited on the dielectric layer and filled into the second trench 123. After the polysilicon material 140 is formed, other conventional processes (for example, patterning the polysilicon material 140 to form a control gate) can be subsequently performed to complete the non-volatile memory device 100. Regarding other conventional manufacturing processes, no more details will be given here.

Referring to FIG. 1G, the non-volatile memory device 100 of the present invention may include a substrate 102, a tunneling oxide layer 104, a floating gate, a dielectric layer, and a control gate. The tunnel oxide layer 104 is disposed on the substrate 102. The floating gate is disposed on the tunneling oxide layer 104, and includes a first polysilicon layer 110, a second polysilicon layer 120, and nitrogen doping. The second polysilicon layer 120 includes dopants. The dielectric layer includes a five-layer structure formed compliantly and covering the floating gate. The five-layer structure includes: a first nitride film 131, an oxide layer 132, a nitride layer 133, an oxide layer 134, and a second nitride film 135. The control gate is arranged on the dielectric layer.

The first polysilicon layer 110 includes a plurality of first polysilicon grains having a first grain size. The second polysilicon layer 120 includes a plurality of second polysilicon grains having a second grain size. The second grain size is larger than the first grain size. Nitrogen dopants are formed in the gaps between the first polysilicon grains of the first polysilicon layer 110.

If the size of the first crystal grain is too large, the gap between the crystal grains in the first polysilicon layer 110 is large, so that the dopants in the second polysilicon layer 120 are likely to accumulate on the first polysilicon layer 110 In the gap between the grains. In this way, the variability of the threshold voltage of the formed non-volatile memory device 100 will be increased, and the reliability and durability of the device will be reduced. In some embodiments, the first grain size is 1-70 nm. In some embodiments, the first grain size is 3-40 nm.

In the present invention, the surface of the first polysilicon layer 110 is doped with non-silicon dopants (for example, nitrogen). Without these dopants, the grains of the first polysilicon layer will combine with the adjacent grains during the subsequent heat treatment process, thus forming grains with larger grain sizes. In contrast, in the present invention, since these dopants exist between the crystal grains, the combination of the crystal grains and other crystal grains in the heat treatment process becomes more difficult, or does not even occur. That is, with the ion implantation process 115 of the present invention, the grain size of the first polysilicon layer 110 can be prevented from being significantly affected by the heat treatment process, thereby making the first grain size smaller than the second grain size.

However, if a general nitrogen plasma is used to dope the surface of the first polysilicon layer 110 with nitrogen dopants, although the grain size of the first polysilicon layer 110 may be prevented from rising due to the heat treatment process, it is not obvious The amount of N-type dopants (for example, phosphorus) in the second polysilicon layer 120 diffused into the first polysilicon layer 110 is reduced. In this case, these phosphorus dopants will accumulate in the gap between the grains of the first polysilicon layer 110 or the gap between the first polysilicon layer 110 and the tunnel oxide layer. Furthermore, the phosphorus dopant diffused into the first polysilicon layer 110 is likely to further diffuse into the substrate 102. As a result, the conductivity of some areas will be abnormally increased, which will cause over-programming and/or over-erasing problems.

After trying various methods, the inventor of the present invention found that the ion implantation process using a high content of N ₂ ⁺ ions as an ion source can effectively improve the above-mentioned problems of over-programming and over-erasing. Therefore, the threshold voltage of the non-volatile memory device 100 can be improved, and the reliability and durability of the device can be greatly improved.

The following explains the reasons why N ₂ ⁺ ions can improve over-programming and over-erasing. N ₂ ⁺ ion is a divalent monovalent cation formed by two nitrogen atoms; on the other hand, N ⁺ ion is a monovalent cation formed by one nitrogen atom. With respect to the N ⁺ ions, N ₂ ⁺ ions of larger mass, and therefore, the first polysilicon layer 110, and after dopant diffusion or movement more difficult ₂ N, and to concentrate on the first polycrystalline The area on the surface of the silicon layer 110, and a film layer containing a high concentration of doped N ₂ (for example, a thin layer 112 doped with N ₂ ) is formed. By the thin layer 112 doped with N ₂ , not only can the grain size of the polysilicon grains of the first polysilicon layer 110 be affected after the heat treatment process, but also the diffusion of phosphorus dopants can be blocked more effectively. In other words, the thin layer 112 doped with N ₂ can greatly reduce the phosphorus dopant entering the first polysilicon layer 110. Therefore, the problems of over-programming and over-erasing can be significantly improved or solved.

In contrast, if the treatment by a nitrogen plasma, and nitrogen-doped polysilicon to a surface of the first layer 110, the plasma form of smaller mass of nitrogen ^{(e.g., N +, N -, N} * And N atoms) will diffuse or move to a deeper position in the first polysilicon layer 110. Therefore, the nitrogen dopant cannot be concentrated on the surface of the first polysilicon layer 110, and the concentration of nitrogen dopant on the surface of the first polysilicon layer 110 is low. As such, the first polysilicon layer 110 has poor ability to block the diffusion of phosphorus dopants, and cannot effectively improve the problems of over-programming and over-erasing.

In order to verify the above, the inventors of the present case conducted experiments, and the results are shown in FIGS. 3A and 3B. Figures 3A and 3B illustrate the dopant concentration distribution of the non-volatile memory devices of Test Example (A) and Test Example (B).

The manufacturing process of Test Example (A) includes: ion implantation using N ⁺ ions as the ion source on the silicon substrate; then depositing a 150 nm polysilicon layer doped with phosphorus on the silicon substrate; then at 1050° C. under nitrogen High temperature annealing process under the environment. The manufacturing process of test case (B) is the same as that of test case (A), the difference is that test case (B) uses N ₂ ⁺ ions as ion sources for ion implantation. Test cases (A) and (B) were analyzed by secondary ion mass spectrometry (SIMS), where the concentration distribution of nitrogen dopants is shown in Figure 3A; the concentration distribution of phosphorus dopants is shown in Figure 3B Figure.

Referring to FIG. 3A, the concentration of nitrogen dopant (N) of Test Example (A) has a peak at a depth of about 150 nm. This means that the doped N is concentrated between the interface between the silicon substrate and the polysilicon layer. However, the nitrogen dopant of Test Example (A) has a severe tailing phenomenon in a region with a depth of about 50-150 nm. This means that the doped N is driven by the stress of the grain growth of the polysilicon layer after heat treatment, so that much of the doped N diffuses into the polysilicon layer. On the other hand, the concentration of nitrogen dopant (N ₂ ) of Test Example (B) has a peak at a depth of about 150 nm, and the concentration of the dopant N ₂ before and after this peak changes very little. This means that the doped N _{2 is} concentrated between the interface between the silicon substrate and the polysilicon layer, and hardly diffuses into the polysilicon layer. In other words, using N ₂ as a nitrogen dopant can avoid the above-mentioned tailing phenomenon.

Please refer to FIG. 3B. At a depth of about 200 nm, the concentration of the phosphorus dopant in Test Example (A) is about 10 ¹⁸ atoms/cm ³ , and the concentration of the phosphorus dopant in Test Example (B) is about 10 ¹⁷ atoms/ cm ³ . That is, the phosphorus dopant concentration of Test Example (A) is about 10 times the phosphorus dopant concentration of Test Example (B). Furthermore, at a depth of about 170-220 nm, the phosphorus dopant concentration of Test Example (A) is significantly higher than that of Test Example (B). This means that the use of N ₂ as a nitrogen dopant can more effectively block the diffusion of phosphorus dopants than N.

It can be seen from the above experimental results that when N ⁺ ions are used as nitrogen dopants in the ion implantation process 115, the nitrogen dopants will be easily attracted by the stress of the growth of polysilicon grains above it, and The above-mentioned nitrogen doping phenomenon occurs in the layer, that is, the nitrogen doping concentration in different depth ranges is significantly uneven. Since nitrogen doping inhibits the growth of polysilicon grains, the higher the nitrogen doping concentration, the smaller the polysilicon grain size. Therefore, the above-mentioned nitrogen-doped tailing phenomenon will make the grain size of the second polysilicon layer non-uniform, that is, increase the variability of the grain size.

In contrast, using N ₂ ⁺ ions for ion implantation can greatly reduce the phosphorus dopant entering the first polysilicon layer 110. Therefore, the above-mentioned over-programming and over-erasing problems can be significantly improved or solved, and thus the threshold voltage of the non-volatile memory device 100 can be improved, and the reliability and durability of the device can be greatly improved.

Furthermore, in order to verify that the doping of the nitrogen dopant in the tunneling oxide layer 104 and the substrate 102 can further block the phosphorus dopant, the inventors of the present application conducted experiments and the results are shown in FIG. 4. FIG. 4 illustrates the doping concentration distribution of the non-volatile memory device of Test Example (C).

The test example (C) includes the structure shown in FIG. 1C, and is produced in accordance with the relevant steps described above in FIGS. 1A to 1C. After forming the tunnel oxide layer 104, the nitrogen plasma treatment and the high temperature annealing process are performed. Figure 4 shows the concentration distribution of nitrogen and phosphorus dopants obtained by analysis of Test Example (C) by secondary ion mass spectrometry. In Fig. 4, the dotted line represents the concentration distribution of nitrogen dopants, and the solid line represents the concentration distribution of phosphorus dopants.

As shown in FIG. 4, the nitrogen dopant concentration distribution includes a first peak P1, a second peak P2, a third peak P3, and a fourth peak P4. The first peak P1 is located in the first polysilicon layer 110. The second peak P2 is located in the substrate 102. The third peak P3 and the fourth peak P4 are located in the second polysilicon layer 120.

Please refer to FIG. 4, the first peak P1 is approximately located on the surface of the first polysilicon layer 110, and the concentration of nitrogen dopant at the first peak P1 is significantly greater than the concentration of nitrogen dopant at the third peak P3. This means that most of the nitrogen-doped N ₂ stays near the interface between the first polysilicon layer 110 and the second polysilicon layer 120, and only a very small amount of nitrogen dopant enters the second polysilicon layer 120. The third peak P3 and the fourth peak P4 are located at different depths in the second polysilicon layer 120. The concentration of nitrogen dopant at the third peak P3 is very close to the concentration of nitrogen dopant at the fourth peak P4. This means that the nitrogen dopant entering the second polysilicon layer 120 does not have the above-mentioned tailing phenomenon.

Please refer to FIG. 4, since the above-mentioned nitrogen plasma treatment and the above-mentioned annealing process are performed, the concentration distribution of nitrogen dopant has a second peak P2 in the substrate 102 and another peak in the tunneling oxide layer 104 (not Marked). The concentration of nitrogen dopant at the second peak P2 is similar to the concentration of nitrogen dopant at the first peak P1.

Still referring to FIG. 4, the concentration distribution of phosphorus dopant in the tunneling oxide layer 104 shows a sharp decrease trend, and it continues to decrease in the substrate 102. This proves that if a high concentration of nitrogen dopant exists in the tunnel oxide layer 104 and the substrate 102, the phosphorus dopant can be further blocked to prevent the phosphorus dopant from entering the tunnel oxide layer 104 and the substrate 102. Therefore, the threshold voltage, reliability, and durability of the nonvolatile memory device 100 can be further improved.

In some embodiments, the concentration of the nitrogen dopant in the non-volatile memory device 100 of the present invention at the third peak P3 is not greater than the concentration at the first peak P1 and the concentration at the second peak P2. Therefore, the above-mentioned problems of over-programming and over-erasing can be improved or solved, and the threshold voltage of the nonvolatile memory device 100 can be improved, and the reliability and durability of the device can be greatly improved.

In some embodiments, the concentration of the nitrogen dopant in the non-volatile memory device 100 of the present invention at the second peak P2 divided by the concentration of the nitrogen dopant at the third peak P3 is between 10 ² and 10 ⁵ . In this way, phosphorus doping can be prevented from entering the tunnel oxide layer 104 and the substrate 102. The first nitride film 131 of the non-volatile memory device 100 of the present invention can be used as a cap layer or a barrier layer to block the escape of the phosphorus dopant in the second polysilicon layer 120 after the high temperature process. In some embodiments, the nitrogen concentration of the first nitride film is 10 ²¹ -10 ²³ atoms/cm ³ . In some embodiments, the concentration of phosphorus dopant in the second polysilicon layer 120 is 10 ²⁰ -10 ²² atoms/cm ³ .

In some embodiments, the concentration of nitrogen dopant at the fourth peak P4 of the non-volatile memory device 100 of the present invention divided by the concentration of nitrogen dopant at the third peak P3 is not greater than 1. Thereby, the uniformity of the grain size of the second polysilicon layer is improved.

For different floating gates, the concentration (or number) of the gaps between the first polysilicon grains may be different, which may result in different concentrations of nitrogen dopants, and thus different resistance values. For example, if the grain size of the first polysilicon is larger than the width of the floating gate, there may be no gaps between the grains in the first polysilicon layer 110 of some floating gates. Such a floating gate will have a lower nitrogen doping concentration and a lower resistance value. In other words, these floating gates may have uncontrollable differences. As a result, the yield and reliability of the non-volatile memory device 100 will be reduced. With the miniaturization of memory devices, this problem will become more serious.

In order to improve the above problems, the non-volatile memory device 100 of the present invention can control the relative relationship between the first die size and the width of the floating gate as needed. As shown in FIG. 1G, W1 represents the width of the floating gate. In some implementations, the ratio of the first grain size to the width W1 of the floating gate is 0.05-0.95. In some implementations, the ratio of the first grain size to the floating gate width W1 is 0.35-0.75.

In addition, in order to further improve the performance of the non-volatile memory device 100, the depth of the first nitride film 131 of the non-volatile memory device 100 of the present invention can be controlled within a specific range.

In some embodiments, as shown in FIG. 1G, the maximum depth of the first nitride film 131 is D1, the depth of the top surface of the first polysilicon layer 110 is the second depth D2, and the second depth D2 minus the maximum The difference of the depth D1 is ΔD. In some embodiments, ΔD is a positive value, that is, the lowest part of the first nitride film 131 is higher than the top surface of the first polysilicon layer 110. If the value of the maximum depth D1 is too large, the first nitride film 131 is too close to the tunnel oxide layer 104. As a result, over-programming problems are prone to occur. Conversely, if the value of the maximum depth D1 is too small, the second trench 123 is too shallow and ΔD is too large. As a result, the problem of excessive erasure is likely to occur, which increases the variability of the threshold voltage of the non-volatile memory device 100, thereby reducing the reliability and durability of the device. With the miniaturization of memory devices, the above problems will become more serious.

In order to improve the above problem, the relative relationship between the depth of the first nitride film 131 and the depth of the top surface of the first polysilicon layer 110 may be controlled as needed. In some implementations, the aforementioned difference ΔD is 5-50 nm. In some implementations, the above-mentioned difference ΔD is 10-30 nm.

In order to further verify the advantages of the first nitride film, the second nitride film, and the implantation of N ₂ ⁺ ions, the inventors of the present application conducted experiments. FIG. 5 illustrates experimental results of threshold voltage variability of the nonvolatile memory devices of Comparative Example (A) and Example (A).

Embodiment (A) is to manufacture a non-volatile memory device according to the relevant steps described in FIGS. 1A to 1G, and the resulting non-volatile memory device may include the structure shown in FIG. 1G. The non-volatile memory device of Comparative Example (A) is manufactured according to similar steps as in Example (A), except that Comparative Example (A) does not perform N ₂ ⁺ ion implantation and does not form the first nitrogen Compound film and second nitride film. The non-volatile memory devices of Example (A) and Comparative Example (A) were programmed/erased 10 or ⁵ times to measure the threshold voltage, and the difference between the maximum and minimum values of the threshold voltage ( The statistical results of the difference in threshold voltage (hereinafter referred to as threshold voltage) are shown in Fig. 5.

In Figure 5, the greater the difference in threshold voltage, the greater the variability of the threshold voltage. In other words, the less reliable the non-volatile memory device. On the other hand, if the average difference value of the threshold voltage exceeds 3000 mV, it is considered that the durability test cannot be passed.

Referring to FIG. 5, for the non-volatile memory device of Comparative Example (A), the average difference in threshold voltage is about 3800 mV, that is, the durability test cannot be passed. For the non-volatile memory device of Example (A), the average difference value of the threshold voltage is about 2800 mV, which represents passing the durability test.

From the above experimental results, it can be proved that the non-volatile memory device 100 of the present invention can significantly improve or solve the above-mentioned problems of over-programming and over-erase, and thus can improve the threshold voltage of the non-volatile memory device and greatly improve the device Yield and durability.

FIG. 2 is a schematic cross-sectional view of a non-volatile memory device 200 according to other embodiments of the invention. FIG. 2 is similar to FIG. 1 except that before forming the first nitride film 131, a third polysilicon layer 150 is formed on the second polysilicon layer 120. The same elements in Fig. 2 and Fig. 1 are denoted by the same reference numerals. In order to simplify the description, the elements that are the same as those in FIG. 1 and the forming process steps will not be repeated here.

In some embodiments, after the doped second polysilicon layer 120 is formed, the supply of the doping gas is stopped, and the on-site deposition process (ie, the third deposition process) is continued to form the undoped first The three polysilicon layers 150 are on the second polysilicon layer 120.

Since there is no dopant (eg, phosphorus dopant) in the third polysilicon layer 150, the third polysilicon layer 150 can also be used as a capping layer or a barrier layer to block the phosphorus dopant in the second polysilicon layer And reduce the generation of protrusions on the surface of the second polysilicon layer 120 due to the emission of phosphorus dopants. In this way, the reliability and durability of the non-volatile memory device can be further improved. In some implementations, the thickness of the third polysilicon layer 150 is 1-50 nm.

In summary, the advantages of the non-volatile memory device and the manufacturing method thereof provided by the embodiments of the present invention include at least:

(1) Use a high content of N ₂ ⁺ ions as an ion source to concentrate nitrogen dopants on the surface of the first polysilicon layer. Therefore, the problems of over-programming and over-erasing can be significantly improved or solved, and the reliability and durability of the non-volatile memory device can be greatly improved.

(2) Forming a first nitride film and a second nitride film to block the escape of phosphorus dopants and reduce the occurrence of protrusions on the surface of the second polysilicon layer. Therefore, the variability of the threshold voltage of the non-volatile memory device can be reduced, thereby improving the reliability and durability of the device.

(3) Nitrogen dopants can be doped in the tunneling oxide layer and the substrate as needed to further block the phosphorus dopants. Therefore, the threshold voltage, reliability, and durability of the nonvolatile memory device can be further improved.

(4) The third polysilicon layer 150 may be formed as necessary to further block the escape of phosphorus dopants and the protrusions on the surface of the second polysilicon layer 120. Therefore, the reliability and durability of the non-volatile memory device can be further improved.

(5) The ion implantation process using N ₂ ⁺ ions as the ion source can be easily integrated into the existing non-volatile memory device process without substantial modification or replacement of the process and/or production equipment. The impact of cost is minimal.

Although the present invention has been disclosed in several preferred embodiments as above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, therefore, the scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧ Non-volatile memory device

102‧‧‧ substrate

104‧‧‧Tunnel oxide layer

110‧‧‧The first polysilicon layer

112‧‧‧N ₂ doped thin layer

120‧‧‧Second polysilicon layer

122‧‧‧Isolated structure

131‧‧‧ First nitride film

132‧‧‧ oxide layer

133‧‧‧Nitride layer

134‧‧‧ oxide layer

135‧‧‧Second nitride film

140‧‧‧ polysilicon material

D1, D2‧‧‧Depth

△D‧‧‧Depth difference

W1‧‧‧Width

Claims (18)

A non-volatile memory device includes: a tunneling oxide layer formed on a substrate; a floating gate formed on the tunneling oxide layer, wherein the floating gate includes: a first polycrystalline The silicon layer includes a plurality of first polysilicon grains having a first grain size; a second polysilicon layer formed on the first polysilicon layer includes a plurality of grains having a second grain size A second polysilicon grain, wherein the second grain size is larger than the first grain size, and wherein the second polysilicon layer includes a dopant; and a nitrogen dopant formed on the first polysilicon In a layer and located in a gap between the first polysilicon grains; a dielectric layer formed on the floating gate, wherein the dielectric layer includes: a first nitride film formed compliantly And covering the floating gate; and an oxide layer/nitride layer/oxide layer structure compliantly formed on the first nitride film; and a control gate formed on the dielectric layer. The non-volatile memory device as described in item 1 of the patent scope, wherein the dielectric layer further includes a second nitride film compliantly formed on the oxide layer/nitride layer/oxide layer structure . The non-volatile memory device as described in item 1 of the patent application range, wherein the thickness of the second polysilicon layer is greater than the thickness of the first polysilicon layer. The non-volatile memory device as described in item 1 of the patent application range, wherein the first die size is 1-70 nm. The non-volatile memory device as described in item 1 of the patent application range, wherein the floating gate has a width, and the ratio of the first die size to the width is 0.05-0.95. The non-volatile memory device as described in item 1 of the patent application range, wherein the dopant is phosphorus, and the concentration of the dopant is 10 ²⁰ -10 ²² atoms/cm ³ . The non-volatile memory device as described in item 2 of the patent application range, wherein the thickness of the first nitride film is 1-5Å, and the thickness of the second nitride film is 1-5Å. The non-volatile memory device as described in item 1 of the patent application range, wherein the nitrogen concentration of the first nitride film is 10 ²¹ -10 ²³ atoms/cm ³ . The non-volatile memory device as described in item 1 of the patent application range, wherein the nitrogen dopant is further formed in the second polysilicon layer, and the concentration of the nitrogen dopant is distributed on the substrate and the first The crystalline silicon layer and the second polysilicon layer include a first peak, a second peak and a third peak, the first peak is located in the first polysilicon layer, and the second peak is located in the substrate The third wave peak is located in the second polysilicon layer, and the concentration of the nitrogen dopant in the third wave peak is not greater than the concentration in the first wave peak and the second wave peak. The non-volatile memory device as described in item 9 of the patent application range, wherein the concentration of the nitrogen dopant at the first peak divided by the concentration of the nitrogen dopant at the third peak is between 10 ² and 10 ⁵ between. The non-volatile memory device as described in item 9 of the patent application range, wherein the concentration distribution of the nitrogen dopant in the second polysilicon layer further includes a fourth peak, and the nitrogen dopant is in the fourth The concentration of the peak divided by the concentration of the nitrogen dopant in the third peak is not greater than 1. The non-volatile memory device as described in item 1 of the patent application range, wherein the first nitride film has a maximum depth D1, a top surface of the first polysilicon layer has a second depth D2, and wherein The difference ΔD of the second depth D2 minus the maximum depth D1 is 5-50 nm. A method for manufacturing a non-volatile memory device includes: forming a tunneling oxide layer on a substrate; forming a floating gate on the tunneling oxide layer, wherein forming the floating gate includes: performing a first A deposition process to form a first polysilicon layer on the tunneling oxide layer, wherein the first polysilicon layer is an undoped polysilicon layer; an ion implantation process is performed to include N ₂ impurities are implanted on the surface of the first polysilicon layer; a second deposition process is performed to form a second polysilicon layer on the first polysilicon layer, wherein the second polysilicon layer A polysilicon layer doped with a dopant; and performing a heat treatment process to form a plurality of first polysilicon grains having a first grain size in the first polysilicon layer, and in the second Forming a plurality of second polycrystalline silicon grains having a second grain size in the polycrystalline silicon layer, wherein the second grain size is larger than the first grain size; forming a dielectric layer on the floating gate; and A control gate is formed on the dielectric layer. The method for manufacturing a non-volatile memory device as described in item 13 of the patent application range, wherein the ion implantation process uses more than 99% N ₂ ⁺ as an ion source. The method for manufacturing a non-volatile memory device as described in item 13 of the patent application scope further includes: forming a first nitride film on the surface of the floating gate; and compliantly forming an oxide layer/nitride The layer/oxide layer structure is on the nitride film. The method for manufacturing a non-volatile memory device as described in item 15 of the patent application scope further includes: conformally forming a second nitride film on the oxide layer/nitride layer/oxide layer structure. The method for manufacturing a non-volatile memory device as described in item 13 of the patent application range, wherein the second deposition process includes a field doping process, and the field doping process is doped with phosphorus as the dopant. The method for manufacturing a non-volatile memory device as described in item 13 of the patent application scope, wherein after performing the second deposition process, further comprising performing a third deposition process to form a third polysilicon layer on the On the second polysilicon layer, the third polysilicon layer is an undoped polysilicon layer.

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