TWI505653B - Enhanced isolation circuit - Google Patents

Description

Enhanced isolation circuit

The present invention relates to the field of wireless communications, and more particularly to a circuit for enhancing the isolation of a Tx/Rx switching interval.

The Wireless Local Area Network (WLAN) transceiver has a half-duplex mechanism, and its working state switches between receiving Rx and transmitting Tx, but cannot work in both Rx state and Tx state. The Rx state and the Tx state cannot interfere with each other, that is, the Tx link and the Rx link require good isolation.

When the existing transceiver operates in the Tx state, the Low-Noise Amplifier (LNA) is turned off by a control signal, or a switching circuit is introduced to turn off the low-noise amplifier LNA when it is not working. To improve the isolation of the Tx/Rx link and avoid loop distortion, and vice versa.

However, if the Tx/Rx enable signal of Tx/Rx is used to control the switch circuit, such as DC switch, if the DC switch is poorly designed, for example, if the delay time is too long, the power cannot be immediately turned off, resulting in power failure delay. Loop distortion.

In the Tx/Rx switching interval, usually after the Rx control signal Rx Enable Signal is turned off, the _guard time t _guard is turned on and the Tx control signal Tx Enable Signal is turned on to avoid loop distortion in the Tx/Rx switching interval, and vice versa. As shown in Figure 1A, if the DC switch design is poor, when the Rx control signal Rx Enable Signal is turned off, the DC switch output voltage DC switch Vout cannot be pulled to the off state immediately, but a slow drop, at this time Tx The control signal Tx Enable Signal is turned on after the delay of the t _guard time, and there is still a Tx/Rx link that is in the working state period t _Tx/Rxen . This loop distortion is caused by the voltage drop time of the output signal of the DC switch of the Rx link being too long.

In contrast, if the Tx link also uses a DC switch to control the power supply of the Power Amplifier (PA), and the DC switch output voltage DC switch Vout drops slowly, then the Tx control signal Tx Enable Signal is turned off and the Rx control signal is turned off. Loop distortion is also generated in the switching interval that Rx Enable Signal is turned on, as shown in Figure 1B.

Therefore, if the switching circuit of the low noise amplifier LNA or the power amplifier PA is poorly designed, the voltage drop time is too long and exceeds the guard time t _guard , regardless of whether the operation is in the Tx state or the Rx state, during the Tx/Rx switching process. Both can cause serious loop distortion.

In view of the problems existing in the prior art, the present invention provides a circuit for enhancing the isolation of the Tx/Rx switching interval, which can greatly shorten the voltage drop time of the switching circuit, and at the same time, the circuit for enhancing the isolation also provides a protection mechanism to avoid the transmission chain. The road and the receiving link work at the same time, completely solving the loop distortion problem.

In order to achieve the above object, the present invention provides an enhanced isolation circuit for enhancing the isolation of a Tx link and an Rx link switching interval, and the operation of the Tx link and the Rx link is controlled by a Tx control signal and an Rx control signal, the Tx/Rx control signal being turned off, waiting for a guard time to turn on the Rx/Tx control signal, the enhanced isolation circuit including a power supply a circuit, the power supply circuit is controlled by the Tx/Rx control signal, and when the Tx/Rx control signal is enabled, powering the Tx/Rx link, the Tx/Rx control signal is not enabled De-energizing the Tx/Rx link, further comprising: a discharge circuit connected to the voltage output end of the power supply circuit, the operation of the discharge circuit being controlled And the inverting circuit is connected between the Tx/Rx control signal and the discharging circuit for inverting the Tx/Rx control signal Controlling the discharge circuit after processing, such that when the Tx/Rx control signal is enabled, the discharge circuit does not operate, and when the Tx/Rx control signal is not enabled, the discharge circuit supplies the power The voltage output of the circuit is discharged.

Further preferably, the discharge time of the discharge circuit is less than the protection time.

Further preferably, the discharge circuit comprises an n-MOS having a source grounded, a drain connected to the voltage output of the power supply circuit, and a gate connected to the Tx/Rx control signal via the inverter circuit .

Alternatively, the discharge circuit includes an npn-BJT whose emitter is grounded, the collector is connected to the voltage output of the power supply circuit, and the base is connected to the Tx/Rx control signal through the inverter circuit. .

Further preferably, the inverter circuit is an inverter.

Alternatively, the discharge circuit includes a second n-MOS and a second resistor, a source of the second n-MOS is grounded, and a drain is connected to the voltage output of the power supply circuit, the second resistor Connected between the gate of the second n-MOS and the ground; The inverter circuit includes a third p-MOS having a source connected to the power source, a gate connected to the Tx/Rx control signal, and a drain connected to the gate of the second n-MOS.

Further preferably, the enhanced isolation circuit further includes a delay circuit, wherein the power supply circuit includes a first p-MOS and a first resistor, and a source of the first p-MOS is connected to a power source, a voltage output end of the power supply circuit, the first resistor being connected between the power source and the gate of the first p-MOS; the delay circuit comprising a fourth n-MOS and a fourth resistor, the fourth a gate of the n-MOS is coupled to the Tx/Rx control signal, a drain is coupled to the gate of the first p-MOS, and a source is coupled to the voltage output of the Rx/Tx link, A fourth resistor is coupled between the source of the fourth n-MOS and ground.

Further preferably, the resistance of the first resistor is greater than or equal to 10 kΩ, and is less than or equal to 20 kΩ, and the resistance of the second resistor is greater than or equal to 10 kΩ, less than or equal to 20 kΩ, and the resistance of the fourth resistor is greater than or equal to 1 kΩ, less than or equal to 3kΩ.

The effect of the invention is that the invention introduces a discharge path, and when the control signal is low level, the voltage of the electronic switch can be quickly reduced to a closed state, thereby shortening the voltage off-delay time and effectively suppressing the Tx/Rx switching interval. Loop distortion occurs and the isolation is greatly improved. At the same time, the invention also provides a protection mechanism for detecting and delaying, detecting whether the voltage of the previous state is completely turned off, and then outputting the voltage of the next state after being completely turned off, that is, the output voltage is also corresponding to the case of delayed power-off. Delayed output, thereby increasing the isolation of the Tx/Rx link by extending the protection time, completely suppressing loop distortion.

10‧‧‧Power supply circuit

20‧‧‧Discharge circuit

30‧‧‧Inverter circuit

31‧‧‧Inverter

40‧‧‧Delay circuit

Figures 1A and 1B are schematic diagrams showing loop distortion in the prior art.

Figure 2 is a schematic diagram of the circuit of the present invention.

Figure 3 is a circuit diagram of Embodiment 1 of the present invention.

Figure 4 is a circuit diagram of Embodiment 2 of the present invention.

Figure 5 is a circuit diagram of Embodiment 3 of the present invention.

Figure 6 is a circuit diagram of Embodiment 4 of the present invention.

Figure 7 is a schematic diagram of the present invention applied to an NxN WLAN radio frequency front end circuit.

The invention will be further described in detail below with reference to the accompanying drawings.

2 is a schematic diagram of the enhanced isolation circuit of the present invention. The enhanced isolation circuit includes a discharge circuit 20 in addition to the conventional power supply circuit 10, and the voltage output terminal Vout of the power supply circuit 10 is connected to the input end of the discharge circuit 20. . The power supply circuit 10 and the discharge circuit 20 are controlled by the same control signal. When the control signal is enabled, the power supply circuit 10 starts to supply power. Conversely, when the control signal is not enabled, the discharge circuit 20 starts to discharge, thereby shortening the power supply circuit 10. The voltage drop time, if the discharge time of the discharge circuit 20 is less than the protection time t _{guard of the} Tx/Rx link, the purpose of enhancing the isolation can be achieved.

The enhanced isolation circuit is for enhancing the isolation of the Tx/Rx switching interval in the Tx/Rx link, wherein the control signal for controlling whether the power supply circuit 10 and the discharging circuit 20 operate is Tx/Rx control for controlling the Tx/Rx operating state. Signal Tx/Rx Enable Signal.

The enhanced isolation circuit further includes an inverter circuit 30, and the inverter circuit 30 is connected Between the control signal and the discharge circuit 20, the Tx/Rx control signal Tx/Rx Enable Signal is used for inverting processing, and then the discharge circuit 20 is controlled, so that when the Tx/Rx control signal Tx/Rx Enable Signal is enabled, The discharge circuit 20 does not operate; when the Tx/Rx control signal Tx/Rx Enable Signal is not enabled, the discharge circuit 20 discharges the voltage output terminal Vout of the power supply circuit 10.

Example 1

As shown in FIG. 3, it is a circuit diagram of Embodiment 1 of the present invention. The power supply circuit 10 of the enhanced isolation circuit is a p-MOS, the source of which is connected to the power supply VDD, and the discharge circuit 20 is an n-MOS, the source thereof. Grounded, the p-MOS 汲 is the voltage output terminal Vout of the discharge circuit 10, which is connected to the drain of the n-MOS.

The inverter circuit 30 is an inverter 31, and the Tx/Rx control signal Tx/Rx Enable Signal is connected to the gates of the p-MOS and n-MOS through the inverter 31, respectively.

The inverter 31 inverts the Tx/Rx control signal Tx/Rx Enable Signal, that is, inverts the high potential to a low potential and then controls whether the p-MOS and the n-MOS are activated or not. When the Tx/Rx control signal Tx/Rx Enable Signal is high, the potential is inverted to a low potential through the inverter 31. At this time, the p-MOS channel is turned on, and the output voltage terminal Vout of the power supply circuit 10 has a voltage output. At the same time, the n-MOS channel is turned off to be in an open state; conversely, when the Tx/Rx control signal Tx/Rx Enable Signal is low, the potential is inverted to a high potential through the inverter 31, and at this time, the p-MOS channel When the n-MOS channel is turned off, the output voltage terminal Vout is quickly discharged through the ground path provided by the n-MOS.

It should be noted that since the Tx control signal Tx Enable Signal is turned off, it will wait for a guard time t _guard and then start the Rx control signal Rx Enable Signal. Therefore, only the discharge time of the n-MOS is less than the guard time t _guard , and the loop distortion phenomenon can be avoided. . The discharge time of the discharge circuit 20 includes the voltage delay time t _{D of the} n-MOS and the voltage rise time t _R , and the following relationship can be obtained: t _guard >t _D +t _R (1)

Therefore, the choice of n-MOS must satisfy the relationship (1) to ensure that the discharge path can act instantaneously, thereby avoiding loop distortion.

Example 2

As shown in FIG. 4, it is a circuit diagram of Embodiment 2 of the present invention. The power supply circuit 10 of the enhanced isolation circuit is a pnp-BJT, the emitter is connected to the power supply VDD, and the discharge circuit 20 is an npn-BJT, and its emitter Ground, the set of pnp-BJT is the voltage output terminal Vout of the discharge circuit 10, which is connected to the collector of the npn-BJT.

The inverter circuit 30 is an inverter 31, and the Tx/Rx control signal Tx/Rx Enable Signal is connected to the bases of the pnp-BJT and npn-BJT through the inverter 31, respectively.

In the second embodiment, the p-MOS and the n-MOS in the first embodiment are replaced with pnp-BJT and npn-BJT, respectively, and the effect of shortening the discharge time can be achieved. Since the p-MOS and n-MOS must be charged before the gate oxide layer can be charged to reverse the channel polarity, there will be a voltage delay time t _D . If npn-BJT is used, there is no voltage delay time t _D , ie t _D = 0. Of course, in order to ensure that the discharge circuit 20 can complete the discharge within the _guard time t _guard , the selection of the npn-BJT must satisfy the relation (1).

Example 3

As shown in FIG. 5, it is a circuit diagram of Embodiment 3 of the present invention. The power supply circuit 10 of the enhanced isolation circuit is a Low Drop-Out regulator (LDO), and the discharge circuit 20 is an n-MOS. The source is grounded, and the drain is connected to the voltage output terminal Vout of the power supply circuit 10. The Tx/Rx control signal Tx/Rx Enable Signal is connected to the low dropout regulator LDO to control whether the low dropout regulator LDO is supplied with power. At the same time, the Tx/Rx control signal Tx/Rx Enable Signal is passed. An inverter 31 is connected to the gate of the n-MOS to control whether the discharge circuit 20 is discharged.

When the Tx/Rx control signal Tx/Rx Enable Signal is a high voltage level, the low dropout regulator LDO can supply power. When the Tx/Rx control signal Tx/Rx Enable Signal is a low voltage level, the low dropout The regulator LDO turns off the power. At this time, the Tx/Rx control signal Tx/Rx Enable Signal generates a high voltage level through the inverter 31, and turns on the n-MOS to provide a discharge path. In order to ensure that during the protection time t _guard , the output voltage terminal Vout can be quickly reduced to zero potential, that is, the discharge is completed to avoid loop distortion. The voltage drop time t _{off of the} LDO needs to be less than the guard time t _guard , and the following relationship can be obtained: t _guard >t _off (2)

Example 4

The enhanced isolation circuit provided by the present example adds a delay protection mechanism in addition to the discharge path. As shown in FIG. 6, it is a circuit diagram of Embodiment 4 of the present invention. The power supply circuit 10 of the enhanced isolation circuit includes the a p-MOS Q1 and a first resistor R1, the source of the first p-MOS Q1 is connected to the power supply VDD, the voltage output terminal Vout of the power supply circuit 10 is extremely large, and the first resistor R1 is a large resistor connected to the power supply VDD and the first Between the gates of a p-MOS Q1. The voltage of the first p-MOS Q1 gate is Von, the voltage between the source and the drain is VSD, and the current flowing through the first resistor R1 is In.

The discharge circuit 20 includes a second n-MOS Q2 and a second resistor R2. The source of the second n-MOS Q2 is grounded, the drain is connected to the voltage output terminal Vout of the power supply circuit 10, and the second resistor R2 is a large resistor. Between the gate of the second n-MOS Q2 and ground, the current flowing through the second resistor R2 is I _P .

The reverse circuit 30 includes a third p-MOS Q3 whose source is connected to the power supply VDD, the gate is connected to the Tx/Rx control signal Tx/Rx Enable Signal, and the drain is connected to the gate of the second n-MOS Q2. When the Tx / Rx control signal Tx / Rx Enable Signal is low, the third p-MOS Q3 signal is turned on, since the resistance of the second resistor R2 is large, the current flowing through the second resistor R2 I _P is quite small, so that the second The n-MOS Q2 channel is turned on, and the output voltage terminal Vout is quickly discharged through the ground path provided by the second n-MOS Q2.

The enhanced isolation circuit further includes a delay circuit 40 including a fourth n-MOS Q4 and a fourth resistor R4, and a gate of the fourth n-MOS Q4 is connected to the Tx/Rx control signal Tx/Rx Enable Signal, The drain is connected to the gate of the first p-MOS Q1, the voltage between the drain and the source is VDS, and the fourth resistor R4 is a large resistor connected between the source of the fourth n-MOS Q4 and the ground. The source of the fourth n-MOS Q4 is connected to the output voltage terminal Rx/Tx Vout of the Rx/Tx link, and the connection node is the protection detection terminal Vpd, that is, when the enhanced isolation circuit is controlled by the Tx control signal Tx Enable In the case of Signal, the protection detection terminal Vpd is connected to the output voltage terminal Rx_Vout of the Rx link, and conversely, when the enhanced isolation circuit is controlled by the Rx control signal Rx Enable Signal, the source of the fourth n-MOS Q4 and the Tx link The output voltage terminal Tx_Vout is connected.

The working principle of the enhanced isolation circuit in this embodiment is as follows: the first p-MOS Q1 is a switching element of the power supply circuit 10, the second n-MOS Q2 is a switching element of the discharging circuit 20, and the third p-MOS Q3 and the fourth The n-MOS Q4 acts as a reversal and integrates the protection mechanism. Taking the enhanced isolation circuit applied to the Rx link as an example, as shown in FIG. 6, the voltage output terminal Vout is completely controlled by the Rx control signal Rx Enable Signal, when the Rx control signal Rx Enable Signal is greater than the fourth n-MOS Q4. At the threshold voltage, the n-channel of the fourth n-MOS Q4 is turned on, at which time Von=VDS+Vpd (3)

Vpd=InR4 (4)

In=(VDD-VDS)/(R1+R4) (5)

The relation (5) ignores the influence of the fourth n-MOS Q4 on-resistance, and since the first resistor R1 and the fourth resistor R4 have a large resistance, the current In flowing to the first resistor R1 and the fourth R4 is relatively small, and the relationship is Equation (5) shows that the current In can be reduced by increasing the resistance value of the first resistor R1, wherein the resistance of the first resistor R1 should be in the following range: 10 kΩ ≦ R1 ≦ 20 kΩ (6)

Considering that the protection detection terminal Vpd is connected to the output voltage terminal Tx_Vout of the Tx link, when the output voltage terminal Tx_Vout of the Tx link is in the power supply state, the resistance of the fourth resistor R4 should be moderatelysized, because too large will affect the fourth n. - MOS Q4 normal operation, too small will produce severe 汲 current consumption, so the fourth resistor R4 resistance should be selected: 1kΩ ≦ R4 ≦ 3kΩ (7)

Therefore, in the case where the first resistor R1 and the fourth resistor R4 satisfy the relations (6) and (7), the protection detecting terminal Vpd will approach 0, so when the fourth n-MOS Q4 is turned on, the voltage of Von can be Approximate to VDS, VDS-VDD will be less than the threshold voltage of the first p-MOS Q1 and the first p-MOS Q1 will be turned on, and finally Vout=VDD-VSD (8)

In addition, the principle of the second resistor R2 is the same as that of the first resistor R1. The large resistor is beneficial to reduce the current I _P to reduce unnecessary power consumption. Therefore, the resistance of the second resistor R2 ranges from 10 kΩ. R2≦20kΩ (9)

The optimum resistance value of this embodiment is: R1=10kΩ, R2=10kΩ, R4=3kΩ

Although the discharge path is introduced to accelerate the discharge, the Tx link and Rx cannot be ensured. The link does not work at the same time, so the delay circuit 40 is required to delay the output voltage terminal Vout correspondingly, that is, the delay of the Tx/Rx link is completely improved by extending the protection time, thereby suppressing the loop distortion. phenomenon. For example, the present embodiment is applied to the receiving link Rx. The source of the fourth n-MOS Q4 is connected to the output voltage terminal Tx_Vout of the Tx link, and the function thereof is to detect the voltage of the output voltage terminal Tx_Vout in the Tx link. Quasi-bit, if there is voltage output, the Rx control signal Rx Enable Signal can not turn on the fourth n-MOS Q4, the first p-MOS Q1 is also turned off at the same time, so that the voltage output of the output voltage terminal Vout can be delayed, and then The purpose of suppressing loop distortion is achieved.

The working principle of this embodiment applied to the Tx link is the same as above.

Figure 7 is a schematic diagram of the present invention applied to an NxN WLAN radio frequency front-end circuit. The NxN WLAN radio front-end circuit includes N sets of radio frequency links, and the Rx link and the Tx link in each set of radio link are respectively connected to a single-pole pair. Two independent ports of the Single Pole Double Throw (SPDT), and the common 埠 of the SPDT is connected to an antenna Ant. Each Rx link includes a low noise amplifier LNA, and each Tx link includes a power amplifier PA. N sets of Rx links Rx 1-Rx N share a Rx control signal Rx Enable Signal controls the state of N low noise amplifier LNAs, N sets of Tx links Tx 1-Tx N share a Tx control signal Tx Enable Signal control N The state of the power amplifier PA.

The enhanced isolation circuit provided by the present invention is used in the Rx link and the Tx link, respectively, to improve isolation. As shown in Figure 7, the Rx switch circuit Rx Switch with enhanced isolation circuit is used to control the N-group Rx link Rx 1-Rx N low-noise amplifier LNA power supply and discharge, used to control the N-group Tx chain. The Tx 1-Tx N power amplifier PA is powered and discharged by a Tx switch circuit Tx Switch with an enhanced isolation circuit. The Rx switch circuit Rx Switch is controlled by the Rx control letter No. Rx Enable Signal, whose voltage output terminal Rx_Vout is respectively connected to N LNAs, and its protection detecting terminal Rx_Vpd is connected to the voltage output terminal Tx_Vout of the Tx switching circuit Tx Switch; the Tx switching circuit Tx Switch is controlled by the Tx control signal Tx Enable Signal The voltage output terminal Tx_Vout is respectively connected to the N PAs, and the protection detecting terminal Tx_Vpd is connected to the voltage output terminal Rx_Vout of the Rx switch circuit Rx Switch.

The discharge path of the Rx switch circuit Rx Switch and the Tx switch circuit Tx Switch improves the isolation of the Rx/Tx link. And the protection detection terminal Rx_Vpd of the Rx switch circuit Rx Switch is connected to the voltage output terminal Tx_Vout of the Tx switch circuit Tx Switch to determine whether the voltage output terminal Tx_Vout of the Tx switch circuit Tx Switch is powered, if the Rx switch circuit Rx Switch protection detection terminal Rx_Vpd When the voltage output terminal Tx_Vout of the Tx switch circuit Tx Switch is read to be high, the voltage output terminal Rx_Vout of the Rx switch circuit Rx Switch interrupts the voltage output, and vice versa, thereby completely avoiding the simultaneous operation of the Rx link and the Tx link. In this case, the loop distortion problem is solved, thereby improving the throughput of the uplink and the downlink.

In the present invention, the power supply circuit 10 can be implemented in various ways in a specific application. The implementation of the discharge circuit 20 is not affected by the power supply circuit 10, but different discharge circuits 20 may need to be matched with the corresponding inverter circuit 30 to achieve the object of the invention.

It should be noted that the above description is a detailed description of the present invention in detail with reference to the specific embodiments, and the specific embodiments of the present invention are not limited thereto, and those skilled in the art may Various equivalent modifications and variations are possible on the basis of the invention, and such equivalent modifications or modifications fall within the scope of the invention.

10‧‧‧Power supply circuit

20‧‧‧Discharge circuit

30‧‧‧Inverter circuit

40‧‧‧Delay circuit

Claims (10)

An enhanced isolation circuit for enhancing isolation of a Tx link and an Rx link switching interval, the Tx link and the Rx link being controlled by a Tx control signal and an Rx control signal, respectively Waiting for a guard time to turn on the Rx/Tx control signal after the Tx/Rx control signal is turned off, the enhanced isolation circuit includes: a power supply circuit controlled by the Tx/Rx control signal, When the Tx/Rx control signal is enabled, the Tx/Rx link is powered, and when the Tx/Rx control signal is not enabled, the Tx/Rx link is powered off; a discharge circuit, The discharge circuit is connected to the voltage output terminal of the power supply circuit, the operation of the discharge circuit is controlled by the Tx/Rx control signal, and an inverter circuit connected to the Tx Between the /Rx control signal and the discharge circuit, for inverting the Tx/Rx control signal and then controlling the discharge circuit, so that when the Tx/Rx control signal is enabled, the discharge The circuit does not operate, and when the Tx/Rx control signal is not enabled, the discharge circuit supplies the The voltage output of the circuit is discharged. The enhanced isolation circuit of claim 1, wherein the discharge time of the discharge circuit is less than the protection time. An enhanced isolation circuit according to claim 2, wherein the discharge circuit comprises an n-MOS having a source grounded, a drain connected to the voltage output of the power supply circuit, and a gate passing through the inverter circuit Connected to the Tx/Rx control signal. The enhanced isolation circuit of claim 2, wherein the discharge circuit comprises an npn-BJT having an emitter grounded, a collector connected to the voltage output of the power supply circuit, and a base passing through the inverter circuit Connected to the Tx/Rx control signal. Such as the enhanced isolation circuit of claim 3 or 4, the inverse circuit is a reverse Phase device. The enhanced isolation circuit of claim 1 or 2, wherein the discharge circuit includes a second n-MOS and a second resistor, a source of the second n-MOS being grounded, a drain and the power supply circuit The voltage output is connected, the second resistor is connected between the gate of the second n-MOS and the ground; the inverter circuit comprises a third p-MOS, the source is connected to the power source, and the gate is connected The Tx/Rx control signal is connected to the gate of the second n-MOS. The enhanced isolation circuit of claim 1 or 2, further comprising a delay circuit, wherein the power supply circuit comprises a first p-MOS and a first resistor, and the source of the first p-MOS is connected a power supply, ???the voltage output end of the power supply circuit, the first resistor is connected between the power source and the gate of the first p-MOS; the delay circuit includes a fourth n-MOS and a fourth a resistor, the gate of the fourth n-MOS is connected to the Tx/Rx control signal, the drain is connected to the gate of the first p-MOS, and the source is connected to the voltage of the Rx/Tx link The output terminals are connected, and the fourth resistor is connected between the source of the fourth n-MOS and the ground. The enhanced isolation circuit of claim 5, further comprising a delay circuit, wherein the power supply circuit comprises a first p-MOS and a first resistor, and a source of the first p-MOS is connected to a power source, Extremely at the voltage output end of the power supply circuit, the first resistor is connected between the power source and the gate of the first p-MOS; the delay circuit includes a fourth n-MOS and a fourth resistor, a gate of the fourth n-MOS is connected to the Tx/Rx control signal, a drain is connected to the gate of the first p-MOS, and a source is connected to the voltage output of the Rx/Tx link The fourth resistor is connected between the source of the fourth n-MOS and the ground. The enhanced isolation circuit of claim 6 further includes a delay circuit, wherein The power supply circuit includes a first p-MOS and a first resistor, a source of the first p-MOS is connected to a power source, and the voltage output end of the power supply circuit is substantially the same, and the first resistor is connected to the power source and The gate of the first p-MOS; the delay circuit includes a fourth n-MOS and a fourth resistor, the gate of the fourth n-MOS is connected to the Tx/Rx control signal, and the drain The gate of the first p-MOS is connected, the source is connected to the voltage output of the Rx/Tx link, and the fourth resistor is connected to the source of the fourth n-MOS and the ground between. The enhanced isolation circuit of claim 9 is characterized in that the resistance of the first resistor is greater than or equal to 10 kΩ and less than or equal to 20 kΩ, and the resistance of the second resistor is greater than or equal to 10 kΩ and less than or equal to 20 kΩ. The resistance is greater than or equal to 1kΩ and less than or equal to 3kΩ.