TWI440009B - Arrangement for a driving ic outputs - Google Patents

Description

Driver chip output pin arrangement

The present invention relates to an arrangement of output pins for driving a wafer, and more particularly to an arrangement of output pins for a display panel driving wafer.

The display panel can be divided into two types: banner type and portrait type. When the display panel is connected to the driving chip, the arrangement of the driving chips is different depending on whether the panel is a banner or a portrait, and there are different arrangement designs. Therefore, there are two kinds of driving chips to respond to the banner type and Portrait panel.

As shown in FIG. 1, the banner panel 1 and the array substrate 2 are connected to the driving wafer 10, and the driving wafer 10 is soldered to the left or right side of the panel. The gate line 21 of the banner panel is horizontally oriented, wherein G1, G2, ..., G799, and G800 respectively represent the first to 800th gate lines, and the source line 22 is vertically oriented. S1-S720 and S721-S1140 respectively represent the first to the first 140th source lines, and R, G, and B represent three different pixels of red, green, and blue, respectively. In order to match the wiring pattern of the gate line 21 and the source line 22 of the banner panel 1, the output pin 77 of the gate line driving circuit must be arranged at the central portion of the driving wafer 10, and the source line driving circuit Output pins 75, 76 are arranged at the upper and lower ends of the drive wafer 10. Therefore, the arrangement of the gate line driving block and the source line driving block inside the driving chip 10 is as shown in FIG. 1. From top to bottom, the source line driving block 65 and the gate line driving block 67 are respectively Source line drive block 66.

As shown in FIG. 2, the portrait panel 1 and the array substrate 2 are connected to the driving wafer 10. The direction of the gate line 21 of the portrait panel and the direction of the source line 22 are not the same as those of the banner type. Portrait panel with its gate line 21 The traces are in the vertical direction, wherein G1, G2, ..., G400, G401, G402, ..., G800 represent the first to 800th gate lines, respectively, and the source line 22 is in the horizontal direction. Wherein, S1, S2, S3, ..., S1138, S1139, S1140 represent the first to the first 140th source lines, respectively, and R, G, and B represent three different pixels of red, green, and blue, respectively. The drive wafer 10 is still soldered to the left or right side of the panel. When the driving wafer 10 is connected to the gate line 21 and the source line 22 of the portrait panel, the gate line driving output pins 71 and 72 must be arranged at the upper and lower ends of the driving wafer 10, and the source line 22 drives the output. The feet are arranged in the center of the drive wafer 10. Therefore, the arrangement of the gate line driving block and the source line driving block inside the driving chip 10 is as shown in FIG. 2, and the gate line driving block 61 and the source line driving block 63 are respectively from top to bottom. The gate line driving block 62 is convenient for connection with the portrait panel.

According to the foregoing prior art, at least two types of driving chips must be used, and different gate driving blocks and source line driving blocks are arranged and arranged in different positions to conform to the difference between the banner type and the portrait panel. demand.

The object of the present invention is to provide a driving chip, and through its internal gate line driving block and source line driving block and corresponding pin arrangement manner, so that a single driving chip can be simultaneously applied to banners and portraits. Panel. The driver chip is internally provided with two or more gate line driving blocks and source line driving blocks, and corresponding output pins, and a gate line driving block is placed between the two source line driving blocks. . When the driver chip is connected to the panel, depending on the requirements of the banner or portrait panel, the output pins of some gate line driving blocks can be floated, and the appropriate gate line driving block and appropriate The output of the source line driver block is connected to the panel. In this way, a single driver chip can be applied to the banner at the same time. With a portrait panel.

In a preferred embodiment of the present invention, the panel may be driven by a gate on array (GOA), and the gate line driving block in the driving chip may be a gate array (GOA) driver. Circuit block. Therefore, in the driving wafer, the gate array (GOA) driving circuit block and the source line driving block are arranged in order from top to bottom: the first gate array driving circuit block, the first source a line driving block, a second gate array driving circuit block, a second source line driving block, and a third gate array driving circuit block.

Another object of the present invention is to save the development cost of the driver chip. The driver chip supplier only needs to develop a driver chip, and a set of masks can be applied to both the banner type and the portrait panel. Different from the traditional way, two kinds of driving chips and two sets of reticle are needed.

Still another object of the present invention is to simplify the mass production process of the panel, and there is only one choice for driving the wafer, and it is no longer necessary to select different driving wafers depending on whether the panel is a banner or a portrait.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The present invention will be described below with reference to Figs. 3 and 4. As shown in FIG. 3, it is a panel 1 of a liquid crystal display, and the panel 1 is composed of a color filter substrate (not shown in FIG. 3) and an array substrate 2, and a driving wafer 10 is soldered to the array substrate 2. on. The gate line 21 of the panel 1 is horizontally oriented, and the source line 22 is oriented in a vertical direction (such a panel is generally referred to as a banner panel), and the driving mode is a gate on array (GOA) drive. And two gate arrays 31, 32 are respectively formed on the left and right sides of the array substrate 2, and the driving wafer 10 is soldered at The left or right side of the array substrate 2. The source line 22 on the panel is connected to the driving wafer 10 through the source line connecting lines 23, 24, and is located in the upper half of the array substrate 2 and the lower half of the array substrate. The interpole array 31 farther from the driving wafer 10 is connected to the driving wafer 10 through the gate array connecting line 41, wherein the gate array connecting line 41 is located in the upper half around the array substrate.

In this embodiment, there are three gate array driving circuit blocks 11, 12, 13 and two source line driving blocks 14, 15 in the driving wafer, and the order of the steps is from top to bottom: first a gate array driving circuit block 11, a first source line driving circuit block 14, a second gate array driving circuit block 12, a second source line driving circuit block 15 and a third gate array driving circuit region Block 13. The order of the output pins of the driving chip 10 is sequentially from top to bottom: the output pin 51 of the first gate array driving circuit block, the first source line driving circuit block output pin 54, and the second gate array driving. The output pin 52 of the circuit block, the second source line drive circuit block output pin 55 and the output pin 53 of the third gate array drive circuit block. The signals required for each gate array, such as the start pulse wave, the clock signal, the complementary clock signal, etc., can be driven by the first, second or third gate array drive circuit block output. Since the panel 1 is of a banner type, the gate array 31 farther from the driving wafer 10 is connected to the output pin 51 of the first gate array driving circuit block 11 through the gate array connecting line 41, and the first source line The output pin 54 of the driving circuit block 14 is connected to the source line of the left half of the panel 1 through the source connection line 23 above the panel, and the gate array 32 closer to the driving chip 10 is transmitted through the gate array connecting line 42 and The output pin 52 of the second gate array driving circuit block 12 is connected, and the output pin 55 of the second source line driving circuit block 15 is connected to the source line of the right half of the panel 1 through the source connecting line 24, and The output pin 53 of the third stage array driving circuit block 13 is floating.

As shown in Fig. 4, the embodiment of the present invention applied to a portrait panel is shown. Figure 4 shows a liquid crystal display and its panel is a portrait panel. The array substrate 2 of the panel has a gate line 21, a source line 22 and a driving wafer 10. The portrait panel has a gate line 21 in a vertical direction, a source line 22 in a horizontal direction, and a driving mode of the gate array. In this embodiment, the two gate arrays 31 and 32 are respectively disposed on the upper and lower sides of the array substrate 2, and the driving wafer 10 is still soldered on one side of the array substrate 2. The three gate array driving circuit blocks 11, 12, 13 and the two source line driving blocks 14, 15 are still disposed inside the driving chip, and the arrangement order thereof and the corresponding output pin arrangement manner are the same as those in the above embodiment. There is no need to change, only the connection method is changed. Since the connection line between the portrait panel gate line and the driving chip is respectively located at the upper half of the array substrate 2 and the lower half of the array substrate, and the position of the portrait panel due to the gate arrays 31, 32, The direction of the gate line and the direction of the source line are different from those of the banner panel, so the driver chip is connected to it differently. When the driving chip 10 is connected thereto, the gate array 31 disposed above the panel 1 is connected to the output pin 51 of the first gate array driving circuit block through the gate array connecting line 41, and the gate array disposed under the panel 32 is connected to the output pin 53 of the third gate array driving circuit block through the gate array connection line 42. The source line 22 of the panel is driven by the horizontal direction, and only needs to be driven through the source line connecting lines 23 and 24 and the output pin 54 and the second source line of the first source line driving circuit block, respectively. The output pin 55 of the circuit block can be connected, and the output pin 52 of the second gate array driving circuit block can be floated because it is not used.

In summary, the object of the present invention is to achieve the purpose of applying a banner and a portrait panel to a single driving chip by arranging the output pins of the driving chip and the corresponding driving circuit blocks. The invention also saves the development cost of the driving chip, and the driver of the driving chip only needs to develop a driving chip to be suitable at the same time. Used for banner and portrait panels. Different from the traditional way, two kinds of driving chips are needed, and two sets of masks increase the cost of driving the chips.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1‧‧‧LCD display

2‧‧‧Array substrate

10‧‧‧Drive chip

11‧‧‧First gate array driver circuit block

12‧‧‧Second gate array driver circuit block

13‧‧‧ Third Gate Array Drive Circuit Block

14‧‧‧First source line driver circuit block

15‧‧‧Second source line driver circuit block

20‧‧‧ panel

21‧‧‧ gate line

22‧‧‧ source line

23, 24‧‧‧ source line connection line

31‧‧‧First Gate Array

32‧‧‧Second gate array

41‧‧‧First gate array cable

42‧‧‧Second gate array cable

51‧‧‧First gate array driver circuit block output pin

52‧‧‧Second gate array driver circuit block output pin

53‧‧‧3rd gate array driver circuit block output pin

54‧‧‧First source line driver circuit block output pin

55‧‧‧Second source line driver circuit block output pin

61, 62, 67‧‧ ‧ gate line drive circuit block

63, 65, 66‧‧‧ source line driver circuit blocks

Output pin of 71, 72, 77‧‧ ‧ gate line drive circuit block

73, 75, 76‧‧ ‧ output line of gate drive circuit block

FIG. 1 is a schematic diagram of a prior art for connecting a banner panel.

2 is a schematic diagram of a prior art for connecting a portrait panel.

FIG. 3 is a schematic view of the present invention for connecting a banner panel.

4 is a schematic view of the present invention for connecting a portrait panel.

1. . . panel

2. . . Array substrate

10. . . Driver chip

11. . . First gate array driver circuit block

12. . . Second gate array driver circuit block

13. . . Third gate array driver circuit block

14. . . First source line driver circuit block

15. . . Second source line driver circuit block

twenty one. . . Gate line

twenty two. . . Source line

23, 24. . . Source line connection

31. . . First gate array

32. . . Second gate array

41. . . First gate array connection line

42. . . Second gate array connection line

51. . . First gate array driver circuit block output pin

52. . . Second gate array driver circuit block output pin

53. . . Third gate array driver circuit block output pin

54. . . First source line driver circuit block output pin

55. . . Second source line driver circuit block output pin

Claims (10)

A liquid crystal display comprising: a panel comprising: a gate line, a source line and at least one gate array; and a driving wafer connected to the source line and the at least one gate array, comprising: at least three gates An array driving circuit block, each of the gate array driving circuit blocks corresponding to a set of output pins; and at least two source line driving circuit blocks, each of the source line driving circuit blocks corresponding to one a group output pin, wherein at least one of the gate array driving circuit blocks is disposed between the two source line driving circuit blocks, and at least one of the source line driving circuit blocks The device is disposed between the two gate array driving circuit blocks. The liquid crystal display according to claim 1, wherein an output pin corresponding to the gate array driving circuit block disposed between the two source line driving circuit blocks is disposed on the two The source line driver circuit block corresponds to the two sets of output pins. The liquid crystal display of claim 2, wherein the at least one gate array comprises a first gate array and a second gate array, and the first gate array and the second gate array are respectively Placed on both sides of the source line. The liquid crystal display of claim 3, wherein at least one of the output pins corresponding to the gate array driving circuit blocks is floating. The liquid crystal display of claim 3, wherein the panel is of a portrait type, and the output pin corresponding to the gate array driving circuit block disposed in the two source line driving circuit blocks is floating. The liquid crystal display device of claim 1, wherein the gate array driving circuit block comprises a first gate array driving circuit block, a second gate array driving circuit block, and a third gate. An array driving circuit block, wherein the source line driving circuit blocks comprise a first source line driving circuit block and a second source line driving circuit block, and the circuit block is in the driving chip The arrangement manner is: the first gate array driving circuit block, the first source line driving circuit block, the second gate array driving circuit block, the second source line driving circuit block, The third gate array drives the circuit block. The liquid crystal display of claim 6, wherein the at least one gate array comprises a first gate array and a second gate array, and the first gate array and the second gate array are respectively It is disposed on both sides of the source line. The liquid crystal display of claim 7, wherein the panel is of a banner type, and an output pin corresponding to the third gate array driving circuit block is floating. The liquid crystal display of claim 7, wherein the panel is of a banner type, and an output pin corresponding to the first gate array driving circuit block is floating. The liquid crystal display of claim 7, wherein the panel is of a portrait type, and the output pin corresponding to the second gate array driving circuit block is floating.