1339511 1 第9612817]號之專利說明書修正本 修正曰期：99.11.11 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種轉換器，特別是有關於一種數 位類比轉換器to analog converter ; DAC)。 【先前技術】 數位類比轉換器（digital to analog converter ; DAC) 係為必要介面電路，用以將信號由數位類型轉換至類 •比類型，特別是轉換至類比信處理類型（ana】〇g signal • Pr〇CeSSing d〇main)。在類比數位轉換器（ADC)的技術領域 . 中，數位類比轉換器也是一道關鍵。數位類比轉換器接 •收N位元的數位字元（dighal w〇rd)或資料，並將其轉換 • 成γ類比電壓信號。該類比電壓信號的範圍由零至一最 大電壓。該最大電壓係取決於數位類比轉換器所提供的 參考電壓。 # 關於數位類比轉換器對於語音信號的效能而言，三 角積分調變（delta sigma modulation)係經常被使用，用以 付知所需的總諧波失真（諧波成分比例）或是信號雜訊比 (signal to n〇ise rati0 ; S/N)等。根據三角積分調變，藉由 雜訊形成技得，使得在轉換時，可達到預定的功效。 【發明内容】 本發明提供一種數位類比轉換器，包括一第—電容 态、一第二電容器 '一第三電容器、一第四電容器、一 運算放大器以及複數開關。在一第一期間，第一電容器 0758-A32476TWF1 (20100914) -Ϊ339511 第96128171號之專利說明書修正本 修正曰期：99.11.1] 儲存一第一電壓，而第二電容器儲存一第二電壓。運算 放大器具有一正相輸入端、一反相輸入端、一正相輸出 端及一反相輸出端。第三電容器耗接於該反相輸入端及 該正相輸出端之間。第四電容器耦接於該正相輸入端及 該反相輸出端之間。在與該第一期間無交疊之一第二期 間，開關根據一數位信號，將該第一及第二電容器耦接 該運算放大器，其中當該第一電容器與該第三電容器並 聯時，該第二電容器與該第四電容器並聯，當該第一電 容器與該第四電容器並聯時，該第二電容器與該第三電 容器並聯。 本發明提供另一種數位類比轉換器，包括一第一電 容器、一第二電容器、一運算放大器、一第一開關群組 以及一第二開關群組。在一第一期間，第一電容器儲存 一第一電壓，而第二電容器儲存一第二電壓。運算放大 器具有一正相輸入端、一反相輸入端、一正相輸出端以 及一反相輸出端。在與該第一期間無交疊之一第二期 間，第一開關群組根據一數位信號，將該第一電容器並 聯該運算放大器，而第二開關群組根據該數位信號，將 該第二電容器並聯該運算放大器，其中，在該第二期間， 當該第一電容器耦接於該反相輸入端及該正相輸出端之 間時，該第二電容器耦接於該正相輸入端及該反相輸出 端之間，當該第一電容器耦接於該正相輸入端及該反相 輸出端之間時，該第二電容器耦接於該反相輸入端及該 正相輸出端之間。 0758-A32476TWFl(20100914) 6 第96】2817】號之專利說明書修正本 修正日期：99.]1.11 本發明另提供—種 法。在-第-期間，將—第二轉換器之轉換方 中，以及將一第二 1壓儲存於-第-電容器 第-期間存於—第二電容器中。在與該 第一及篆二 弟二期間，根據-數位信號，將节 弟及弟一電容器與1 匕將。亥 驟包含：當將兮Μ — ♦ A °。亚如’其中该並聯步 相浐入踹及Λ “谷器耦接於該運算放大器之一反 相輸入…正相輸出端 ： 於該運算放大器之— ^弟一电奋克耦接 合將兮Μ—士6 相輸入端及一反相輸出端之間， 二L於，谷裔耦接於該運算放大器之該正相輪入端 放3= 端ί間時’將該第二電容器，接於該運算 反相輪入端及該正相輸出端之間。 為讓本發明之上述和其他目的、特徵、和優點 明顯易t重’下文特舉出較伟每 * *人 作詳細說明如下： 貝施例，並配合所附圖式， 【實施方式】 第1圖為本發明之數位類比轉換器之示意圖。如圖 所示’數位類比轉換器10包括，電容器CINP、CINN、 CF1、CF2、運算放大器11〇、開關則〜swi2。所有符 號為0P的節點相互轉接在一起。所有符號為〇N的節點 相互耗接在一起。 開關SW1〜SW4由時脈信號Φι控制。開關sw卜SW3 與電容器CINP串聯於參考電壓VREFp與共通模式電壓 Vcm之間。開關SW2' SW4與電容器CINN串聯於參考電 〇758-A32476TWF1(20100914) 7 1339511 修正日期：99.11.11 第96128Π1號之專利說明書修正本 壓VREFN與共通模式電壓VcM之間。 開關SW5〜SW8由時脈信號％及數位信號£)丨控 制。開關SW9〜SW12由時脈信號φ2及數位信號Dib控 制°數位信號Di係由三角積分調變器（delta_sjgma modnlator)120所產生。數位信號Di經過反相器13〇反相 後，便可產生數位信號Dib。在本實施例中，三角積分調 ’交斋120係產生單一位元（singie_bit)數位信號。 在第一時間，開關SW1〜SW4被導通，使得電容器 CINP所儲存的電荷為（VREFp_VcM)*CINp，而電容器αΝΝ 所儲存的電荷為（VREFN-Vcm)*CINn。 在第一期間，開關SW5、SW6、SW9及SW10根據 數位信號Di及Dib，將電容器CINp耦接至運算放大器 110。同樣地，開關SW1、SW8、swn及SW12根據數 位信號Di及Dib，將電容器CINn耗接至運算放大器π〇。 在本實施财，運算放M 11Q包括—正相輸入 :二：反相輸入端、一正相輸出端以及-反相輸出端。 电奋CF1耗接於反相輸人端及正相輸出端之間，而電 容器，接於正相輸入端及反相輸出端之間。 吵在弟二期間’根據數位信號〇丨，開關SW5及SW6 將電容器CINP耦接至運曾访士叫11Λ ,^ r 放大克】】〇之反相輸入端及正 相輸出端。因此，雷交哭、， Ρ亚聯電容器CF】。同樣地， 開關S W 7及S W 8柄撼者々乂λ γ丄„上 至運uDi，將電容器CINn耗接 主連异放大為ll〇之正相私λ山 ♦办。、，β 相輸入玄而及反相輸出端。因此’ 电合為CINn亚聯電容器CP)。 1 58-A324 76TWF1 (20100914) 1339511 修正日期：99.11.]丨 第96128171號之專利說明書修正本 在第二期間，根據數位信號Dib，開關SW9及sw】〇 馳接至運算放大器11G之正相輸入端及反 相輸出端。因此，電容器CINp並聯電容器cn。同樣地， 開關SWn及SW12根據數位信號Dib，將電容哭⑽ 麵接至？算放大器】10之反相輸入端及正相輸出端。因、 此’電谷器CINn並聯電容器CF1。 假設，時脈信號Φι或是％為高位準時，則可 相對應的開關，當時脈信號φ]或是％為低位準時’ 不導通相對應的開關。 、 ㈤^一^卜時脈信“為高位準’使得開關1339511 1 Patent No. 9612817] Revision of this revision period: 99.11.11 IX. Invention Description: The present invention relates to a converter, and more particularly to a digital analog converter to analog Converter ; DAC). [Prior Art] A digital to analog converter (DAC) is a necessary interface circuit for converting a signal from a digital type to a analog type, in particular to an analog signal processing type (ana) 〇g signal • Pr〇CeSSing d〇main). In the technical field of analog-to-digital converters (ADCs), digital analog converters are also a key. The digital analog converter receives N bits of dighal w rd or data and converts it into a gamma analog voltage signal. The analog voltage signal ranges from zero to one maximum voltage. This maximum voltage is dependent on the reference voltage provided by the digital analog converter. # About digital analog converters For the performance of speech signals, delta sigma modulation is often used to know the total harmonic distortion (harmonic component ratio) or signal noise ratio required. (signal to n〇ise rati0; S/N) and so on. According to the trigonometric integral modulation, the noise is formed by the technique, so that the predetermined effect can be achieved at the time of conversion. SUMMARY OF THE INVENTION The present invention provides a digital analog converter including a first capacitor state, a second capacitor 'a third capacitor, a fourth capacitor, an operational amplifier, and a plurality of switches. In a first period, the first capacitor 0758-A32476TWF1 (20100914) - Ϊ 339511 Patent No. 96128171 is amended. The correction period: 99.11.1] stores a first voltage, and the second capacitor stores a second voltage. The operational amplifier has a positive phase input, an inverting input, a positive phase output, and an inverting output. The third capacitor is consumed between the inverting input terminal and the positive phase output terminal. The fourth capacitor is coupled between the non-inverting input terminal and the inverting output terminal. And during a second period of no overlap with the first period, the switch couples the first and second capacitors to the operational amplifier according to a digital signal, wherein when the first capacitor is connected in parallel with the third capacitor, The second capacitor is connected in parallel with the fourth capacitor, and when the first capacitor is connected in parallel with the fourth capacitor, the second capacitor is connected in parallel with the third capacitor. The present invention provides another digital analog converter including a first capacitor, a second capacitor, an operational amplifier, a first switch group, and a second switch group. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier has a positive phase input, an inverting input, a positive phase output, and an inverting output. During a second period that does not overlap with the first period, the first switch group connects the first capacitor in parallel with the operational amplifier according to a digital signal, and the second switch group according to the digital signal, the second The capacitor is connected in parallel with the operational amplifier, wherein, in the second period, when the first capacitor is coupled between the inverting input terminal and the positive phase output terminal, the second capacitor is coupled to the positive phase input terminal Between the inverting output terminals, when the first capacitor is coupled between the non-inverting input terminal and the inverting output terminal, the second capacitor is coupled to the inverting input terminal and the positive phase output terminal between. 0758-A32476TWFl(20100914) 6 Amendment of Patent Specification No. 962817] Date of amendment: 99.] 1.11 The present invention further provides a method. During the -first period, the conversion of the second converter is performed, and a second voltage is stored in the -first capacitor - the period - in the second capacitor. During the period with the first and second brothers, according to the -digit signal, the younger brother and the younger one capacitor will be combined with one. The hail contains: when 兮Μ — ♦ A °. Yaru' where the parallel phase is connected to 踹 and Λ "The valley device is coupled to one of the op amp's inverting input... the positive phase output: for the op amp - ^ 一 一 电 奋 接合 接合 接合 兮Μ Between the 6-phase input terminal and an inverting output terminal, the second L is connected to the operational amplifier, and the positive-phase wheel input terminal is placed between the 3= terminal ί The above-mentioned and other objects, features, and advantages of the present invention are apparently made easy to emphasize. The following is a detailed description of each of the following: Embodiments, and in conjunction with the drawings, [Embodiment] FIG. 1 is a schematic diagram of a digital analog converter of the present invention. As shown in the figure, the digital analog converter 10 includes capacitors CINP, CINN, CF1, CF2, and operation. The amplifier 11〇 and the switch are ~swi2. All the nodes with the symbol 0P are transferred to each other. All the nodes with the symbol 〇N are mutually consumed. The switches SW1~SW4 are controlled by the clock signal Φι. The switch sw SW3 Capacitor CINP is connected in series with reference voltage VREFp and common mode Between the voltage Vcm, the switch SW2' SW4 and the capacitor CINN are connected in series with the reference electrode 758-A32476TWF1 (20100914) 7 1339511 Revision date: 99.11.11 The patent specification No. 96128Π1 corrects the voltage between the voltage VREFN and the common mode voltage VcM. SW5 to SW8 are controlled by the clock signal % and the digital signal £). The switches SW9 to SW12 are controlled by the clock signal φ2 and the digital signal Dib. The digital signal Di is generated by a delta_sigma modnator 120. After the signal Di is inverted by the inverter 13〇, the digital signal Dib can be generated. In the present embodiment, the trigonometric integral adjustment “crossing” 120 generates a single bit (singie_bit) digital signal. In the first time, the switch SW1 ~SW4 is turned on, so that the charge stored in the capacitor CINP is (VREFp_VcM)*CINp, and the charge stored in the capacitor αΝΝ is (VREFN-Vcm)*CINn. During the first period, the switches SW5, SW6, SW9, and SW10 are based on the digits. The signals Di and Dib couple the capacitor CINp to the operational amplifier 110. Similarly, the switches SW1, SW8, swn and SW12 consume the capacitor CINn to the operational amplifier according to the digital signals Di and Dib. In this implementation, the operation amplifier M 11Q includes - positive phase input: two: inverting input terminal, one positive phase output terminal and - inverting output terminal. The electric Fin CF1 is connected to the inverting input terminal and positive Between the phase output terminals, and the capacitor is connected between the positive phase input terminal and the inverting output terminal. During the second phase of the clock, according to the digital signal, the switches SW5 and SW6 couple the capacitor CINP to the former visitor. 11Λ , ^ r Amplify gram] 〇 反相 inverting input and positive phase output. Therefore, Lei Jiao Cry, Ρ Yalian capacitor CF]. Similarly, the switches SW 7 and SW 8 are 々乂 λ γ 丄 上 运 运 u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u And the inverting output. Therefore 'electricity is CINn sub-capacitor CP). 1 58-A324 76TWF1 (20100914) 1339511 Revision date: 99.11.] 专利 No. 96128171 patent specification amendments in the second period, according to digital The signal Dib, the switches SW9 and sw] are connected to the non-inverting input terminal and the inverting output terminal of the operational amplifier 11G. Therefore, the capacitor CINp is connected in parallel with the capacitor cn. Similarly, the switches SWn and SW12 chop the capacitor according to the digital signal Dib (10) The surface is connected to the inverting input terminal of the amplifier and the positive phase output terminal. Because of this, the electric cell CINn parallel capacitor CF1. Assume that the clock signal Φι or % is high level, then the corresponding switch , the pulse signal φ] or % is the low level on time 'non-conducting corresponding switch., (5) ^ one ^ Bu clock signal "high level" makes the switch
:導通。因此，電容$ αΝρ所儲存的電荷為 (觀P-vCM)*CINp，而電容器 CIN (VREFN-VCMmNN。 子 ^ 何為 ^第二期間’時脈信號Φι為低位準，而時脈信 ^氏1玉數位信號^高位準’而數位信號⑽為 準蚪，則可導通開關SW5〜SW8而不導 _〜，4。因此，電容器CINp並聯電容器cn，而電容 並聯電容器CF2。正相輸出端的輸出信號係由儲 :-二：哪與電容器CF1的電荷所決定。也就是由 ΐ 一』間所得到的電荷（VREFp-vCM)*CINp再加上 二，t電容器C F1並聯後的電荷所決定。此時的二 广虎Φ2會一使電容器CF"皮充電。儲存在並聯的電容器 INp與電容器CF1的最終電荷即可決 出俨轳。& c ^ ]丨J，秀疋正相輸出端的輸 出U而反相輸出端的輸出信係由儲存在電容器CINi 0758-A32476TWFi(2〇i 00914) 1339511 第96128171號之專利說明書修正本 修正日期：99.11.11 與電容器CF2的電荷所決定。也就是由第二期間所得到 的電荷（VREFN-Vcm)*CINn再加上電容器CINn與電容器 CF2並聯後的電荷所決定。此時的時脈信號Φ2會使電容 器CF2被充電。儲存在並聯的電容器CINn與電容器CF2 的最終電荷即可決定反相輸出端的輸出信號。 同樣地，若時脈信號Φ2及數位信號Dib為高位準， 而時脈信號％及數位信號Di為低位準時，則可導通開 關SW9〜SW12而不導通SW卜SW4。因此，電容器CINP 並聯電容器CF2，而電容器CINn並聯電容器CF1。運算 放大器11 0的正相輸出端的輸出信號係由儲存在電容器 匸⑺〜與電容器CF1的電荷所決定。也就是由在第二期間 所得到的電荷（VREFN-Vcm)*CINn再加上電容器CINn與 電容器CF1並聯後的電荷所決定。此時的時脈信號Φ2 會使電容器CF1被充電。儲存在並聯的電容器CINn與電 容器CF1的最終電荷即可決定正相輸出端的輸出信號。 而反相輸出端的輸出信係由儲存在電容器CINp與電容器 CF2的電荷所決定。也就是由在第二期間所得到的電荷 (VREFP-Vcm)*CINp再加上電容器CINP與電容器CF2並 聯後的電荷所決定。此時的時脈信號Φ2會使電容器CF2 被充電。儲存在並聯的電容器CINP與電容器CF2的最終 電荷即可決定反相輸出端的輸出信號。: Conduction. Therefore, the charge stored by the capacitor $αΝρ is (p-vCM)*CINp, and the capacitor CIN (VREFN-VCMmNN. is the second period of the clock signal Φι is low level, and the clock signal is 1 jade digital signal ^ high level ' and the digital signal (10) is quasi-蚪, then the switches SW5 ~ SW8 can be turned on without _ ~, 4. Therefore, the capacitor CINp parallel capacitor cn, capacitor parallel capacitor CF2. output of the positive phase output The signal system is stored by: - 2: which is determined by the charge of the capacitor CF1. That is, the charge obtained by the ( 』 (VREFp-vCM) * CINp plus two, the charge of the t capacitor C F1 in parallel is determined. At this time, the Erguanghu Φ2 will charge the capacitor CF". The final charge of the capacitor INp and the capacitor CF1 stored in parallel can be determined. & c ^ ]丨J, the output of the positive output of the show The output signal of the U and the inverting output is determined by the charge stored in the capacitor CINi 0758-A32476TWFi (2〇i 00914) 1339511 No. 96128171, as amended by the date of the modification: 99.11.11 and the charge of the capacitor CF2. The charge obtained during the second period ( VREFN-Vcm)*CINn is determined by the charge of the capacitor CINn in parallel with the capacitor CF2. The clock signal Φ2 at this time causes the capacitor CF2 to be charged. The final charge stored in the parallel capacitor CINn and capacitor CF2 can be determined. Similarly, if the clock signal Φ2 and the digital signal Dib are at a high level, and the clock signal % and the digital signal Di are at a low level, the switches SW9 to SW12 can be turned on without turning on the SW SW4. Therefore, the capacitor CINP is connected in parallel with the capacitor CF2, and the capacitor CINn is connected in parallel with the capacitor CF1. The output signal of the positive phase output of the operational amplifier 110 is determined by the charge stored in the capacitor 匸(7)~ and the capacitor CF1. The obtained charge (VREFN-Vcm)*CINn is determined by the charge of the capacitor CINn in parallel with the capacitor CF1. The clock signal Φ2 at this time causes the capacitor CF1 to be charged. The final storage of the capacitor CINn and capacitor CF1 in parallel The charge determines the output signal at the output of the positive phase. The output signal from the inverting output is stored by the charge stored in capacitor CINp and capacitor CF2. The decision is made, that is, the charge (VREFP-Vcm)*CINp obtained in the second period is determined by the charge of the capacitor CINP connected in parallel with the capacitor CF2. At this time, the clock signal Φ2 causes the capacitor CF2 to be charged. The final charge of the capacitor CINP and capacitor CF2 in parallel determines the output signal at the inverting output.
由上述可知，藉由控制數位信號D i，可使得電容器 CINP並聯電容器CF1，以及使電容器CINn並聯電容器 CF2。另外，藉由控制數位信號Dib，可使得電容器CINP 0758-A32476TWF1(20100914) 10 1339511 修正曰期：99.1].]] 第961281 7]號之專利說明書修正本 並％電谷器CF2，以及使電容器CINN並聯電容器cF 1。 第2圖為本發明之數位類比轉換器之另一實施例。 第2圖相似於第1圖，不同之處在於，數位類比轉換器 20具有截波器（chopper)功能，用以將運算放大器21〇的 閃爍雜訊（flicker n〇ise)調變至—較高的頻帶（知叫如^ band)。被調變的閃爍雜訊便可被濾除。如圖所示，開關 SW5〜SWi2由時脈信號％、^、數位信號及As can be seen from the above, by controlling the digital signal D i , the capacitor CINP can be connected in parallel with the capacitor CF1 and the capacitor CINn can be connected in parallel with the capacitor CF2. In addition, by controlling the digital signal Dib, the capacitor CINP 0758-A32476TWF1(20100914) 10 1339511 can be modified by the following period: 99.1].]] The patent specification of the 961281 7] corrects the % electric grid device CF2, and makes the capacitor CINN shunt capacitor cF 1. Figure 2 is another embodiment of a digital analog converter of the present invention. Fig. 2 is similar to Fig. 1, except that the digital analog converter 20 has a chopper function for modulating the flicker noise of the operational amplifier 21 to - High frequency band (known as ^ band). The modulated flicker noise can be filtered out. As shown in the figure, the switches SW5 to SWi2 are composed of clock signals %, ^, and digital signals.
Dlb控制。時脈信號與0ehb互為反相。 、數位類比轉換器20並不需要額外增加開關以達到 截波器的功能。只需將開關S W5〜s w丨2原本的控制邏輯 加上時脈信號Φε1ι、〇>ehb ’便可將戴波㈣功能加進數位 類比轉換器中。藉由數位電路可控制開關⑽，因而可 執行布林函數。同樣地，開關 SW6〜SW12亦可由數位電路所控制。$ 了執行截波功Dlb control. The clock signal is inverted from 0ehb. The digital analog converter 20 does not require an additional switch to achieve the function of the chopper. The DAB function can be added to the digital analog converter by simply adding the clock control signal Φε1ι, 〇>ehb ’ to the original control logic of the switch S W5~s w丨2. The switch (10) can be controlled by a digital circuit so that the Boolean function can be executed. Similarly, switches SW6 through SW12 can also be controlled by digital circuitry. $ performed interception
j，、可將額外增加的數位電路整合於晶片(eh*)中，進而 卽省成本。 弟3圖為本發明之數位類比轉換器之另—實施例。 ^類比㈣E 3G用以處理多位^(_hi-bit)數位作 圖:，反相器331〜33n分別處理三角積分調^ 二所提供的數位信，以產生 所有符號為0?的節點均相互謝-起。 所有付號為ON的節點均相互減在一起。 在第，月間’開關SWl广及 脈信™制’用，容器⑽及㈣根^ 075S-A32476TWF1C20I00914) 1339511 修正日期：99.11.π 第96128171號之專利說明書修正本 考電壓VREFP以及共通模式電壓Vcm而充電，而電容器 CINN1及CINNn根據參考電壓VREFN以及共通模式電壓 Vcm而充電。 在第二期間’開關SW5PSW12,由數位信號' Dih及時脈信號φ2,用以使電容器αΝρ|並聯電容器 或CF2，以及使電容器CINni並聯電容器CF2或。 同樣地，開關SW5n〜SWl2n由數位信號Din、叫及時脈 信號％控制，用以使電容器CINpn並聯電容器cn或 CF2 ’以及使電容器C〖NNn並聯電容器CF2或CF1。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作些許之更動與 潤飾，因此本發明之保、護範圍當視後附之中請專利範圍 所界定者為準。 【圖式簡單說明】 第1圖為本發明之數位類比轉換器之示意圖。 D圖為本發明之數位類比轉換器之另一實施例。 第3圖為本發明之數位類比轉換器之另—實施例。 【主要元件符號說明】 10、20 ' 30 :數位類比轉換器； 、ciNPn、cmN1、 CINP、CINn、CF1、CF2、CINP丨 CINNn :電容器； 1 Π 0、2 ] 0 :運算放大器； 0758-A32476TWF1 (201 〇〇914) 1339511 第9612817〗號之專利說明書修正本 120、320 :三角積分調變器； SW1 〜SW12、SW5n〜SW12n :開 Φ 2、Φ eh、Φ chb :時脈信號； Di、Dib、Di】〜Din、Dib广Dibn 331〜33η :反相器。 修正日期：99.11.11 關； :數位信號； 0758-A32476TWFl(20100914) 13j, can add additional digital circuits to the chip (eh*), which saves costs. Figure 3 is another embodiment of the digital analog converter of the present invention. ^ Analogy (4) E 3G is used to process multiple bits of ^ (_hi-bit) digits: the inverters 331~33n respectively process the digital signals provided by the trigonometric integral modulation to generate all the nodes whose symbols are 0? Thank you. All nodes whose pay-numbers are ON are subtracted from each other. In the first month, the 'switch SWl wide and the pulse letter TM system', the container (10) and (four) root ^ 075S-A32476TWF1C20I00914) 1339511 Revision date: 99.11. π The patent specification No. 96128171 modifies the test voltage VREFP and the common mode voltage Vcm The charging is performed, and the capacitors CINN1 and CINNn are charged according to the reference voltage VREFN and the common mode voltage Vcm. In the second period 'switch SW5PSW12, the digital signal 'Dih and the pulse signal φ2' are used to make the capacitor αΝρ|parallel capacitor or CF2, and the capacitor CINni to be connected in parallel with the capacitor CF2. Similarly, the switches SW5n to SW12n are controlled by the digital signal Din, called the time pulse signal %, for the capacitor CINpn to be connected in parallel with the capacitor cn or CF2' and the capacitor CNNN to be connected in parallel with the capacitor CF2 or CF1. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection and protection of the present invention is subject to the scope defined in the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a digital analog converter of the present invention. D is another embodiment of the digital analog converter of the present invention. Figure 3 is a further embodiment of a digital analog converter of the present invention. [Main component symbol description] 10, 20 ' 30 : digital analog converter; ciNPn, cmN1, CINP, CINn, CF1, CF2, CINP 丨CINNn: capacitor; 1 Π 0, 2 ] 0 : operational amplifier; 0758-A32476TWF1 (201 〇〇 914) 1339511 Patent No. 9612817 Revised Edition 120, 320: Triangular Integral Modulator; SW1 ~ SW12, SW5n ~ SW12n: Open Φ 2, Φ eh, Φ chb: Clock Signal; Di, Dib, Di] ~ Din, Dib Wide Dibn 331~33η: Inverter. Amendment date: 99.11.11 off; : digital signal; 0758-A32476TWFl (20100914) 13