1321750 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種可支援多位元組資料連續讀取之儲存裝 置（像是快閃記憶體）’尤指一種以位址緩衝及輸出緩衝來 實現多位元組資料連續讀取之儲存裝置。 【先前技術】 鲁 在典型的微處理器與電腦系統中，常需整合不同功能之 電路構築方塊來實現電腦系統複雜、多樣化的功能。如何 在不同電路構築方塊間快速、有效地交換電子訊號、資料， 達成電腦系統應有的功能，也就成為現代資訊廠商研發的 =點之…尤其是現倾㈣狀發展輕絲低功率消 、低成本，也要減少電路構築方塊佈局所需的面積，使 奸相關研發所需考慮的因素更形複雜。 方參4第1圖。第1圖即為一典型電腦系統10之功能 …則透過—匯流橋晶片^晶 ^22A等等。中央處理器二來主儲存裝置邊控 作，記憶體18用來暫存中 控4糸統10之操 料、程式，儲存裝置20可以 J運作期間所需的資 快閃記憶體，用來支援電腦二：發性的儲存裝置，像是 、、 之非揮發性記憶體資 7 1321750 源。舉例來說，儲存裝置20可以是一快閃記憶體之義本輪 出入系統（BIOS) ’以儲存電腦系統10開機時所需執行^ 程式（像是各種檢查流程及運作參數之設定）。週^控 22A則用來控制週邊裝置22B (像是鍵盤、滑鼠等的輸入1 裝置）。經由晶片組14、匯流排16的連接，儲存農置 週邊控制器22A就能和中央處理器12相互交換資料，達& 電腦系統10的整體功能。 如第1圖所示’匯流排16是晶片組14與儲存裝置2〇 等電路構築方塊間重要的資料交換管道。在現代的電腦系、 統中’都希望能以較少的配線數來實現匯流排16。若匯凉 排16之配線數較少，晶片組14、儲存裴置2〇、週邊控制 器22A都僅需要較少的腳位(pin)就能連接於匯流排。 有效減少晶片組14、儲存裝置20等之佈局面積及功率 耗。舉例來說，由資訊廠商英特爾（intel)所制訂的低腳位數 (low-pin count，LPC)匯流排規格，就是針對配線數較少之 匯流排，制訂了在此種匯流排上資料交換之協定與格式。 請繼續參考第2® (並-併參考第i圖）。第2圖即為 第1圖之匯流排16以較少配線數來實現之典型示意圖（像 是以前述之低腳位數匯流排規格來實現時之示意圖）。在此 典型之實施例中，匯流排16可由六條配線來實現，於第2 圖中分別標示為配線CLK，以及FWH〇至FWH4。對匯流 8 1321750 排16來說，晶片組14可稱為主端（host)，可透過配線CLK 將時脈傳輸至儲存裝置20 (可稱為裝置端），控制主端、 裝置端間資料交換之時序；另外，主端亦可透過配線FWH4 來提示資料交換之開始與結束。主端、裝置端之間的資料， 主要是經由配線FWH0至FWH3(第2圖中記為FWH[3:0]) 來進行交換。 配線數少之匯流排雖然能減少主端、裝置端電路所需 的腳位數，但在進行資料（尤其是較多的資料）交換時， 勢必要以序列傳輸的方式依序地逐筆傳輸資料。為了要增 加效能，最好要能連續不中斷地傳輸複數筆資料。像是在 前述之低腳位數匯流排規格中，就為了對儲存裝置的快速 讀取而制訂有多位元組資料連續讀取之資料交換協定。請 參考第3圖（並一併參考第1圖及第2圖）。第3圖即為第 2圖中匯流排16在主端、裝置端之間進行多位元組資料連 • 續讀取時，其資料交換協定之訊號時序的示意圖；第3圖 之橫軸即為時間，由上而下則列示了各配線上資料交換的 情形。當裝置端為儲存裝置20時，主端、裝置端可以用第 3圖中所示意的時序將主端所指定的資料由儲存裝置20中 Ί買出，並傳輸回主端（也就是晶片組14)。 如第3圖所示，首先，在時點t0，主端將配線FWH4 ‘之訊號由高位準拉低至低位準，提示其要由匯流排16上進 9 1321750 • 行資料交換。在時點tl (也就是配線CLK上時脈的升緣）， 主端經由配線FWH0至FWH3發出一個四位元的訊號 START (各個配線發出一個位元的訊號，延續一個時脈週 期T )’心疋要交換資料的對象（此處應為儲存裝置2〇 )， 及要執行的運作（此處為讀取，要由儲存裝置2〇中讀取資 料），以開始主端與儲存裝置20間資料交換的程序。 _ 在時點t2 ’主端同樣以四配線FWH0至FWH3來發出 一個四位元的訊號IDSEL·，代表主端要由裝置端之儲存裝 置20的某個特定部份讀出資料。作為一資料館存的裝置， 儲存裝置20中的每一筆資料都有一對應的位址。接下來， 在時點t3至t4間，主端就會在配線FWH0至FWH3上以7 個週期T的時間發出一個28位元的訊號MADDR，指定其 所需資料的位址。每條配線FWH0至FWH3在一週期τ内 可傳輸一位元的資料，故4條配線在7週期内就可將一個 籲 28位元的位址傳遞至裝置端的儲存裝置20。接下來，在時 點t4，主端又將四位元的訊號MSIZE傳輸至裝置端，代表 其要連續讀出的資料有幾筆。在第3圖中的例子中，假設 訊號MADDR中的位址為AR(X)’而訊號MSIZE代表主端 要讀出四筆資料，那就代表主端要從儲存裝置20中連續讀 取位址為 AR(X)、AR(X+1)、AR(X+2)及 AR(X+3)等四筆各 一位元組的資料。換句話說，以主端訊號MADDR中之位 址為初始位址，配合訊號MSIZE中的資料數量，裴置端的 1321750 儲存裝置20應該就可以遞増算出所主端所需之各筆資料 的位址。 在時點t5、t6之間為兩週期τ之訊號TAR，也就是迴 轉週期（turn-around cycle)，代表匯流排16將由儲存裝置20 來主控，以將主端要求的資料由儲存裝置20回傳至主端。 在時點t6，儲存裝置20透過配線FWH0至FWH3發出四 位元的訊號SYNC，代表儲存裴置2〇開始主控資料的傳 輸。為了要實現高速資料交換的目的，接下來，儲存裝置 20應該就要能連續傳輸主端所要求的四筆資料。在時點 t7、t8之間’儲存裝置20以兩個週期T的時間傳輸位址 AR(X)的一位元組（8位元）資料，也就是訊號DATA1。 緊接著，又要在時點t8、t9間傳輸位址AR(X+1)的位元組 資料，也就是訊號DATA2。以此類推，儲存裝置20就要 在時點t7至til之間，以8個週期T的時間不中斷地依序 傳輸位址分別為AR(X)至AR(X+3)的四個位元組之資料 (即訊號DATA1至DATA4)，達成主端在時點tl至t5間 提出的要求。在時點til之後，又是兩個週期τ之訊號 TAR，完成與主端間的資料交換。 由以上描述可知，為了配合配線數較少之匯流排16， 裝置端的儲存裝置20應該要能像第3圖中所示的時序第i 圖樣，能計算連續遞增（或遞減）的位址，並能不中斷地 1321750 連續傳輸多位元組之資料，才能支援高效率的資料讀取協 定（也就是多位元組資料連續讀取）。不過，一般來說，習 知之儲存裴置都難以支援上述之多位元組讀取。進一步的 說明請參考第4圖。第4圖即為一習知儲存裳置30的功能 方塊示意圖。儲存裝置3〇可以是一快閃記憶體，其内設有 一介面電路24、一控制電路26、一位址計算模組28、一 解碼模組32、一記憶陣列％與複數個感測電路40。其中， φ 介面電路24電連於匯流排16，以從配線CLK、FWH0至 FWH4來收發訊號，與主端（未示於第4圖）交換資料。 控制電路26用來主控儲存裝置30之運作，位址計算模組 28則用來計算位址，將算出的位址輸出為訊號ADDRp。 在記憶陣列36中’設有複數個記憶單元38，各記憶單元 38用來記憶一位元的資料（譬如說是以具有浮動閘極之電 晶體來以非揮發性的方式記錄資料）。對應於記憶陣列36 的各個s己憶單元38’解碼模組32中則設有一列解碼器34A •及-灯解碼器34B，用來依據位址計算模組28提供的位址 訊號ADDRp解碼^該位址對應的各彳目記憶單元％，並使 這些記憶單元38將儲存的資料傳輸至各個感測電路4〇。 配口匯机排16的四條配線FWIi〇至請阳，儲存裝置 30中也設有四個感測電路4〇，各感測電路4〇彳分別將一 記憶早元3 8傳輪過來的資粗成、y u . J貝枓感測、頃取出來，並將資料傳 輸至一條對應的配線上。被t 洗如弟4圖中所示，各感測電路 12 1321750 40的基本構造相同，其中可設有一感測放大器42、反相器 I、以及以互補金氧半電晶體形成之輸出級；由一記憶單元 ' 36傳來的資料會以電壓訊號之形式傳輸至感測電路40 中，並在感測放大器42和一參考電壓Vr相互比較，以決 定該記憶單元中儲存的資料是數位「0」或「1」的位元， 再經由反相器I、偏壓於電壓Vd及G的互補金氧半電晶體 形成對應之訊號sAOUTp，傳輪至介面電路24，以將一位 元之資料傳輸至對應之配線（也就是配線FWH0至FWH3 •其中之一)。 不過’若要以習知儲存裝置30來實現第3圖中多位元 組資料連續讀取之協定，則尚有技術上的瓶頸。請參考第 5圖（及第4圖）。第5圖即為第4圖中儲存裝置30實施 資料讀取時之時序示意圖；第5圖的橫軸為時間。為了方 便討論’第5圖中也繪出了多位元組連續資料讀取之時序 • 協定，作為比較（也請一併參考第3圖）。依據協定，主端 會在時點t2及t4間以七個週期τ之時間傳輸共28位元之 訊號MADDR，作為28位元之初始位址AR(X)。在時脈之 升緣觸發下，儲存裴置30應可經由介面電路24、控制電 路26而在時點t3b取得這28位元的訊號MADDR，並傳輪 至位址計算模組28，也就是訊號ADDRp中在時點t3b之 後的位址AR(X)。由協定規範的時序可看出，儲存裝置3〇 應在時點t7開始提供位址ar(x)對應資料的前四個位元， 13 1321750 因此解碼模組32可在時點t3b與t6之間進行解碼，使位址 AR(X)之資料前四位元對應的四個記憶單元能在時點t6開 始將其儲存的一位元資料分別傳輸至四個感測模組40。在 時點t7，各個感測模組40完成資料的感測，能將其讀取之 位元輸出，即訊號SAOUTp中的一位元資料Px。集合四個 感測模組40傳回介面電路24的一位元資料，就能在時點 t7回傳位址AR(X)資料的前四位元，以符合協定中規範的 時序。 然而，依據協定規範之時序，習知之儲存裝置30應該 要在時點t7p不中斷地繼續傳輸位址AR(X)資料的後四個 位元。此時習知之儲存裝置30就會發生困難，因為習知儲 存裝置30必需要延遲一時段Tpl才能繼續讀出這後四個位 元。要讀取後四個位元之資料，習知儲存裝置30必需重新 解碼出位址AR(X)資料後四個位元對應的記憶單元，重新 • 設定各個感測模組40，再對這四個記憶單元中儲存的一位 元資料Qx進行感測；因此，習知儲存裝置30可能要延遲 到時點t8才能提供後四個位元的資料。這樣一來，就不能 符合協定中多位元組資料連續讀取之規範了。 除此之外，在多位元組資料連續讀取的過程中，習知儲 存裝置30還有位址計算的問題。如前面所描述過的，在處 理完位址AR(X)的資料後，儲存裝置30應該要能不中斷地 14 1321750 繼續傳輸次一位址AR(X+1)的資料。如第5圖所示，由於 解碼模組32要在時點t7p解碼出位址AR(X)後四個位元對 應的記憶單元，故在時點t8，位址計算模組28才能開始由 位址AR(X)遞增計算出次一位址AR(X+1)。要計算出位址 AR(X+1)，位址計算模組28還要另外耗費時段Tp2之時 間。就如前面討論過的，各位址AR(X)、AR(X+1)為28位 元之位址，即使只是遞增1，還是會涉及28個位元間逐一 進位之計算，故需耗費相當之時間。因此，到了時點t8p， 位址計算模組28才能計算出次一位址AR(X+1)。接著，在 時點t9,解碼模組32也才能再根據位址AR(X+1)讓感測模 組40開始感測對應之四個記憶單元，提供位址AR(X+1) 資料的前四個位元（也就是訊號SAOUTp中的資料Pxl )。 由第5圖中可看出，在習知儲存裝置3〇中，由於位址計算 所需的時間會直接影響資料感測的時序，習知儲存裝置30 就無法在處理完位址AR(X)之資料傳輸後不中斷地繼續處 理位址AR(X+1)之資料’也就無法達到協定中多位元組資 料連續讀取之要求。 ’ 综合以上數種因素，都使得習知儲存裝置3〇無法有效 地支援多位元組資料連續讀取之協定，降低了資料交換的 效率，進而影響電腦系統整體工作之效能。 15 1321750 【發明内容】 因此，本發明之主要目的，即是要提出一種儲存裝置的 改進架構，能有效地支援多位元組資料連續讀取之協定， 增進資料交換之效能，克服習知技術的缺點。 在本發明之較佳實施例中，係以一位址計算模組配合一 位址緩衝模組來解決位址計算時間的問題。當位址計算模 組將一位址計算出來後，就能將其儲存至位址緩衝模組， 讓解碼模組能依據位址缓衝模組中的位址來解碼出對應的 記憶單元；在此同時，位址計算模组因為已將位址儲存至 位址缓衝模組，所以能隨即開始計算次一位址。換句話說， 當解碼模組在對一位址解碼其對應之記憶單元時，位址計 算模組已經在計算次一位址。這樣一來，等儲存裝置處理 完該位址之資料讀取後，就能緊接著處理次一位址之資料 讀取。 另一方面，本發明也使用了輸出緩衝模組之設計來支援 位元組之讀取。雖然在多位元組資料連續讀取之協定下， 一位元組之資料係在兩時脈週期之時間中分別傳輸兩筆之 四位元資料，但本發明之儲存裝置一次就可讀出八位元之 所有資料，再由輸出緩衝模組安排而將這八位元資料分別 在兩個時脈週期中以各四位元的方式依次傳輸出去。經由 上述的安排，本發明儲存裝置就能支援多位元資料連續讀 16 1321750 . 取之協定，在低配線數之匯流排上以高效能來交換資料。 【實施方式】 明參考第6圖。第6圖即為本發明儲存裝置5〇 一實施 例之功能方塊示意圖。本發明儲存裝置可以是一快閃記憶 體（像是電腦系統中快閃記憶體之基本輸出入系統，flash BIOS)，其内設有一介面電路54、一控制電路％、一位址 觸發模組58A、一輸出觸發模組58B、一位址計算模組 • 60A、一位址緩衝模組60B、一解碼模組62、一記憶陣列 66及一感測模組70。介面電路54可以透過匯流排1〇〇的 配線CLK、FWH0-FWH4來和一主端（像是第2圖中的晶 另組，此處並未顯示於第6圖）交換資料。控制電路允用 來主控儲存裝置50的運作。在進行多位元組連續資料讀取 時，位址觸發模組58A可以用訊號CK—ADS控制位址計算 模組60A，以觸發位址計算模組6〇A開始計算遞增的各個 鲁位址，並輸出為訊號ads。另外，位址觸發模組58A也可 用訊號ADSLAT來觸發位址緩衝模組接收位址計算模 組60A傳來的位址，並加以儲存（鎖定），以便將位址以訊 號ADDR傳輸至解碼模組62。 記憶陣列66中設有複數個排列為矩陣的記憶單元68， 各記憶單元68用來記錄一位元的資料。舉例來說，記憶單 元68可以包括有具有浮動閘極的電晶體，用來以非揮發性 17 的=式儲存資料。對應於記憶陣列66，解碼模組 言又有-列解碼器64A及—行解碼器6 〜中也 60B中儲存的位址，解巧模/ 址緩衝模組 洲立址㈣換、组62就能使該位址對 記憶早疋68輸出其所儲存的—位元資料。在以下討論的每 施例中’位址緩衝模組_中儲存的—個位址可對應於: 個位元組(byte)的資料；換句話說，有八個記憶單元^、皆 對應於此-位址。而在本發明中，解碼模組幻可根據^立 址解碼出所有人個與其對應之記憶單元，使這人個記 元同時輸出其記錄的—位元#料。對應於會在同—時間= 輸出資料的八個記憶單元，本發明的感測模組7〇中也: 四個輸出緩衝模組72 ;各個輸出緩衝模板々2用來接收X兩有 個s己憶單元輸出的資料。而輸出觸發模組58b 丨J用訊號 SASEL、HNBSEL、OBLAT等來觸發控制各個輪出緩衝模 組58B ’使輸出缓衝模組58B^r在兩個時脈週期的時間内 逐一將兩個記憶單元的資料傳輸至介面電路，作為由儲存 裝置50讀取的資料。請參考第7圖（並—併參考第6圖）。 各輸出缓衝模組72的基本構造相同，而第7圖即繪出了本 發明一輸出緩衝模組72實施例的示意圖（並連帶繪出其與 記憶陣列66聯合配置的情形）。 在本發明的一個輸出緩衝模板72中，設有兩個感測放 大器74Α、74Β、以互補金氧半電晶體形成之傳輸閘76Α、 76Β、78、80，以反相器I連接而成的鎖定電路、82Β 1321750 與84，以及偏壓於電壓Vd、G之間、以互補金氧半電晶體 1 形成之輸出級。兩感測放大器74A、74B分別用來感測一 記憶單元傳來的資料，並分別輸出為對應的訊號SAOUT1 及SAOUT2。各傳輸閘作為傳輸電路，其中傳輸閘76A、 76B接收訊號SASEL(及其反相訊號）之控制，傳輸閘78、 80則分別接收訊號OBLAT、HNBSEL (及對應反相訊號） 之控制。最後，輸出級輸出的訊號SAOUT3即可作為一配 g 線FWH[n]上的輸出訊號（配合四個輸出缓衝電路72，η 即分別為0到3)，輸出儲存裝置50讀出的資料。 關於本發明儲存電路50運作的情形，請參考第8圖（及 第3圖、第6圖與第7圖）。第8圖即為儲存電路50實現 第3圖中多位元組連續資料讀取之資料交換協定時，各相 關訊號之時序示意圖；第8圖之橫轴即為時間。就如第3 圖及相關討論中敘述過的，在多位元組資料連續讀取的協 # 定中’主端會透過匯流排上的配線FWH[3:0]在時點tl、t2 分別傳輸一訊號START (第8圖中標為S)、IDSEL，使儲 存裝置50的控制電路56準備讀取資料。在時點t3到t4 的七個週期T之間’主端會以28位元的訊號MADDR將其 所要讀取資料的初始位址（也就是位址AR(X))傳輸給儲 存裝置50,並將連續讀取之資料位元組數目以訊號MSIZE (第8圖中標示為M)傳輸給儲存裝置50 ;跟第3圖中的 例子一樣’在第8圖討論的例子中，也假設主端要求連續 19 1321750 四個位元組的資料。在兩個週期T的TAR訊號及一週期Τ 之SYNC訊號（第8圖中標示為SC)之後，儲存裝置50 就要從時點t7開始，在接下來以八週期T的時間連續向主 端提供位址分別在AR(X)至AR(X+3)的四個位元組的資 料。 如第8圖所示，在升緣觸發的情形下，儲存裝置50可 在時點t3b取得訊號MADDR所有的28個位元，使位址計 算模組60A、位址緩衝模組60B都能在時點t3b取得位址 AR(X)。時點tb3距離要開始傳輸資料的時點t7還有五個 週期T之時間，故儲存裝置5〇的解碼模組62有充裕的時 間來進行解碼，並在時點t5m，開始讓位址AR(X)對應的 八個記憶I元同時向對應的輸出緩衝模組傳輸其所儲存的 資料。如第8目（及第7圖）所示，在每一輸出緩衝電路 72中，訊號SA〇UT1、SA〇UT2代表其對應的感測放大器 74A 74B自於點t5m開始感測對應記憶單元傳來的資 料，並在時點t6穩定地讀出資料内容（即一位元的資料1321750 IX. Description of the Invention: [Technical Field] The present invention provides a storage device (such as a flash memory) capable of supporting continuous reading of multi-byte data, especially an address buffer and an output buffer. A storage device for continuously reading a plurality of bytes of data. [Prior Art] In a typical microprocessor and computer system, it is often necessary to integrate circuit blocks of different functions to realize the complex and diverse functions of the computer system. How to quickly and efficiently exchange electronic signals and data between different circuit building blocks to achieve the functions that a computer system should have, and it has become a point of research and development by modern information vendors... especially in the current development of (four) development of light wire low power consumption, At a low cost, it is also necessary to reduce the area required for the circuit to construct the block layout, which complicates the factors required for research and development. Fangshen 4 Figure 1. Figure 1 shows the function of a typical computer system 10 ... then through - the bridge chip ^ crystal ^ 22A and so on. The central processing unit 2 controls the main storage device, and the memory 18 is used to temporarily store the control and program of the central control system 10. The storage device 20 can support the flash memory required during the operation of the J. Computer 2: a hair storage device, like the non-volatile memory source 7 1321750 source. For example, the storage device 20 can be a flash memory (BIOS) to store the execution of the computer system 10 (such as various inspection processes and operational parameter settings). The peripheral control 22A is used to control the peripheral device 22B (such as an input 1 device such as a keyboard or a mouse). Through the connection of the wafer set 14 and the bus bar 16, the storage farm peripheral controller 22A can exchange data with the central processing unit 12 to achieve the overall function of the computer system 10. As shown in Fig. 1, the bus bar 16 is an important data exchange pipe between the circuit packs such as the chip set 14 and the storage device 2A. In modern computer systems, it is desirable to implement the busbar 16 with a small number of wires. If the number of wirings of the cooling row 16 is small, the wafer set 14, the storage device 2, and the peripheral controller 22A need only a small number of pins to be connected to the bus bar. The layout area and power consumption of the wafer set 14, the storage device 20, and the like are effectively reduced. For example, the low-pin count (LPC) busbar specification developed by the information manufacturer Intel (intel) is to exchange data on such busbars for busbars with a small number of wires. Agreement and format. Please continue to refer to Section 2® (and - and refer to Figure i). Fig. 2 is a typical diagram of the busbar 16 of Fig. 1 implemented with a small number of wires (as shown in the aforementioned low pin count busbar specification). In this exemplary embodiment, bus bar 16 can be implemented by six wires, labeled as wiring CLK, and FWH〇 to FWH4, respectively, in Figure 2. For the bus 8 1321750 row 16, the chip set 14 can be called a host, and can transmit the clock to the storage device 20 (which can be called the device end) through the wiring CLK, and control the data exchange between the main end and the device end. Timing; In addition, the master can also prompt the beginning and end of data exchange through the wiring FWH4. The data between the master and the device is mainly exchanged via the wiring FWH0 to FWH3 (referred to as FWH[3:0] in Fig. 2). Although the number of pins with a small number of wires can reduce the number of pins required for the main-end and device-side circuits, when data (especially more data) is exchanged, it is necessary to sequentially transmit the data in sequence. data. In order to increase performance, it is best to transfer multiple data continuously without interruption. For example, in the aforementioned low-foot number busbar specification, a data exchange protocol for continuous reading of multi-byte data is prepared for fast reading of the storage device. Please refer to Figure 3 (and refer to Figure 1 and Figure 2 together). Figure 3 is a schematic diagram of the signal timing of the data exchange protocol when the bus bar 16 in the second figure performs multi-byte data connection between the main terminal and the device end; the horizontal axis of the third figure is For the time, from top to bottom, the situation of data exchange on each wiring is listed. When the device end is the storage device 20, the main terminal and the device end can use the timing illustrated in FIG. 3 to purchase the data designated by the main terminal from the storage device 20 and transmit it back to the main end (that is, the chip set). 14). As shown in Fig. 3, first, at time t0, the main terminal pulls the signal of the wiring FWH4 ‘from the high level to the low level, prompting it to be switched from the bus 16 to the 13 1321750. At time t1 (that is, the rising edge of the clock on the wiring CLK), the main terminal sends a four-bit signal START via wiring FWH0 to FWH3 (each wiring emits a bit signal, continuing a clock cycle T) The object to be exchanged (here should be the storage device 2), and the operation to be performed (here, read, to be read from the storage device 2) to start between the primary end and the storage device 20 The procedure for data exchange. _ At the time t2 ′, the master also sends a four-bit signal IDSEL· with four wires FWH0 to FWH3, indicating that the master is to read data from a specific part of the storage device 20 on the device side. As a repository device, each of the data in the storage device 20 has a corresponding address. Next, between time points t3 and t4, the master will issue a 28-bit signal MADDR on the lines FWH0 to FWH3 for 7 cycles T, specifying the address of the desired data. Each of the wirings FWH0 to FWH3 can transmit one-bit data in one cycle τ, so that four wirings can transmit a 28-bit address to the storage device 20 on the device side in seven cycles. Next, at time t4, the master transmits the four-bit signal MSIZE to the device side, indicating that there are several pieces of data to be continuously read. In the example in FIG. 3, it is assumed that the address in the signal MADDR is AR(X)' and the signal MSIZE represents that the master wants to read four pieces of data, which means that the master wants to continuously read bits from the storage device 20. The address is four pieces of each tuple such as AR (X), AR (X+1), AR (X+2), and AR (X+3). In other words, with the address in the primary signal MADDR as the initial address and the amount of data in the signal MSIZE, the 1321750 storage device 20 on the set side should be able to calculate the bits of the data required by the primary end. site. Between the time points t5 and t6, the signal TAR of the two periods τ, that is, the turn-around cycle, represents that the bus bar 16 will be mastered by the storage device 20 to return the data requested by the primary terminal from the storage device 20. Pass to the main end. At time t6, the storage device 20 sends a four-bit signal SYNC through the wires FWH0 to FWH3 to start the transmission of the master data on behalf of the storage device 2. In order to achieve the purpose of high-speed data exchange, next, the storage device 20 should be able to continuously transmit the four pieces of data required by the main terminal. Between the time points t7 and t8, the storage device 20 transmits a one-tuple (8-bit) data of the address AR(X) at two cycles T, that is, the signal DATA1. Then, the byte data of the address AR(X+1), that is, the signal DATA2, is transmitted between time points t8 and t9. By analogy, the storage device 20 transmits four bits of addresses AR(X) to AR(X+3) sequentially between the time points t7 and til with an uninterrupted time of 8 cycles T. The group's data (ie, signal DATA1 to DATA4) meets the requirements of the master between time points t1 and t5. After the time point til, the signal TAR of two cycles τ is completed, and the data exchange with the master end is completed. As can be seen from the above description, in order to match the bus bar 16 with a small number of wires, the storage device 20 on the device side should be able to calculate the continuously increasing (or decreasing) address like the timing chart i shown in FIG. The 1321750 can continuously transmit data of multiple bytes in order to support efficient data reading protocol (that is, continuous reading of multi-byte data). However, in general, it is difficult for conventional storage devices to support the above-mentioned multi-byte reading. Please refer to Figure 4 for further instructions. Figure 4 is a block diagram showing the function of a conventional storage shelf 30. The storage device 3 can be a flash memory, and is provided with an interface circuit 24, a control circuit 26, an address calculation module 28, a decoding module 32, a memory array % and a plurality of sensing circuits 40. . The φ interface circuit 24 is electrically connected to the bus bar 16 to transmit and receive signals from the wirings CLK, FWH0 to FWH4, and exchanges data with the main terminal (not shown in Fig. 4). The control circuit 26 is used to control the operation of the storage device 30. The address calculation module 28 is used to calculate the address and output the calculated address as the signal ADDRp. A plurality of memory cells 38 are provided in the memory array 36, and each memory cell 38 is used to store data of one bit (e.g., a cell having a floating gate to record data in a non-volatile manner). A decoder decoder 34A and a lamp decoder 34B are provided in the decoding module 32 corresponding to the memory array 36 for decoding the address signal ADDRp provided by the address calculation module 28. The address corresponds to each of the memory cells %, and causes the memory cells 38 to transfer the stored data to the respective sensing circuits 4A. The four wirings of the matching port row 16 are FWIi〇 to the sun, and the storage device 30 is also provided with four sensing circuits 4〇, and each sensing circuit 4〇彳 respectively transmits a memory of the early memory. Thick, yu. J 枓 枓 sensing, is taken out, and the data is transmitted to a corresponding wiring. The basic structure of each sensing circuit 12 1321750 40 is the same, wherein a sense amplifier 42, an inverter I, and an output stage formed by a complementary metal oxide semiconductor can be provided; The data transmitted from a memory unit '36 is transmitted to the sensing circuit 40 in the form of a voltage signal, and the sense amplifier 42 and a reference voltage Vr are compared with each other to determine that the data stored in the memory unit is digital. The bit of 0" or "1" is further formed into a corresponding signal sAOUTp via the inverter I and the complementary MOS transistor biased to the voltages Vd and G, and is transmitted to the interface circuit 24 to The data is transferred to the corresponding wiring (that is, wiring FWH0 to FWH3 • one of them). However, there is a technical bottleneck in the conventional storage device 30 to implement the agreement for continuous reading of multi-byte data in Figure 3. Please refer to Figure 5 (and Figure 4). Fig. 5 is a timing chart when the storage device 30 performs data reading in Fig. 4; the horizontal axis of Fig. 5 is time. In order to facilitate the discussion, the timing of multi-byte continuous data reading is also depicted in Figure 5, as a comparison (see also Figure 3). According to the agreement, the master transmits a total of 28 bits of signal MADDR at a time of seven cycles τ between time points t2 and t4 as the initial address AR(X) of 28 bits. Under the trigger of the rising edge of the clock, the storage device 30 should obtain the 28-bit signal MADDR at the time point t3b via the interface circuit 24 and the control circuit 26, and transmit to the address calculation module 28, that is, the signal. The address AR(X) in the ADDRp after the time point t3b. As can be seen from the timing of the protocol specification, the storage device 3 should provide the first four bits of the data corresponding to the address ar(x) at time t7, 13 1321750. Therefore, the decoding module 32 can be performed between the time points t3b and t6. The decoding enables the four memory units corresponding to the first four bits of the data of the address AR(X) to start transmitting one of the stored meta-data to the four sensing modules 40 at time t6. At time t7, each sensing module 40 completes the sensing of the data, and can output the bit to be read, that is, a bit data Px in the signal SAOUTp. By integrating the four sensing modules 40 back to the one-bit data of the interface circuit 24, the first four bits of the address AR(X) data can be returned at time t7 to conform to the timing of the specifications in the protocol. However, in accordance with the timing of the protocol specification, the conventional storage device 30 should continue to transmit the last four bits of the address AR(X) data without interruption at time t7p. At this time, the conventional storage device 30 is difficult because the conventional storage device 30 must delay the time period Tpl to continue reading the last four bits. To read the data of the last four bits, the conventional storage device 30 must re-decode the memory unit corresponding to the four bits after the address AR(X) data, and re-set each sensing module 40, and then One bit of metadata Qx stored in the four memory cells is sensed; therefore, the conventional storage device 30 may have to delay until time t8 to provide the last four bits of data. In this way, the specification of continuous reading of multiple bytes of data in the agreement cannot be met. In addition to this, in the process of continuous reading of multi-byte data, the conventional storage device 30 also has a problem of address calculation. As described above, after processing the data of the address AR(X), the storage device 30 should continue to transmit the data of the secondary address AR(X+1) without interruption. As shown in FIG. 5, since the decoding module 32 decodes the memory unit corresponding to the four bits after the address AR(X) at the time point t7p, the address calculation module 28 can start from the address at the time point t8. AR(X) incrementally calculates the secondary address AR(X+1). To calculate the address AR(X+1), the address calculation module 28 additionally consumes the time period Tp2. As discussed above, the addresses AR(X) and AR(X+1) are the addresses of 28 bits. Even if it is only incremented by 1, it will involve the calculation of the bit-to-bit between 28 bits, so it costs a lot. Time. Therefore, at time t8p, the address calculation module 28 can calculate the secondary address AR(X+1). Then, at time t9, the decoding module 32 can also cause the sensing module 40 to start sensing the corresponding four memory units according to the address AR(X+1), and provide the address AR(X+1) data before. Four bits (that is, the data Pxl in the signal SAOUTp). As can be seen from FIG. 5, in the conventional storage device 3, since the time required for the address calculation directly affects the timing of the data sensing, the conventional storage device 30 cannot process the address AR (X). After the data transmission, the data of the address AR(X+1) is continuously processed without interruption, and the requirement for continuous reading of the multi-byte data in the agreement cannot be achieved. The combination of the above factors has made the conventional storage device 3〇 unable to effectively support the agreement of continuous reading of multi-byte data, which reduces the efficiency of data exchange and thus affects the overall efficiency of the computer system. 15 1321750 SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an improved architecture of a storage device, which can effectively support the agreement of continuous reading of multi-byte data, improve the efficiency of data exchange, and overcome the conventional technology. Shortcomings. In the preferred embodiment of the present invention, the address calculation module cooperates with an address buffer module to solve the problem of address calculation time. After the address calculation module calculates an address, it can be stored in the address buffer module, so that the decoding module can decode the corresponding memory unit according to the address in the address buffer module; At the same time, since the address calculation module has stored the address to the address buffer module, the next address can be calculated. In other words, when the decoding module decodes its corresponding memory unit for the address, the address calculation module is already calculating the secondary address. In this way, after the storage device processes the data of the address, the data of the next address can be read. On the other hand, the present invention also uses the design of the output buffer module to support the reading of the byte. Although the data of one tuple transmits two digits of data in two time periods during the two-clock cycle under the agreement of continuous reading of multi-byte data, the storage device of the present invention can be read at one time. All the data of the octet is arranged by the output buffer module, and the octet data is sequentially transmitted in the form of four bits in two clock cycles. Through the above arrangement, the storage device of the present invention can support continuous reading of multi-bit data 16 1321750. It is agreed to exchange data with high efficiency on the bus with low wiring number. [Embodiment] FIG. 6 is referred to. Fig. 6 is a functional block diagram showing an embodiment of the storage device 5 of the present invention. The storage device of the present invention may be a flash memory (such as a flash input memory system in a computer system, flash BIOS), and has an interface circuit 54, a control circuit %, and an address trigger module. 58A, an output trigger module 58B, an address calculation module 60A, an address buffer module 60B, a decoding module 62, a memory array 66, and a sensing module 70. The interface circuit 54 can exchange data with a main terminal (such as the crystal set in Fig. 2, which is not shown here in Fig. 6) through the wiring CLK, FWH0-FWH4 of the bus bar 1〇〇. The control circuit is enabled to host the operation of the storage device 50. When performing multi-byte continuous data reading, the address triggering module 58A can use the signal CK-ADS control address calculation module 60A to trigger the address calculation module 6A to start calculating the incremental Lu addresses. And output as signal ads. In addition, the address triggering module 58A can also use the signal ADSLAT to trigger the address buffer module to receive the address from the address calculation module 60A, and store (lock) the address to transmit the address to the decoding mode with the signal ADDR. Group 62. The memory array 66 is provided with a plurality of memory cells 68 arranged in a matrix, and each memory unit 68 is used to record data of one bit. For example, memory unit 68 can include a transistor having a floating gate for storing data in a non-volatile 17 version. Corresponding to the memory array 66, the decoding module has the address stored in the column decoder 64A and the row decoder 6~60B, and the decoding module/address buffer module is located at the fourth address (four), and the group 62 can make The address outputs its stored-bit data to memory early 68. In each of the examples discussed below, the address stored in the 'address buffer module _ may correspond to: one byte (byte) of data; in other words, eight memory cells ^, all corresponding to This - address. In the present invention, the decoding module can decode all the memory units corresponding to the person according to the address, so that the person records the bits of the record at the same time. Corresponding to the eight memory cells that will be in the same time = output data, the sensing module 7 of the present invention also: four output buffer modules 72; each output buffer template 々 2 is used to receive X two s I have recalled the data output from the unit. The output trigger module 58b 丨J uses the signals SASEL, HNBSEL, OBLAT, etc. to trigger and control each of the wheel buffer modules 58B' to cause the output buffer module 58B^r to store two memories one by one in two clock cycles. The data of the unit is transmitted to the interface circuit as data read by the storage device 50. Please refer to Figure 7 (and - and refer to Figure 6). The basic construction of each of the output buffer modules 72 is the same, and FIG. 7 is a schematic diagram showing an embodiment of an output buffer module 72 of the present invention (and the case where it is combined with the memory array 66). In an output buffer template 72 of the present invention, two sense amplifiers 74A, 74A, and transmission gates 76Α, 76Β, 78, 80 formed by complementary MOS transistors are connected by inverters I. A locking circuit, 82 Β 1321750 and 84, and an output stage formed between the voltages Vd, G and the complementary MOS transistor 1 are formed. The two sense amplifiers 74A and 74B are respectively used to sense the data transmitted from a memory unit and output the corresponding signals SAOUT1 and SAOUT2, respectively. Each of the transmission gates serves as a transmission circuit in which the transmission gates 76A, 76B receive the control of the signal SASEL (and its inverted signal), and the transmission gates 78, 80 receive the control of the signals OBLAT, HNBSEL (and corresponding inverted signals), respectively. Finally, the signal SAOUT3 outputted by the output stage can be used as an output signal on the g line FWH[n] (with four output buffer circuits 72, η being 0 to 3 respectively), and the data read by the storage device 50 is output. . For the operation of the storage circuit 50 of the present invention, please refer to Fig. 8 (and Figs. 3, 6, and 7). Fig. 8 is a timing chart of the related signals when the storage circuit 50 implements the data exchange protocol for multi-byte continuous data reading in Fig. 3; the horizontal axis of Fig. 8 is time. As described in Figure 3 and related discussion, in the co-determination of continuous reading of multi-byte data, the main terminal transmits separately through the wiring FWH[3:0] on the bus bar at time points t1 and t2. A signal START (marked S in Figure 8), IDSEL, causes the control circuit 56 of the storage device 50 to prepare for reading data. Between the seven periods T of time t3 to t4, the primary end transmits the initial address (ie, the address AR(X)) of the data to be read to the storage device 50 with the signal MADDR of 28 bits. The number of consecutively read data bytes is transmitted to the storage device 50 by the signal MSIZE (labeled M in Figure 8); as in the example of Figure 3, 'in the example discussed in Figure 8, the primary is also assumed A total of 19 1321750 four-byte data is required. After the TAR signal of two periods T and the SYNC signal of one period (labeled as SC in FIG. 8), the storage device 50 starts from the time point t7 and continues to provide the main terminal for eight cycles T. The data of the four bytes of the AR (X) to AR (X+3) are respectively located. As shown in FIG. 8, in the case of the rising edge triggering, the storage device 50 can obtain all 28 bits of the signal MADDR at the time point t3b, so that the address calculation module 60A and the address buffer module 60B can be at the time point. T3b obtains the address AR(X). At the time point tb3, there is still five cycles T at the time point t7 at which the data is to be transmitted. Therefore, the decoding module 62 of the storage device 5 has sufficient time for decoding, and at the time point t5m, the address AR(X) is started. The corresponding eight memory I elements simultaneously transmit their stored data to the corresponding output buffer module. As shown in the eighth (and FIG. 7), in each output buffer circuit 72, the signals SA〇UT1, SA〇UT2 represent their corresponding sense amplifiers 74A 74B from the point t5m to sense the corresponding memory unit transmission. The information coming, and the data content is steadily read at time t6 (ie, one yuan of data)
Ax、Bx)。集合四個輸出緩衝模組72共人個感測放大器所 -起讀取出㈣八個位元:轉，狀位址ar(x)對應的一 位元組資料。 來在柃點t6m，輸出觸發模組58B開始將訊號 SASEL由低位準提面至純準，使原本關閉不導通的傳輸 20 1321750 閘76A、76B皆導通，將感測放大器74A、74B感測出來的 資料分別存入（鎖定）至鎖定電路82A、82B。依據多位元 組資料連續讀取之協定’到了時點t7，儲存電路5〇應該要 輸出位址AR(X)對應資.料的前四個位元。所以，到了時點 t7，本發明中之輸出觸發模組58B就會將訊號〇BLAT之位 準升南’使原本不導通的傳輸閘78導通，將儲存於鎖定電 路82A中的資料（也就是資料Αχ)傳輸至鎖定電路84， • 並由經由輸出級傳輸出去。集合四個輸出緩衝電路在時點 t7分別開始輸出的一位元資料’就能向主端傳輸位址AR(X) 對應資料的前四個位元。 接續訊號OBLAT在時點t7至t7a間對傳輸閘78的導 通控制’輸出觸發模組58B會在時點t7a、t7b之間將訊號 HNBSEL提升至高位準’導通傳輸閘8〇，將儲存於鎖定電 路82B中的資料（也就是資料Bx)傳輸至鎖定電路82八； 籲 在時點t7a、t7b之間，原本儲存於鎖定電路82A的資料 Αχ已經先被儲存至鎖定電路84 (由於訊號〇BLAT之導 通），故可將鎖定電路82Β中的資料Βχ遞移至鎖定電路 82Α。到了時點t7b’訊號OBSLAT又變為高位準，將傳輸 閘78導通，使鎖定電路82B中的資料Bx可傳輸至鎖定電 路84中並加以輸出。集合四個輪出緩衝模組72在時點t7b 輸出的四個位元資料，就剛好能符合協定的要求，能在時 點t7b連續地輸出位址AR(X)對應資料的次四個位元。 1321750 換句話說，本發明是將一位址對應之位元組資料的八 * 個位元一次就全部讀取出來，再藉由各個輸出缓衝模組72 的運作，將八個位元的資料分別於兩個週期τ中逐次輸 出，以符合多位元組連續資料讀取之協定，能夠連續、不 中斷地於兩個週期τ中將一位元組的八位元資料輸出給主 端。相較之下，像在先前討論過的習知儲存裝置30，由於 _ 其一次僅能讀出四個位元的貧料’故在將一位元組之資料 分成四位元、四位元資料傳輸時，中間勢必要再耗費一段 延遲時間來重新進行感測，也因此不能符合多位元組資料 連續讀取之協定。 另一方面’根據第3圖中多位元組資料連續讀取之協 定’在時點t7、t8連續的兩個週期T中傳輸完位址AR(X) 之一位元組資料之後，又要不中斷地從時點t8繼續開始傳 • 輸次一位址AR(X+1)所對應的一位元組資料。如第8圖所 示’在位址計异模組60A將位址AR(X)傳輸至位址緩衝模 組60B之後’位址觸發模组58A就會在時點t6將訊號 CK_ADS由低位準升南至尚位準，觸發位址計算模組a 開始計算次一位址AR(X)。在此同時，控制位址緩衝模組 60B的訊號ADSLAT仍維持於低位準，以鎖定其内儲存之 位址AR(X)’使其不隨訊號ADS改變而改變（位址緩衝模 組60B可用一資料鎖定器來實現）。因此，當解碼電路在時 22 丄以1750 , 點t5m開始依據位址緩衝模組60B於訊號ADDR提供的位 址AR(X)來解碼出位址AR(X)對應的八個記憶單元時，其 過程也都一直不會受到訊號ADS之影響。請注意，當位址 計算模組60A從時點t6開始計算次一位址AR(X+1)時，對 應於位址AR(X)的八個位元資料也才感測/讀取完畢，甚至 還沒開始傳輸回主端。 g 到了時點t7，位址計算模組60A已經有一週期T的時 間來完成位址AR(X+1)之計算，此時位址觸發模組58A就 會將訊说ADSLAT轉變為1¾位準，觸發位址缓衝模組60B 接收位址計算模組60A計算出來的位址AR(X+1)。同時， 在時點t7，解碼模組62也就能開始解碼出位址AR(X+1) 對應的八個記憶單元，並使這些記憶單元將其儲存的資料 傳輸至各輸出缓衝模組72，由輸出緩衝模組72中的各感 測放大器開始偵測位址AR(X+1)對應之一位元組資料。到 鲁 了時點t7b，各感測放大器已經能穩定地輸出位址AR(X+1) 對應資料的各個位元資料，即為訊號SAOUT1、SAOUT2 中所示的資料Axl、Bxl。由於訊號SASEL在時點t7b、t7m 之間還是低位準，保持傳輸閘76A、76B的關閉狀態，使 得各輸出緩衝模組72還能繼續由鎖定電路84輸出位址 AR(X)的後四個位元。到了時點t7m，訊號SASEL才會再 度升高至高位準，開始將位址AR(X+1)的各個位元資料由 感測放大器傳輸至鎖定電路76A、76B。接下來，從時點t8 23 開始’ siL说OBLAT又轉蠻為古 复為同位準，使四個輸出缓衝模組 72此接著由鎖定電路 A中輸出位址AR(X+1)資料的前四 出緩衝組72所輪出的一位元資料A# 位月"付合f立凡組資料連續讀取之協定，在時點t8結束 位址AR(X)資料之輸出後 丄， 偬緊接著輪出位址AR(X+1)之資 科。 、Ax, Bx). The four output buffer modules 72 are collectively connected to each of the sense amplifiers to read out (four) eight bits: a byte data corresponding to the address ar(x). At the point t6m, the output trigger module 58B starts to raise the signal SASEL from the low level to the pure level, so that the originally closed non-conducting transmission 20 1321750 gates 76A, 76B are all turned on, sensing the sense amplifiers 74A, 74B The data is stored (locked) to the lock circuits 82A, 82B, respectively. According to the agreement of continuous reading of multi-bit data, at time t7, the storage circuit 5 should output the first four bits of the address AR(X) corresponding to the material. Therefore, at time t7, the output trigger module 58B of the present invention will raise the level of the signal 〇BLAT to 'turn on the original non-conducting transmission gate 78, and store the data stored in the locking circuit 82A (that is, the data). Αχ) transmitted to the lockout circuit 84, • and transmitted out via the output stage. The four output buffer circuits of the four output buffer circuits start to output at the time point t7, respectively, and the first four bits of the data corresponding to the address AR(X) can be transmitted to the master. The connection signal OBLAT turns on the conduction control of the transmission gate 78 between the time points t7 and t7a. The output triggering module 58B will raise the signal HNBSEL to the high level 'on transmission gate 8' between the time points t7a and t7b, and will be stored in the locking circuit 82B. The data in the data (that is, the data Bx) is transmitted to the lock circuit 82. The data stored in the lock circuit 82A has been previously stored in the lock circuit 84 (because the signal 〇BLAT is turned on) between the time points t7a and t7b. Therefore, the data in the lock circuit 82A can be transferred to the lock circuit 82A. When the time t7b' signal OBSLAT reaches the high level again, the transmission gate 78 is turned on, so that the data Bx in the lock circuit 82B can be transmitted to the lock circuit 84 and output. The four bit data outputted by the four wheel-out buffer modules 72 at the time point t7b can just meet the requirements of the agreement, and the next four bits of the data corresponding to the address AR(X) can be continuously output at the time point t7b. 1321750 In other words, the present invention reads all the eight* bits of the bit corresponding to the address of the address, and then operates the output buffer module 72 by eight bits. The data is successively outputted in two periods τ to conform to the multi-byte continuous data reading protocol, and the octet data of one tuple can be output to the primary end continuously and without interruption in two periods τ . In contrast, as in the conventional storage device 30 discussed earlier, the data of one tuple is divided into four bits and four bits because of the fact that only four bits of the poor material can be read at a time. When the data is transmitted, the intermediate potential needs to spend a delay time to re-sensing, and therefore cannot meet the agreement of continuous reading of multi-byte data. On the other hand, 'the agreement for continuous reading of multi-byte data according to Fig. 3' after transmitting one bit of the address AR(X) in two consecutive periods T of time t7, t8, The transmission of the one-bit data corresponding to the address AR(X+1) is continued from the time point t8 without interruption. As shown in Fig. 8, after the address counting module 60A transmits the address AR(X) to the address buffer module 60B, the address triggering module 58A raises the signal CK_ADS from the low level at time t6. The south is still in position, and the trigger address calculation module a starts to calculate the secondary address AR(X). At the same time, the signal ADSLAT of the control address buffer module 60B is still maintained at a low level to lock the address AR(X)' stored therein so as not to change with the change of the signal ADS (the address buffer module 60B is available). A data locker to achieve). Therefore, when the decoding circuit decodes the eight memory cells corresponding to the address AR(X) according to the address AR(X) provided by the address buffer ADDR by the address buffer module 60B at 1750 and t5m, The process has also been unaffected by the signal ADS. Please note that when the address calculation module 60A calculates the secondary address AR(X+1) from the time point t6, the eight bit data corresponding to the address AR(X) is also sensed/read. It has not even started transmitting back to the main end. g When the time point t7 is reached, the address calculation module 60A has a period of time T to complete the calculation of the address AR(X+1). At this time, the address triggering module 58A converts the voice ADSLAT to a level of 13⁄4. The trigger address buffer module 60B receives the address AR(X+1) calculated by the address calculation module 60A. At the same time, at time t7, the decoding module 62 can also start decoding the eight memory cells corresponding to the address AR (X+1), and cause the memory cells to transfer the stored data to the output buffer modules 72. A bit matrix corresponding to the address AR(X+1) is detected by each sense amplifier in the output buffer module 72. When the time point t7b is reached, each sense amplifier can stably output the bit data of the address AR(X+1) corresponding data, that is, the data Axl, Bxl shown in the signals SAOUT1, SAOUT2. Since the signal SASEL is still at a low level between the time points t7b and t7m, the off state of the transfer gates 76A, 76B is maintained, so that each output buffer module 72 can continue to output the last four bits of the address AR(X) by the lock circuit 84. yuan. At the time t7m, the signal SASEL will rise again to the high level and begin to transfer the individual bit data of the address AR(X+1) from the sense amplifier to the lockout circuits 76A, 76B. Next, starting from the time point t8 23, 'SiL says that the OBLAT turns to the same level as the ancient complex, so that the four output buffer modules 72 are then outputted by the lock circuit A before the address AR(X+1) data. The one-bit data of the four-out buffer group 72 is rounded out. The agreement for continuous reading of the data of the group is completed. After the output of the address AR(X) is finished at time t8, Take the position of the AR (X+1). ,
由以上敘述可知，太恭么 本發明係以位址缓衝模組60B來鎖 疋儲存解碼模組60B解石民夕你μ 鮮馬之位址，讓位址計算模組60Α能 直接開始计异次一位址，使得, t π 便仔解碼感測、位址計算的過程 能同時進行。就如第8圄张+ ^ + 、 乐圖所不’當輪出缓衝模組之各個感 測放大在時點t5m、tft 5Κ η ju* t6至t7之間還在處理位址AR(X)之It can be seen from the above description that the present invention uses the address buffer module 60B to lock the address of the storage decoding module 60B, and the address calculation module 60 can directly start the calculation of the difference. The address is such that the process of t π decoding and sensing and address calculation can be performed simultaneously. Just as the 8th sheet + ^ + , the music map does not 'when the wheeled buffer module's respective sense amplification at the time point t5m, tft 5 Κ η ju* t6 to t7 is still processing the address AR (X) It
資料讀取時，位址計算模組6〇A已經在時點t6開始計算次 -位址AR(X+1)，並能在時點t7提供算好的位址 AR(X+1)。緊接著’解碼模組62、各感測放大器就能在時 點t7、t7b至t8之間開始依據位址AR(X+1)處理對應的資 料感測。同時，在時點t7b，位址計算模組6〇A又能開始 s十算次一位址AR(X+2)。每當解碼模組62、各感測放大器 處理完前一位址的資料感測/讀取後，位址計算模組6〇A也 剛好完成次一位址的計算，讓解碼模組62、各感測放大器 緊接著又能繼續處理對次一位址的資料感測，讓不同位址 之資料感測能連續不中斷地進行，如第8圖中於訊號 SAOim、SA0UT2所示的情形。相較之下，第4圖、第5 24 1321750 圖中的習知儲存裝置在處理不同位址資料之感測時’就會 因位址計算而發生中斷、延遲。利用位址計算模組6〇a、 位址缓衝模組60B之間的協調運作，再加上本發明於各輪 出缓衝模組72中同時讀取兩位元再先後輸出的設計，就能 使本發明儲存裝置50能完全實現多位元組資料連續讀取 之功能，符合低配線數/低腳位數匯流排上資料交換之協 定。 依據相同的道理’當各輸出緩衝模組72中的感測放大 器於時點t8b至t9之間完成位址AR(x+2)資料之感測/讀取 後(也就是訊號SAOUT1、SAOUT2中的一位元資料Ax2、 Bx2) ’位址計算模組60A也已經計算出位址AR(X+3)。從 時點t8b開始，輸出緩衝模組72就可依據訊號SASE]L、 OBLAT、HNBSEL依序於時點t8m至t9、t9至t9a以及t9a 至t9b之間的高位準，使一位元資料Αχ2能經由鎖定電路 82Α、84而輸出，而另—位元之資料Βχ2則經由鎖定電路 82Β、82Α及84而於次一週期τ中輸出。從時點t9開始至 t9b、tlO的期間，位址緩衝模組6〇b、各感測放大器又開 始處理位址AR(X+3)之資料感測/讀取，此時各輸出緩衝模 組72中的各個鎖定電路才正在處理前一位址AR(x+2)之資 料的輸出；而位址計算模組6〇A則已經在時點ti〇計算出 次一位址AR(X+4)。就因為本發明中各相關模組緊密銜接 的工作時序，讓本發明得以符合多位元組資料連續讀取之 25 1321750 協定，增進低配線數/低腳位數匯流排上資料交換的效率。 相較於習知技術’本發明是在各個輸出緩衝模組中將 一位址的所有8個位元的資料一次就全部讀出，再按照多 位元組資料連續讀取協定之規範，將此八個位元以前四 個、後四個位元之順序逐一輪出，使得同一位元組之前四 個、後四個位元能不中斷地連續輸出。另外，本發明亦利 用位址緩衝模組、位址計算模組之設置，來使資料感測、 位址計算的運作能同時進行，使得不同位址之各筆資料能 連續不中斷地被感測、璜出。結合上述兩種機制，本發明 儲存電路就能達成多位元組資料連續讀取之功能，將不同 位址之各個位元組之資料連續輸出，增進匯流排上資料交 換之效能，進而提升電腦系統的整體功能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾’冑應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為一典型電腦系統之功能方塊是意圖。 第2圖為第i圖中晶片組與儲存裝置以喊排連接之示意圖。 第3圖為第2圖中晶片組與儲存裝置進行多位元組資料連 ★續讀取時資料交換協定之時序示意圖。 第4圖為—習知儲存裝置功能方塊的示意圖。 26 1321750 第5圖為第4圖中儲存裝置進行資料讀取時之時序示意圖。 第6圖為本發a月儲存|置—實_之魏方塊示意圖。 第7圖為第6圖中輸出緩衝模組之電路示意圖。 第8圖為f 6 _巾儲存裝置運作時各相⑽號波形時序之 示意圖。When the data is read, the address calculation module 6A has started to calculate the secondary address AR(X+1) at time t6, and can provide the calculated address AR(X+1) at time t7. Immediately after the decoding module 62 and the sense amplifiers, the corresponding data sensing according to the address AR(X+1) processing can be started between the times t7 and t7b to t8. At the same time, at time t7b, the address calculation module 6A can start the s ten-bit address AR(X+2). Whenever the decoding module 62 and each sense amplifier process the data sensing/reading of the previous address, the address calculation module 6A also just completes the calculation of the second address, and the decoding module 62, Each sense amplifier can then continue to process the data sensing of the next address, so that the data sensing of different addresses can be performed continuously without interruption, as shown in Figure 8 in the signals SAOim, SA0UT2. In contrast, the conventional storage device of Figures 4 and 5 24 1321750 will be interrupted and delayed due to address calculation when processing the sensing of different address data. The coordinated operation between the address calculation module 6A and the address buffer module 60B, together with the design of the present invention for simultaneously reading two bits and outputting them in each of the wheel buffer modules 72, The storage device 50 of the present invention can fully realize the function of continuously reading multi-byte data, and conforms to the agreement of data exchange on the low wiring number/low pin number bus. According to the same principle, when the sense amplifiers in the output buffer modules 72 complete the sensing/reading of the address AR(x+2) data between the time points t8b and t9 (that is, in the signals SAOUT1, SAOUT2) The one-bit data Ax2, Bx2) 'address calculation module 60A has also calculated the address AR (X+3). From time t8b, the output buffer module 72 can make the bit data Αχ2 pass through the high level between the time points t8m to t9, t9 to t9a and t9a to t9b according to the signals SASE]L, OBLAT, HNBSEL. The lock circuits 82A, 84 are output, and the other bit data Βχ2 is outputted in the next cycle τ via the lock circuits 82A, 82B and 84. During the period from time t9 to t9b and tlO, the address buffer module 6〇b and each sense amplifier start processing data sensing/reading of the address AR(X+3). At this time, each output buffer module Each of the locking circuits in 72 is processing the output of the data of the previous address AR (x+2); and the address calculation module 6A has calculated the secondary address AR (X+4) at the time point ti〇. ). Because of the working sequence of the closely related modules in the present invention, the invention can conform to the 25 1321750 agreement for continuous reading of multi-byte data, and improve the efficiency of data exchange on the low wiring number/low pin number bus. Compared with the prior art, the present invention reads all the data of all 8 bits of an address at a time in each output buffer module, and then continuously reads the specification of the agreement according to the multi-byte data. The order of the first four bits and the last four bits of the eight bits is rotated one by one, so that the first four and the last four bits of the same byte can be continuously output without interruption. In addition, the present invention also utilizes the address buffer module and the address calculation module to enable the data sensing and address calculation operations to be performed simultaneously, so that the data of different addresses can be continuously and uninterrupted. Test, pull out. Combining the above two mechanisms, the storage circuit of the invention can achieve the function of continuously reading multi-byte data, continuously outputting data of each byte of different addresses, improving the performance of data exchange on the bus, and thereby improving the computer. The overall function of the system. The above are only the preferred embodiments of the present invention, and the equivalent variations and modifications made by the scope of the present invention should be within the scope of the present invention. [Simple description of the diagram] Figure 1 is a functional block of a typical computer system is intended. Fig. 2 is a schematic view showing the connection between the chip set and the storage device in the i-th figure. Figure 3 is a timing diagram of the data exchange protocol for the multi-byte data connection between the chipset and the storage device in Figure 2. Figure 4 is a schematic diagram of a functional block of a conventional storage device. 26 1321750 Figure 5 is a timing diagram of the data reading in the storage device in Figure 4. Figure 6 is a schematic diagram of the Wei block of the storage and setting of the a month. Figure 7 is a circuit diagram of the output buffer module in Figure 6. Figure 8 is a schematic diagram of the waveform timing of each phase (10) when the f 6 _ towel storage device is in operation.
【主要元件符號說明】 10電腦系統 14晶片組 18記憶體 22A週邊控制器 24、54介面電路 28、60A位址計算模組 34A、64A列解碼器 36、66記憶陣列 40感測電路 58A位址觸發模組 60B位址緩衝模組 72輸出緩衝模組 82A-82B、84 T週期 AR(X)-AR(X+3)位址 Px-Pxl ' Qx-Qxl > Ax-7 12中央處理器 16、100 匯流排 20、30、50儲存裝置 22B週邊裝置 26、56控制電路 32、62解碼模組 34B、64B行解碼器 38、68記憶單元 42、74A-74B感測放大器 5 8B輸出觸發模組 70感測模組 76A-76B、78、80 傳輸閘 鎖定電路 Tp卜Tp2時段 I反相器 、Bx-Bx3 資料 27 1321750[Main component symbol description] 10 computer system 14 chipset 18 memory 22A peripheral controller 24, 54 interface circuit 28, 60A address calculation module 34A, 64A column decoder 36, 66 memory array 40 sensing circuit 58A address Trigger module 60B address buffer module 72 output buffer module 82A-82B, 84 T period AR (X)-AR (X + 3) address Px-Pxl 'Qx-Qxl > Ax-7 12 central processor 16, 100 bus 20, 30, 50 storage device 22B peripheral device 26, 56 control circuit 32, 62 decoding module 34B, 64B row decoder 38, 68 memory unit 42, 74A-74B sense amplifier 5 8B output trigger mode Group 70 sensing module 76A-76B, 78, 80 transmission gate locking circuit Tp Tp2 period I inverter, Bx-Bx3 data 27 1321750
Vd、G電壓Vd, G voltage
Vr參考電壓 CLK、FWH0-FWH4 配線 tO-tll、t3b、t5p、t7p-t9p、t7a-tl0a、t5m-tl0m、t7b-tl0b 時點 START、IDSEL、MADDR、MSIZE、TAR、SYNC、DATA 1-DATA4、 SAOUTp、ADDRp、ADS、ADDR、CK_ADS、ADSLAT、SASEL、 HNBSEL、OBLAT、SAOUT1-3 訊號Vr reference voltage CLK, FWH0-FWH4 wiring tO-tll, t3b, t5p, t7p-t9p, t7a-tl0a, t5m-tl0m, t7b-tl0b point START, IDSEL, MADDR, MSIZE, TAR, SYNC, DATA 1-DATA4, SAOUTp, ADDRp, ADS, ADDR, CK_ADS, ADSLAT, SASEL, HNBSEL, OBLAT, SAOUT1-3 signals
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