TWI220460B - Connector for testing semiconductor device - Google Patents

Abstract

A connector for testing semiconductor device is disclosed, which mainly comprises a substrate, plural conductive route and plural bonding pads on the substrate, and plural metal bumps on the bonding pad. Plural conductive route are electrically connected to a testing circuit. The testing circuit can apply a testing signal to the semiconductor device. The plural bonding pads are electrically connected to he plural conductive route. The plural metal bumps are designed to form temporary electrical connections with the plural contacts of the semiconductor device.

Description

1220460 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method for interconnecting with semiconductor elements. [Previous Technology] Manufacturing, packaging, and testing of semiconductor integrated circuits. Testing Parametric In these methods, the semiconductor element is type tested. Although the packaging system is a semiconductor manufacturer, the structure of components with suitable properties and functional components is becoming more and more complicated. The wafer type or the low packaging of the wafer type appears to prevent the normal operation of the package structure. Due to the damage of the wafer on the wafer carrier, As a result, the entire package structure has no manufacturing cost. Therefore, in general, chips of integrated circuits are generally referred to as integrated circuits with 50 integrated circuits. Test method for split-crystal semiconductor components, especially related to connectors that form temporary electrical connections. Multiple processes into functional manufacturing require test separability and burn-in (bur η-the device may be a device that is often forced before the device is sealed). Each half of the components that have been advanced is normal or the wafer system is made to 1000. It is divided into circles and divided into wafers. After the wafers are installed relatively, it must be tested by the operator. It is possible. Conductive elements may be manipulated and sized, including design, functional, and in methods. The more expensive steps in this wafer or package construction, but also the warranty semiconductor testing. As semiconductors do this before the packaging process, in addition, as polycrystalline is only set in multiple factors, one of which is detrimental to Amoy, it is even more necessary to test it here.

JT is built on a semiconductor wafer, each of which is independent (street. Then the integrated circuit is separated from the wafer. The indices on the wafer) are separated by an independent integrated circuit of a divided process.

1220460 5. Description of the invention (2) Multiple wafers. Because the individual integrated circuits on the wafer are neatly distributed in an array, the use of wafer-level testing can greatly reduce the time and cost of testing. In the test process, the probe end (pr〇be t ^ p) of the tester (pr〇ber) must be temporarily connected to the contact on the semiconductor device (such as a pad (b〇n (i pad) or bump contact) (Bumped contact)) to form an electrical connection. In order to complete this temporary electrical connection, a variety of connectors have been developed. The connector typically used at wafer level is a test card. card), which generally includes a probe end in the form of a probe needle. A wafer handler aligns the wafer with the test card, and then electrically contacts the probe pin to the wafer. Then test The signal is transmitted to the integrated circuit on the wafer through the probe pin. However, continuous miniaturization poses a challenge to the aforementioned test method. As the density of contacts on semiconductor devices becomes higher and higher, the aforementioned test card must be used It has a smaller probe pin. However, the probe size cannot be reduced indefinitely as the size of a semiconductor element is reduced. Therefore, there is a need for a connector for testing a semiconductor element, which can overcome or at least improve the above. [Summary of the Invention] The object of the present invention is to provide a connector for forming a temporary electrical connection with a semiconductor device, which is manufactured using photo 1 ithographic technology so that it can have a fine pitch (fine pi) tch) and a highly accurate configuration probe (pr〇be tip).

00525.ptd! 22〇46〇 5. Description of the invention (3) A connector according to an embodiment of the present invention mainly includes a substrate, a plurality of conductive lines and a plurality of pads are disposed on the substrate, and a plurality of metal bumps Set on the pad. The substrate is preferably made of a material having a coefficient of thermal expansion similar to that of a semiconductor element, such as a glass wafer or a silicon wafer. The plurality of conductive lines are not electrically connectable to the 'test circuit, and the test circuit can apply a test signal to the semiconductor device. The plurality of pads are electrically connected to the plurality of conductive lines. The plurality of metal bumps are designed to form a temporary electrical connection with a plurality of contacts of the semiconductor element. The plurality of metal bumps may be gold bumps, solder bumps, or stud bumps formed by a conventional wire bonding method. The connector according to another embodiment of the present invention mainly includes a substrate, a plurality of conductive lines and a plurality of first pads are disposed on the substrate, an insulating layer is formed on the substrate and the plurality of conductive lines, and a plurality of first Two pads are disposed on the insulating layer, a plurality of first metal bumps are disposed on the first pad, and a plurality of second metal bumps are disposed on the second pad. The insulation layer has a plurality of vias to expose the plurality of first pads. It should be noted that 'the height of the first metal bump is substantially equal to the thickness of the insulating layer' plus the height of the second metal bump, thereby making the first metal bump and the tip of the second metal bump It is substantially coplanar and can form a temporary electrical connection with a plurality of contacts of the semiconductor element. The first metal bump and the second metal bump are preferably stud bumps formed by a conventional wire bonding method. Ϊ́ ΐ The connector according to another embodiment of the present invention mainly includes a substrate, a plurality of conductive lines are provided on the substrate, and an insulating layer is formed on the substrate and

1220460 5. Description of the invention (4) The plurality of conductive lines. The insulating layer has a plurality of via holes (v i a) to expose a part of the conductive circuit. The plurality of pilot holes are filled with a plurality of pilot hole plugs (v i a p 1 ug). The pilot hole plug is provided with a plurality of first contacts. The insulating layer is provided with a plurality of second pads. The first pad and the plurality of metal bumps on the first pad are not designed to form temporary electrical connections with the plurality of contacts of the semiconductor device. 1 The connector according to the present invention uses the lithography technology, that is, the photodetector is used to manufacture the detection end (ie, the aforementioned metal bump) on the connector and its connection line. 1 The connector made here can have fine pitch and A highly accurate detection terminal can overcome or at least improve the problems of the foregoing prior art. When using a glass wafer as a substrate to manufacture a connector, the positioning and alignment of the basin is right. Furthermore, according to the present invention: when the cylindrical protrusion at the measuring end is damaged, the fertilization can be directly performed (two b drop, '/ re-use the wire bonding technology to form a new cylindrical protrusion ·) in the connector according to the present invention ^ Hunting this on the substrate effectively reduces costs. q Xiu Lei Xian: Bottom: d: t and other items w, features, and advantages can be described in more detail as follows: χ show the preferred embodiment, and with the accompanying drawings, make a detailed [invention description] The: ϋυ illustrates the connector 100 according to an embodiment of the present invention. °, used to establish a temporary electrical connection with a semiconductor element.

Page 8 1220460 V. Description of the invention (5) The connector 100 mainly includes a substrate 11 (), a plurality of conductive lines 12 (), and a plurality of contacts 1 3 0 (see FIG. 4) (located on the substrate) 丨〇, and ff 5 metal bumps 140 are provided on the pad 13. The substrate is preferably made of 70 materials with similar thermal expansion coefficients, such as glass wafer crystal f. The plurality of conductive lines 120 (for the sake of brevity, a portion of the conductive lines 120 in FIG. 1) are formed in a specific pattern. When a glass wafer is used as the substrate 110, it is helpful in the test process. Positioning and alignment. As shown in the figure, the conductive circuit 120 preferably includes a layer of chromium and a gold handle. In addition, the conductive circuit 120 may also be formed of other metals with good conductivity, such as 及 or an alloy thereof. In detail ... First, a layer of chromium and a layer of gold are sputtered onto the substrate 110. Next, a photoresist layer is coated on the chromium / gold and developed using conventional techniques and materials (UeVelQPing). The exposed part of the chrome / gold layer will be engraved to form the conductive i after lmaglng is imaged (see Figure 4). See Figure 4 for specific parts of the plurality of pads i 3 012. The surface may be formed on the conductive line 140. The positions of the plurality of pads 130 are determined by eight or more metal bumps. The positions of the plurality of metal bumps 14 to the desired position of the system / block 140 are determined by the contacts of the conductive elements. According to the eighth of the present invention, half of the solder bumps (solder b_) (such as high-temperature tin i complex bumps :, yes: soldering) 00525.ptd page 9 1220460

5Sn / 95Pb or 3Sn / 97Pb, and low temperature tin-lead balls, such as 63Sn / 37pb) are formed on the pad 130 by electroplating to form a probe tip. Therefore, the connecting member of the present invention can directly use the connection between the detection terminal and the semiconductor element to establish a temporary electrical connection. The metal bump according to the present invention may also be a gold bump plated on the pad 13 to form a detection terminal. The gold bump generally contains at least ninety weight percent gold, and is deposited on the pad 130 by electroplating. In addition, the metal bump according to the present invention may also be a stud bump formed by a wire bonding technique. First, a ball is used to form a ball at the tip of a line (wire), and the ball is joined to the connection 130 using a g-wave or thermocompression technique. Then, the thread was cut directly above the ball to make a columnar bump formed on the pad. The reference image 1 of the reference makeup ′ may include a solder pad 150 placed on the edge of the connector 100 or other positions. The pads 50 are used to connect the conductive circuit 120 to the test circuit by wire bonding, TAB bonding or soldering.

Referring to FIG. 5, which illustrates a connector 200 according to another embodiment of the present invention, the connector 200 mainly includes a substrate 11, a plurality of conductive lines (not shown in the figure), and an insulating layer 2 10 formed on the substrate. A substrate and the plurality of conductive lines. A plurality of pads 3 and 3 are provided on the substrate 11. A plurality of pads 220 are provided on the insulating layer 2 i 〇. A plurality of metal bumps 230 are disposed on the pads 320 and a plurality of metal bumps 2 4 0 are disposed on the pads 2 2 0. The insulating layer 2 1 0 has a plurality of via holes (v i a) 2 1 0 a to expose the plurality of pads 3 0. The metal bumps 230 and 240 are preferably stud bumps formed by a conventional wire bonding method. The metal bumps 230 and 240 are designed to break the wire

1220460 5. Description of the invention (7) Different heights directly above the ball, thereby making the height of the metal bump 230 approximately equal to the thickness of the insulating layer 210 plus the height of the metal bump 240. This will allow the tips of the metal bumps 230, 240 to be substantially coplanar, and to form temporary electrical connections with a plurality of contacts of the semi-conducting element. Referring to FIG. 6, it illustrates a connector 300 ′ according to yet another embodiment of the present invention, which mainly includes a substrate 11, a plurality of conductive lines (not shown in FIG. 5), and an insulating layer 2 10 formed on On the substrate and the plurality of conductive lines. The connector 300 is characterized in that the plurality of guide holes 2 1 0a are filled with a plurality of guide hole plugs (v i a p 1 ug) 3 1 0. The guide hole plug 3 1 0 is provided with a plurality of pads 3 2 0. A plurality of pads 3 3 0 are provided on the insulating layer. The joints 3 2 0 and 3 3 are provided with a plurality of metal bumps 1 4 0 designed to form temporary electrical connections with the plurality of contacts of the semiconductor element. Please refer to FIG. 1 again. In this embodiment, the size and contour of the connector correspond to a conventional semiconductor wafer. However, the connector according to the present invention can be designed to test one wafer or several wafers at a time. Figures 2 and 3 show a wafer uve test system 400 for testing a wafer 510 on a semiconductor wafer 500. The test system 400 includes the connector 100 and a main body 4 10 (see FIG. 3). The main body 41 occluded emperor ’s follower, striker, ΟΛ / ▲ α —η dagger 3 or privately connected to the test circuit 420 (see figure 3 in Mai) for the wafer 50n postal person h round The build-ups contained in υ u test you signal. As shown in FIG. 2, a multilayer tape 43 is used to establish an electrical connection between the connector 100 and the test circuit 420.俜 It is similar to TAB tape, which contains a thin polymer layer 4 on it. This multilayer tape ㈣ can be spliced to a connector = 塾

1220460

150 (see Figure 1) and miscellaneous system 40. There is a force applying mechanism 44〇 = the connection point on the top. The test is referred to as 44 and a force applying element 442. The force element 4 = Γ; Ϊ "450 and a compressible member made of an elastomer material, and the compressible and shrinkable member 460 is in contact with the back of the connector 100. f ^ The compression member 460 can buffer the wafer The force exerted by 500, which allows the current phase ST wafer to be flattened by 50 °. The test system can include ": = (not shown in the figure) to select and move the connected components of the invention as needed. Although the method of cleaning the rough surface of the protruding side can end itself, the length of the connector is detected as a columnar protruding bump due to physical abrasion. However, there are some bumps in the way of grinding. Metal bumps are used as a probe to touch hundreds of points. The shorter you want to polish the device, the shorter. The detection terminal is damaged according to bump) or the detection terminal circuit on the connector according to the present invention is created. Therefore, the detection terminal of the connection is made, so that the question 0 can be answered. In addition, according to this bump), it is cleaned with the test. . At present, this method using a rotating grinding disc enables the detection and cleaning of a post that can be ground into a better end system by using lithography technology (that is, the aforementioned metal device can be finely overcome or at least improve the front connector Probe block contact method, roughly contacting, by cleaning the connection material will also be more and more uniform. Therefore, the block (stud clean and wear 'that is, using the mask to make bumps) and its connection line spacing and highly accurate Describe the contamination on the probe end of the probe in the prior art, and repeatedly use the code and grind it (that is, the connector 2 of the present invention in the aforementioned name, so as to make the connector grow short and uneven)

After that, clean detection is needed_and

00525.ptd Page 12 1220460

Page 1212460 Brief description of the drawings [Illustration] Figure 1: A schematic top view of a connector according to an embodiment of the present invention; Figure 2: A wafer-level test system according to an embodiment of the present invention ( Wafer level test system); Figure 3: Block diagram of wafer level test system shown in Figure 2; Figure 4: Sectional view along line 4-4 of Figure 1; Figure 5: According to the present invention A partial sectional view of a connector according to another embodiment; and FIG. 6 is a partial sectional view of a connector according to still another embodiment of the present invention. [Illustration of drawing number]

100 connector 110 substrate 120 conductive line 130 pad 140 metal bump 150 solder pad 200 connector 210 insulation 210a via hole 220 pad 230 metal bump 240 metal bump 300 connector 310 via plug 320 pad 330 Pad 400 Wafer-level test system 410 Main body 420 Test circuit 430 Multi-layer tape 430a Polymer thin layer 430b Conductive circuit 440 Force mechanism 442 Force element

00525.ptd Page 14 1220460 Brief description of drawings 450 Pressure plate 460 Compressible part 50 0 Semiconductor wafer 510 Wafer

00525.ptd Page 15 III!

Claims (1)

JV / ---------Repair Qi Charger No. 91117839 6. Scope of Patent Application Λ a Amendment 1. A type for testing semiconductor devices, the semiconductor device has a plurality of lnterconnects-a substrate (Substrate); ",, The connector includes: a plurality of conductive lines provided on the substrate ^ counted to be electrically connected to a test circuit" ° plurality of conductive line system components are provided with test signals; The test circuit may provide a plurality of pads of the semiconductor on the substrate, the plurality of conductive lines; and °, the plurality of pads are electrically connected to a plurality of bumps provided on the pads and the semiconductor elements # 二 = Several bumps are designed to be able to form a temporary electrical connection. 2 According to the scope of the patent application, the first day of the circle (si 1 icon waf device, where the substrate is _3 3 to test semiconductor components Connector er Connection of various parts 3. According to the scope of the patent application, the substrate is one, which is used for testing semiconductors, glass wafers. 4. According to the scope of the patent application, where The The connection of electrical circuit people for testing semiconductor components-a layer of chromium and a layer of gold. 5. According to the scope of the patent application, the bump is-the connection I used to test the semiconductor component I is a bump. According to the patent application Fan 00525.ptc for testing the connection of semiconductor components Page 16 1220460 Because the metal bumps are in a group of stud bumps! A. Yu tin bumps and columnar protrusions. Two kinds of connections for testing semiconductor devices. The semiconductor device has a plurality of contacts, and a substrate. Λ, the connector contains ： A plurality of conductive lines are provided on the base so that they can be electrically connected to the -test circuit; == the conductive line is provided with components for applying a test signal; the side measurement and subtraction circuit can connect the plurality of first heat-conducting circuits # _L, Is connected to the plurality of conductive wires two, the plurality of-pads are connected to the electrical edge plate Γ and the plurality of conductive wires, and there are several V-holes (Vla) to expose the plurality of conductive wires. First: a plurality of second pads are disposed on the electrical connection to the plurality of conductive lines; and a brother pad is a plurality of 帛 -bumps I on the second: on the second pad, the first The height of a bump is roughly equal to two: the bump and the second bump system; the degree and the number of the first bumps are temporarily connected electrically. … The multiple contact shapes of the Hai semiconductor components 1220460 amended j number 911178, ¾ (the sixth, the scope of application for patents, according to the application of the Qing dynasty patent Fan Qifan 7 devices, the plate • slope;: === 器 ， where The guide :: Γ contains two of the terms, which are used to test the connection of the semiconductor device. It has three layers of chromium and one layer of gold. 11. According to the seventh item of the scope of patent application, the first bump and the $-convex poem , / = 脰: connection bump of the pieces). Leyi bumps are columnar bumps (stud 1 2 for testing the connection of semiconductor devices). The semiconductor device has a plurality of contacts :::: i: t: nnect) a substrate ^ Connected as a plurality of conductive lines are provided on the substrate, and are counted to be electrically connectable with a test circuit. A plurality of conductive line system components are provided with a test signal; 'the test circuit can be used for the semiconductor An insulating layer is formed on the substrate and the edge layer having a plurality of vias to conduct conductive lines, and the insulation is separated; the circuit is provided with a plurality of vias plugs (via Pl)埴, — ^ a plurality of first pads are provided in the guide hole insert = the 稷 several guide holes; yes, it is sexually connected to the plurality of conductive lines, 线路 a plurality of first pads + a plurality of second pads The pads are provided in the insulated room and are connected to the plurality of conductive lines y2 in a pen-like manner. The plurality of second pads are 00525.ptc page 18 5 & 1220460 case number 91117839 A bump is provided on the first pad and the second pad, The plurality of bumps are designed to form a temporary electrical connection with the plurality of contacts of the semiconductor element. 1 3. The connector for testing a semiconductor element according to item 12 of the scope of patent application, wherein the substrate is It is a silicon wafer (si 1 ic ο nwafer). 1 4. The connector for testing semiconductor components according to item 12 of the patent application scope, wherein the substrate is a glass wafer (g 1 asswafer). 1 5. The connector for testing semiconductor components according to item 12 of the scope of patent application, wherein the conductive circuit includes a layer of chromium and a layer of gold. 16 ', according to item 12 of the scope of patent application for testing semiconductor components A connector, wherein the bump is a metal bump. 1 7. The connector for testing a semiconductor element according to item 16 of the scope of patent application, wherein the metal bump is a gold bump, a solder bump And those selected from the group consisting of stud bumps. 00525.ptc Page 19