1269381 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體平坦化製程方法，特別是， 關於一種利用化學機械研磨進行平坦化製程的方法。 【先别技術】 在半導體元件製程中，常需要對晶圓的表面進行平坦 化處理，以利後續製程步驟的進行。化學機械研^ (chemical mechanical polishing (CMP))為目前常見的平抽 化技術之一。CMP製程的基本作用係從晶圓表面凸出部 分開始，依其高低照順序研磨而除去，以使表面平坦。 然而，由於不同材質的CMP研磨速率並不相同，因 此經過CMP處理後的表面，可能仍存在凹凸起伏的情 況。隨著製程尺寸的縮小，精密度要求越來越高，這些凹 凸起伏的程度已經超過了所能容忍的誤差極限。因此，如 =增加CMP平坦化的程度，成為製程技術發展的重要課 舉例來說 μ馮寻利公告編號313694號揭露一種積 體電路的平坦化方法’用以改善CMP製程的縣度。然 而，右使用該專利所揭露的方法，顺要進行2次的1269381 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor planarization process, and more particularly to a method of planarizing a process using chemical mechanical polishing. [Technology] In the semiconductor device process, it is often necessary to planarize the surface of the wafer to facilitate the subsequent process steps. Chemical mechanical polishing (CMP) is one of the common flat extraction techniques. The basic function of the CMP process begins with the embossed portion of the wafer surface and is removed by grinding in order of high and low order to flatten the surface. However, since the CMP polishing rates of different materials are not the same, there may still be undulations on the surface after CMP treatment. As the size of the process shrinks, the precision requirements become higher and higher, and the extent of these concave bulges has exceeded the tolerance limit that can be tolerated. Therefore, if the degree of CMP flattening is increased, it becomes an important part of the development of process technology. For example, μ Fenglili Bulletin No. 313694 discloses a method for flattening an integrated circuit to improve the county of the CMP process. However, the method disclosed in the patent is used right, and it is performed twice.
CMP ^以及1次的乾钱刻步驟，而這將增加不少製程上的成 本〇 4NTC/05004TW ； 93046 1269381 因此，有必要提供一種可增加CMP製程之平坦度， 而又可最簡化製程所需步驟的方法。 【發明内容】 鑑於先如技術所存在的問題，本發明提供了 ^_種半導 體製程技術，用以平坦化晶圓表面。CMP ^ and 1 dry money engraving step, which will increase the cost of many processes 〇 4NTC/05004TW; 93046 1269381 Therefore, it is necessary to provide a flatness that can increase the CMP process while simplifying the process The method of the step. SUMMARY OF THE INVENTION In view of the problems inherent in the prior art, the present invention provides a semi-conductive process technique for planarizing wafer surfaces.
根據本發明之一方面，半導體平坦化製程方法包含以 下步驟.在一基板上形成複數個元件，各元件間形成複數 個間隔；形成一回填層’以覆蓋基板、複數個元件及複數 個間隔；形成具有-就厚度之—犧牲層，以覆蓋回填 層；以及執行-化學機械研磨，除去犧牲層及部分回填 層，以形成一平坦化表面；其中，化學機械研磨對回填層 的研磨速率大於對犧牲層的研磨速率。 、According to an aspect of the invention, a semiconductor planarization process includes the steps of: forming a plurality of components on a substrate, forming a plurality of spaces between the components; forming a backfill layer to cover the substrate, the plurality of components, and the plurality of intervals; Forming a sacrificial layer having a thickness of - to cover the backfill layer; and performing - chemical mechanical polishing to remove the sacrificial layer and a portion of the backfill layer to form a planarized surface; wherein the chemical mechanical polishing has a polishing rate greater than that of the backfill layer The polishing rate of the sacrificial layer. ,
=據本_以—方面，轉體相 基板上形成複數個元件，技件間形= Π成H案化多祕層，填充部分之複數個間 隔，形成一回填層，以覆蓋基板、複數 〃 間隔及圖案化多晶石夕層；在回填層之 複數個 定厚度之一犧牲声·以及勃—一 & ，形成具有一預 案化多晶料，磨絲露出圖 磨對回埴層的二+千坦化表面;其中，化學機械研 、_研磨逮率大於對犧牲層的研磨速率 4NTC/05004TW ; 93046 -6 - 1269381 【實施方式】 本發明揭露一種半導體製程方法，用以平坦化晶圓表 面。本發明係以記憶製程為實施例做說明，然本發明但並 不限於此，本發明所提供的平坦化方法可應用在其他需要 消除高低差的各種積體電路製程步驟中。為了使本發明之 敘述更加詳盡與完備，可參照下列描述並配合圖丨至圖 12之圖式。 圖M2繪示本發明應用在動態隨機存取記憶體之一 實把例的製程流程。在此實施例中，本發明係用以改善位 元線接觸孔形成過程中，所造成動態隨機存取記^體 (DRAM)之陣列區域電路與週邊區域電路的高低差。需注 意的是，本發明所舉實施例只是用以說明，並非用以限制 本發明。糊來說’―般邏輯雜電路誠溝槽隔離 (^hallow trench isolation)或是絕緣層上矽(s〇I)元件的製程 等皆可利用本發明來增&CMp製程的平坦度。 '"王 20、^考^ 1 ’4·百先在基板1〇上形成例如複數個電晶體 、而除電晶體外，元件20、22、24亦可a 電容器或其他電財見元件。在此實_巾，電晶體 及22代表DRAM的陣列區 =声 ，的週邊區域電路。接著在基板i。上：體= i 30’以覆盖電晶體2()、22、24及基板⑺，如圖2所示。 4NTC/05004TW ; 93046 1269381 多晶石夕層3G的雜方法可则習知製程技術，如化學氣 相沉積所形成。由於基板ίο與電晶體20、22、24之間的 高低差，多祕層3G的表面也呈現出相對應的高低^。 接著，參考圖3 ’為利於後續的製程，對多晶石夕層3〇 的表面施財坦化雜’其平坦化的方材_化學機械 研磨(chemical mechanical p〇lishing)。得到多晶石夕層 3〇 的 平坦化表面後’以習知的曝光顯影技術定義出所需曰區域， 並以習知的钮刻技術將多晶石夕層3〇侧出所需圖案，如 圖4所示。 接著，在基板10上共形地形成一氮化層4〇，例如氮 化石夕，而形成圖5所示的結構。接著，在氮化層4〇上形 成回填層50。此回填層5〇可為一删磷矽玻璃(BpSG)， ^形成方法可為習知的沉積方法。由於底下結構的高低 差，回填層50的表面也會有高低起伏，如圖6所示。 同樣地，為了繼續後續的製程步驟，必須對回填層 =的表面進行平坦化處理。然而，當直接對圖6結構進 了化學機械研磨處理時，若要達成理想的平坦化程度，則 :=層5〇的材料必須有相當的厚度才能制理想的平坦 私度。如此不但造成材料浪費，亦影響生產效率。 因此，如圖7所示，在進行化學機械研磨前，先沉積 4NTC/05004TW ； 93046 1269381 -層犧牲層6G，此難層6G的研紐率低於贿石夕玻璃 (回填層50)_速率。犧牲層6〇的材料可例如為氮化 石夕⑼心氮化硼购或塗佈玻璃獅㈣㈣⑽)）。 形成犧牲層6G後’開始進行化學機械研磨步驟。首先， 犧牲層60位置較向的部分會先被研磨t而移除，亦即電晶 體2〇與22上方的犧牲層會先被移除而暴露出部分的回填 層50。由於犧牲層60的研磨速率低於回填層5〇，造成回 填層50所絲的部份產生凹_現象，师細8所示 的結構。研磨繼續進行，使得圖8所示回填層5〇的凹陷 部份由於接觸到氮化層40 *使研磨速率變慢，而圖8所 示的犧牲層6〇則由於接觸到回填層5〇而使研磨速率變 快。因此，▲藉由在同-研磨步獅過程巾所產生的研磨速 度之相反’I：彳b ’便可在化學機械研磨步驟結束後，得到 有平坦表面的結構，如圖9所示。 ^ 犧牲層60的厚度係根據各層間研磨速率的差異及各 層厚，的差異而決定，並可藉由實驗喊出最佳化值。透 過計算及/或實驗找出犧牲層6〇的理想厚度後，只需進Γ 一次化學麵研齡獅可制平坦化的目的。因此，^ 發明可最小化所需的製程步驟來職具有良好平坦度 表面。 』 在得到平坦的晶圓表面後，即可繼續進行後續 步驟。在此實施例中係針對多晶销3G進行綱，^得 4NTC/05004TW ； 93046 1269381 到圖ίο所示的開孔結構。接著，形成—導電層兀於回填 層刈之上，並填充電晶體20及22之間的開孔，如圖^ 所不’其中導電層70的材料可例如為鶴。接著，參考圖 12，以例如化學機械研磨(CMp)之方法，平坦化導電層7〇 至露出_層50表面’而形成具有良好平坦度的動態隨 機存取記舰之位元線接觸。接著，可_進行其他各種 後續的製程步驟，在此不再贅述。 本發明所提供方法可消除例如DRAM製造過程中所 產生之删傘夕玻璃層(BPSG)的高低差異。然而，其他需 要進行平坦化處理的各種半導體製程，亦可運用本發明之 方法。 以上所述僅為本發明之較佳實施例而已，並非用以限 疋本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 【圖式簡單說明】 圖M2為本發明之一實施例的製程剖面流程圖。 【主要元件符號說明】 10、基板 20、22、24電晶體 30、多晶矽層 40、氮化層 4NTC/05004TW ； 93046 -10- 1269381 50、回填層 60、犧牲層 70、導電層According to the present invention, a plurality of components are formed on the substrate of the rotating body, and the shape of the technical component is 多成H. The multiple layers of the filling portion are filled to form a backfill layer to cover the substrate and the plurality of layers. Interstitial and patterned polycrystalline lithosphere; one of a plurality of predetermined thicknesses of the backfill layer, sacrificial sound, and Bo-I&, formed with a pre-formed polycrystalline material, and the polished wire reveals a pattern of the rubbing layer + thousand-stained surface; wherein, the chemical mechanical research, the grinding rate is greater than the polishing rate of the sacrificial layer 4NTC/05004TW; 93046 -6 - 1269381 [Embodiment] The present invention discloses a semiconductor manufacturing method for planarizing a wafer surface. The present invention is described by taking an memory process as an embodiment. However, the present invention is not limited thereto, and the planarization method provided by the present invention can be applied to other integrated circuit process steps that need to eliminate high and low differences. In order to make the description of the present invention more detailed and complete, reference is made to the following description and the drawings to the drawings. Figure M2 illustrates a process flow of an embodiment of the present invention applied to a dynamic random access memory. In this embodiment, the present invention is for improving the height difference between the array area circuit of the dynamic random access memory (DRAM) and the peripheral area circuit during the formation of the bit line contact hole. It is to be noted that the embodiments of the present invention are intended to be illustrative only and not to limit the invention. The paste can be used to increase the flatness of the CMp process by using the method of "Hallow Space Isolation" or "Insulator Layer" (S?I). '" Wang 20, ^ test ^ 1 '4 · Bai first on the substrate 1 形成 formed a plurality of transistors, and in addition to the transistor, the elements 20, 22, 24 can also be a capacitor or other electricity see components. Here, the actual area, the transistor and the 22 represent the array area of the DRAM = acoustic, peripheral area circuit. Next on the substrate i. Upper: body = i 30' to cover the transistors 2 (), 22, 24 and the substrate (7) as shown in FIG. 4NTC/05004TW; 93046 1269381 The polycrystalline method of 3G can be formed by conventional process techniques such as chemical vapor deposition. Due to the difference in height between the substrate ίο and the transistors 20, 22, 24, the surface of the multi-layer 3G also exhibits a corresponding height. Next, referring to Fig. 3', in order to facilitate the subsequent process, the surface of the polycrystalline layer 3〇 is subjected to a flattened square material_chemical mechanical p〇lishing. After obtaining the flattened surface of the polycrystalline layer 3 ', the desired 曰 region is defined by a conventional exposure development technique, and the desired pattern is formed by the polysilicon layer 3 〇 by a conventional button technique. As shown in Figure 4. Next, a nitride layer 4, such as nitrogen nitride, is conformally formed on the substrate 10 to form the structure shown in Fig. 5. Next, a backfill layer 50 is formed on the nitride layer 4A. The backfill layer 5 can be a PpSG, and the formation method can be a conventional deposition method. Due to the height difference of the underlying structure, the surface of the backfill layer 50 also has high and low undulations, as shown in FIG. Similarly, in order to continue the subsequent process steps, the surface of the backfill layer must be planarized. However, when the chemical mechanical polishing treatment is directly applied to the structure of Fig. 6, in order to achieve a desired degree of planarization, the material of the layer = 5 must have a considerable thickness to achieve an ideal flatness. This not only causes material waste, but also affects production efficiency. Therefore, as shown in Fig. 7, before performing chemical mechanical polishing, 4NTC/05004TW; 93046 1269381 - sacrificial layer 6G is deposited, and the rate of the 6G of the hard layer is lower than that of the brittle glass (backfill 50). . The material of the sacrificial layer 6〇 can be, for example, nitrided (9) core boron nitride or coated glass lion (four) (four) (10))). After the sacrificial layer 6G is formed, the chemical mechanical polishing step is started. First, the portion of the sacrificial layer 60 that is oriented is first removed by grinding t, that is, the sacrificial layer above the transistors 2 and 22 is removed first to expose a portion of the backfill 50. Since the polishing rate of the sacrificial layer 60 is lower than that of the backfill layer 5, the portion of the silk layer of the backfill layer 50 is concave, which is the structure shown in detail 8. The polishing is continued, so that the depressed portion of the backfill layer 5 of FIG. 8 is slowed by the contact with the nitride layer 40*, and the sacrificial layer 6 shown in FIG. 8 is contacted by the backfill layer 5〇. Make the grinding rate faster. Therefore, the structure having a flat surface can be obtained after the chemical mechanical polishing step by the opposite 'I: 彳b ' produced by the same-grinding rifle process towel, as shown in Fig. 9. ^ The thickness of the sacrificial layer 60 is determined by the difference in the polishing rate between the layers and the thickness of each layer, and the optimum value can be called by experiments. After calculating and/or experimenting to find the ideal thickness of the sacrificial layer 6〇, it is only necessary to enter the chemical surface of the lion to make the flattening. Therefore, the invention can minimize the required process steps for a good flatness surface. After obtaining a flat wafer surface, you can proceed to the next step. In this embodiment, the polycrystalline pin 3G is used for the opening structure of 4NTC/05004TW; 93046 1269381 to FIG. Next, a conductive layer is formed over the backfill layer and filled with openings between the transistors 20 and 22, such as the material of the conductive layer 70 being, for example, a crane. Next, referring to Fig. 12, the conductive layer 7 is planarized to expose the surface of the layer 50 by, for example, chemical mechanical polishing (CMp) to form a bit line contact of a dynamic random access ship with good flatness. Then, various other subsequent process steps can be performed, and will not be described herein. The method provided by the present invention can eliminate, for example, the difference in height of the shed glass layer (BPSG) produced in the DRAM manufacturing process. However, other semiconductor processes that require planarization may also employ the method of the present invention. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included. Within the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure M2 is a flow chart of a process profile according to an embodiment of the present invention. [Main component symbol description] 10. Substrate 20, 22, 24 transistor 30, polysilicon layer 40, nitride layer 4NTC/05004TW; 93046 -10- 1269381 50, backfill layer 60, sacrificial layer 70, conductive layer
4NTC/05004TW ； 93046 -11 -4NTC/05004TW ; 93046 -11 -