8twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是有關於一 種動態隨機存取記憶胞（Dynamic Random Access Memory cell，DRAM cell)及其製造方法。 【先前技術】 在半導體產業中，動態隨機存取記憶體是一種不斷地 在研究與發展的重要積體電路。而目前在提高動態隨機存 取記憶胞的儲存電容、改善動態隨機存取記憶胞的讀取與 寫入速度以及縮小動態隨機存取記憶胞的元件尺寸等方面 的研究，持續獲得不少成果。動態隨機存取記憶胞中通常 包括有一個電晶體以及一個由電晶體所操控之電容器。一 般來說，動態隨機存取記憶胞的設計係可分為三種型式， 分別稱為平面式、電容堆疊式以及溝渠式。在平面 胞的設計中，電晶體與電容器皆為平面式之元件，而在電 容堆疊式DRAM胞的設計巾，f容㈣係配置在電晶體之 上。在溝渠式DRAM胞的設計中，f晶體係配置在基底的 表面上，而電容關係配置於形成在此表面 由 而在形成溝渠的製程中，光罩必須確實對位準且 „米的半導體元件中，深溝渠之長度與直徑的比例 可能是4G.卜而在深且㈣溝渠中形成電容器的血 法係先將介電層沈積在絲壁上，再將具有 ^ 層填入溝渠中。然而，當溝渠之長度與直徑的比例例: 大於20 : 1時，可能會難以將構成電容器所需之材質填入 12513¾ 38twf.doc/006 溝渠内。 【發明内容】 胞二電ίϊ:的目的就是提供-種動態隨機存取記憶 知之意H成於半導體柱體的側壁上，以解決習 1 = _存取記憶體難以將電容器填入的問 通，並可曰加電容器的表面面積。 料目的是提供—種以本發明之動態隨機存 取⑽^構為基礎的動紐機存取記憶體_，由於垂 直式電晶體係形成在記憶胞巾，@此動態隨機存取記情體 陣列可具有較高之積集度。 〜 本發明的又一目的是提供一種動態隨機存取記憶體陣 列的製造方法，以便解決習知之溝渠式動態隨機存取記憶 體難以將電容H填人的問題，並增加動紐機存取記憶體 元件的積集度。 〜 本發明提出一種動態隨機存取記憶胞（Dynamic8twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a dynamic random access memory cell (DRAM cell) and Production method. [Prior Art] In the semiconductor industry, dynamic random access memory is an important integrated circuit that is constantly researching and developing. At present, research on improving the storage capacitance of dynamic random access memory cells, improving the read and write speed of dynamic random access memory cells, and reducing the size of components of dynamic random access memory cells have continued to yield a lot of results. Dynamic random access memory cells typically include a transistor and a capacitor controlled by the transistor. In general, the design of dynamic random access memory cells can be divided into three types, which are called planar, capacitive stacked, and trenched. In the design of the planar cell, both the transistor and the capacitor are planar components, and in the design of the capacitor-stacked DRAM cell, the f-capacitor (four) is disposed on the transistor. In the design of the trench DRAM cell, the f crystal system is disposed on the surface of the substrate, and the capacitance relationship is disposed on the surface formed in the process of forming the trench, and the photomask must be exactly aligned and the semiconductor component is π In the middle, the ratio of the length to the diameter of the deep trench may be 4G. The blood system that forms the capacitor in the deep (4) trench first deposits the dielectric layer on the wire wall, and then fills the layer into the trench. When the ratio of the length to the diameter of the ditch is: If it is greater than 20: 1, it may be difficult to fill the material required to form the capacitor into the 125133⁄4 38twf.doc/006 ditch. [Inventive content] The purpose of the cell is: Providing a kind of dynamic random access memory knows that H is formed on the sidewall of the semiconductor pillar to solve the problem that it is difficult to fill the capacitor and can increase the surface area of the capacitor. Is provided by the dynamic random access (10) structure of the present invention based on the dynamic memory access memory _, because the vertical electro-crystal system is formed in the memory cell, @ this dynamic random access memory array can Have a higher A further object of the present invention is to provide a method for fabricating a dynamic random access memory array, so as to solve the problem that the conventional trench random dynamic access memory is difficult to fill the capacitor H, and to increase the dynamics. Machine access memory component accumulation. ~ The present invention proposes a dynamic random access memory cell (Dynamic
Random Access Memory cell，DRAM cell)，其包括有半 導體柱體、電容器以及垂直式電晶體。其中，半導體柱體 係形成於基底上，且電容器係配置在此半導體柱體下部的 側壁上，此電容器包括有第一電極、介電層以及第二電^。 其中，第一電極係位於半導體柱體下部的側壁中，且介電 層係覆蓋在半導體柱體下部的侧壁上，而第二電極則係覆 蓋在此介電層之上。而垂直式電晶體則係配置在此半導體 柱體上部的側壁上，此電晶體包括有第一摻雜區、第二換 雜區、閘極以及閘絕緣層。其中，第一摻雜區係位在半導 11438twf.doc/006 體柱體的側壁中，並與電容器的第二電極相連接。第二換 在：導體柱體的頂部中，且閘極係配置在第-掺 雜&與第二摻雜區間半導體柱體 係配置在閘極與半導體柱體的側壁之間。而閉心層則 於排ΠΓί動態隨機存取記憶體陣列包括由前述之記憶 、數條位元線以及數條字元線。此記憶 :相同。此基！上’且其結構與前述之記憶胞的結 位元線相‘思 '在單Γ列（rGW)中的第二摻雜區係與 線相連接。’而早一行(c°lumn)中的閘極則係與字元 μ 3 Γ對本發明之動態隨機存取記憶體陣列的製造方 月。首先’將半導體基底圖案化，以在基板 成數行與數列之半導體柱體，再於每一半導體柱 填入i導二形成電容器’接著將第一絕緣材質部分地 體柱，間的間隙’以覆蓋此些電容器。然後於第 、’、冬曰上的每-半導體柱體側壁上形成電晶體的間極結 ，閘極、纟。構包括閘極與閘絕緣層。其中，閘絕緣層係 丄極與半導體柱體之間。再於每一半導體柱體的侧 電晶體的第一推雜區，並與同一半導體柱體上之 目，接’之後在每一半導體柱體之上部中形成電晶 4雜區。在完成電晶體的製造後，接著將第二絕 二、填入每一半導體柱體的間隙中，以覆蓋此些電晶 ⑽。然後在基底上形成數條位元線，其中每一條位元線在 早-列中係與電晶體的第二摻雜區電性連接。另外，在基 12513说 twf.doc/0〇6 底上形成數條字元線，其中每一 過接觸窗而與電晶趙的二:連，線在早-行中係透 配置機存取記憶體陣列中的電晶趙係 有效解決習知上置在深溝渠中，因此可 的任ϋπ、^ 4f科配1在半導體柱體 :任f也就疋說，電容器可配置在記憶胞的任一邊， 所以電日日體能夠有較大的表面面積。 H t由於本發明係將動態隨機存取記憶胞的電晶體 、、晶體，因此能財效地縮Λί、此記憶胞所佔 的橫向面積，並明顯地增加動態隨機存取記憶體陣列的積 集度。換句話說，本發明之動態隨機存取記憶體陣列係具 有較高之積集度。 除此之外，由於本發明之製造動態隨機存取記憶體陣 列的方^中，係於半導體柱體周圍形成電晶體，以解決習 知之溝渠式動態隨機存取記憶體難以將電容器填入的問 題，因此，亦可改善電容器的儲存能力。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 第1圖至第16圖是繪示本發明之一較佳實施例的動態 隨機存取記憶體（Dynamic Random Access Memory， DRAM)陣列之製造流程圖。第1圖係清楚地呈現出此 [oc/006 DRAM陣列的排列之透視圖，第2圖至第9圖、第li圖至第 13圖以及第16 (a)圖是第1圖之Ι-Γ部位的剖面圖，而第16 (b)圖則是第1圖之Ι·Ι’部位的另一剖面圖。第10圖、第14 圖以及第15圖是上視圖。 若以更具體地說法來說明，則第1圖至第6圖是綠示 DRAM陣列之電容器的製造流程圖，第7圖至第12圖是繪 示DRAM陣列之垂直式電晶體的製造流程圖，而第13圖至 第16圖則是繪示後續製程之製造流程圖，包括位元線及字 元線之製造流程圖。 〈電容器之製造方法〉 請參照第1圖，提供一半導體基底100，且半導體基底 100/列如是摻有P型摻質之矽基底。在基底1〇〇上依序形成 整氧化層102以及具有圖案之罩幕層1〇4，且具有圖案之罩 幕層104包括有數行及數列的矩形（或正方形）塊狀物， 而其材質例如是氮化矽。然後利用具有圖案之罩幕層1〇4 作為罩幕，蝕刻基底1〇〇，以形成數行與數列之半導體柱 體L值f注意的是，具有圖案之罩幕層104的塊狀物其 狀還可以是圓形、橢圓形或其他多邊形等等，第1 將錢示成矩形或正方形，但本發明並未對其上視 限定。且半導體柱體11G之形狀也可以是®柱體、 或是與圖案化之罩幕層104的塊狀物之上視形狀 相付的任何多邊形柱體。 jcr 查之4兒日值得特別注意的是，為了方便起見，在本說明 曰ϋ兄明中有時會以半導體柱體U〇同時代表半導體柱體 12513¾ 38twf.doc/006 110以及位於其上之部分的罩幕層刚。 請再參照第_，進行摻 的表面上形成 H首先」在半導體柱體U。間形成具有預定深度 t梦層 rric,^_g)氧化石夕層，並使其填入半導體柱間 f用電極112。此摻質製程例如是包括以下： =即ίΙΞΓ 氧化料’直到其深度達到預定 t 。另外’物氧化石夕層的形成方法還可 二 體柱體110侧壁及基底_上沉積-層砷摻雜 =石=，再彻光阻塗佈法將雜填人半導體柱體ιι〇 ^ 之後再進行回蝕光阻及去除未被光阻覆蓋的砷 t雜氧化，相定祕預定深度。當未_之氧化梦層覆 =在，摻雜氧切層上之後，接著進行熱㈣，以提供坤 摻雜氧化⑪層中之4原子熱能，使其擴散至糾摻雜氧化 石夕層所接觸之半導體柱體11⑽及基底1GG的絲中，以形 成共用電極112。 ★第2圖至第6圖是用以說明電容器的後續製程步驟，其 中第2圖至第6圖是第1圖之Ι-Γ部位的剖面圖。 請參照第2圖，在基底1〇〇以及半導體柱體11〇上形成 ，形之介電層114，而較佳的是，以氧化物層/氮化物層/ 氧化物層（0/N/0)或是氮化物層/氧化物層（N/〇)所組 成之複合層作為電容器之介電層114。接著在半導體柱體 1251335 ll438twf.doc/006 ，如是掺雜N型摻質之多㈣，其形成方法 4如疋先在基底100上沈積一層臨場_換雜㈣itu N_ t^dopmg)之多晶石夕層，並使其填入半導體柱體ιι〇之間 隙中，接著回⑽㈣型掺質之多晶♦層，直到其深度達 ： 到預疋值後即停止回敍。 請參照第3®，將介電層⑴巾未被導· 116所覆蓋 的部分移除，而移除介電層114之方法例如是以濕侧製# 私將其移除。舉例來說，若介電層114為〇]^〇複合層，即 疋說介電層114是依序由氧化物層、氮化物層以及氧化物 層所構成之複合層，則用以移除位於此複合層最上層及最 下層之氧化物層的敍刻液例如是稀釋過的氫氟酸（HF)， 而用以移除氮化物層的蝕刻液例如是磷酸。 請參照第4圖，在導電層n6上的每一半導體柱體n〇 之侧壁上形成絕緣間隙壁H8，且絕緣間隙壁118的材質例 如是氧化石夕，而其形成方法例如是先以化學氣相沈積法將 籲 氧化石夕沈積在導電層116上，再以非等向性姓刻法將其回 蚀。值得注意的是，雖然在此剖面圖中，其所繪示之絕緣 間隙壁118係配置在半導體柱體11〇的兩側，但實際上絕緣 間隙壁118係配置在半導體柱體110的四周且圍繞著半導體 柱體110。然後在導電層116上形成導電層12〇，並覆蓋住 每一絕緣間隙壁118的下部。且導電層120的材質例如是摻 雜N型摻質之多晶矽，而其形成方法例如是先在基底1〇〇 11 I2513^8twfdoc/006 上沈積-層臨場n型摻雜之多㈣層，接著⑽摻雜喃 摻質^日日日:’層，直到其深度賴就紐即停止回餘。 請參照第5®，將每—半導齡體丨關壁上未被導電 層120所覆蓋的絕緣間隙壁118移除，以形成圍繞半導體柱 體110的環狀絕緣層ll8a。接著在半導齡體11G間的導電 層120及環狀絕緣層118a上形成另一導電層122。且導電層 122的材質例如是摻雜汉型摻質之多晶矽，而其形成方^ 例如是先在基底100上沈積一層臨場]^型摻雜之多晶矽 層，接著回蝕摻雜N型摻質之多晶矽層，直到其深度達到 預定值後即停止回蝕。之後，於導電層122上的每一半導 體柱體110之侧壁上形成罩幕間隙壁124，用以定義以下所 述之電容器的上電極，而其厚度例如是大於環狀絕緣層 118a之厚度。 請同時參照第5圖及第6圖，以罩幕間隙壁124作為罩 幕，依序蝕刻導電層122、導電層120以及導電層116，以 ，在每一半導體柱體110下部之侧壁上形成上電極126。值 得注意的是，經過蝕刻製程後所剩餘的導電層丨 上電極126的頂部，其係與半導體柱體11〇的側壁直接接 觸。而上電極126係與介電層H4以及共用電極112 一同構 成電容器127。之後，將罩幕間隙壁124移除，並在半導體 ，體110間形成絕緣層128，以覆蓋半導體柱體11〇間的電 容器127。且絕緣層128的材質例如是氧化矽，而其形成方 式例如是先在基底100上沈積一層氧化矽，使某 底100上，再將其回蝕至所預定之深度。 八 12 12513¾ 38twf.doc/006 而且Random Access Memory cell (DRAM cell), which includes a semiconductor pillar, a capacitor, and a vertical transistor. The semiconductor pillar is formed on the substrate, and the capacitor is disposed on a sidewall of the lower portion of the semiconductor pillar. The capacitor includes a first electrode, a dielectric layer, and a second capacitor. Wherein, the first electrode is located in a sidewall of the lower portion of the semiconductor pillar, and the dielectric layer covers the sidewall of the lower portion of the semiconductor pillar, and the second electrode is overlying the dielectric layer. The vertical transistor is disposed on a sidewall of the upper portion of the semiconductor pillar. The transistor includes a first doping region, a second impurity region, a gate, and a gate insulating layer. Wherein, the first doped region is located in the sidewall of the semiconducting 11438 twf.doc/006 body cylinder and is connected to the second electrode of the capacitor. The second change is in the top of the conductor pillar, and the gate is disposed between the first doped & and the second doped region semiconductor pillar between the gate and the sidewall of the semiconductor pillar. The closed center layer of the dynamic random access memory array includes the aforementioned memory, a plurality of bit lines, and a plurality of word lines. This memory: the same. This base! The upper doped line and the structure of the memory cell are connected to the line of the second doped region in the single-turn column (rGW). The gate in the earlier row (c°lumn) is the character of the dynamic random access memory array of the present invention. First, the semiconductor substrate is patterned to form a plurality of rows and columns of semiconductor pillars on the substrate, and then each semiconductor pillar is filled with a second conductive capacitor to form a capacitor. Then, the first insulating material is partially filled with a body pillar, and the gap therebetween is Cover these capacitors. Then, the inter-electrode junction, the gate and the 纟 of the transistor are formed on the sidewalls of each of the semiconductor pillars on the first, ', and the winter raft. The structure includes a gate and a gate insulating layer. Wherein, the gate insulating layer is between the drain and the semiconductor pillar. Further, in the first dummy region of the side transistor of each of the semiconductor pillars, and on the same semiconductor pillar, an electromorphic region is formed in the upper portion of each of the semiconductor pillars. After the fabrication of the transistor is completed, a second second is then filled into the gap of each of the semiconductor pillars to cover the plurality of crystals (10). A plurality of bit lines are then formed on the substrate, wherein each of the bit lines is electrically connected to the second doped region of the transistor in the early-column. In addition, at the base 12513, a number of word lines are formed on the bottom of twf.doc/0〇6, wherein each of the contact windows is connected with the second crystal of the electro-crystal Zhao, and the line is accessed in the early-line mode. The electric crystal Zhao system in the memory array is effectively solved in the deep trench, so the ϋ π, ^ 4f can be matched in the semiconductor column: any f, the capacitor can be placed in the memory cell On either side, the solar day can have a larger surface area. Since the present invention relates to a transistor and a crystal of a dynamic random access memory cell, it is possible to reduce the lateral area occupied by the memory cell and significantly increase the product of the dynamic random access memory array. Collection. In other words, the dynamic random access memory array of the present invention has a high degree of integration. In addition, since the method of manufacturing the dynamic random access memory array of the present invention forms a transistor around the semiconductor pillar to solve the problem that the conventional trench random dynamic access memory is difficult to fill the capacitor. The problem, therefore, can also improve the storage capacity of the capacitor. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] Figs. 1 to 16 are flowcharts showing the manufacture of a dynamic random access memory (DRAM) array according to a preferred embodiment of the present invention. Fig. 1 clearly shows a perspective view of the arrangement of the [oc/006 DRAM array, and Figs. 2 to 9, Li to Fig. 13, and Fig. 16 (a) are diagrams of Fig. 1 - The cross-sectional view of the Γ portion, and the 16th (b) plan is another cross-sectional view of the Ι·Ι' portion of Fig. 1. Fig. 10, Fig. 14, and Fig. 15 are top views. 1 to 6 are manufacturing flowcharts of capacitors of a green DRAM array, and FIGS. 7 to 12 are manufacturing flow diagrams of a vertical transistor of a DRAM array, if more specifically described. FIG. 13 to FIG. 16 are manufacturing flow charts showing subsequent processes, including a manufacturing flow chart of bit lines and word lines. <Manufacturing Method of Capacitor> Referring to Fig. 1, a semiconductor substrate 100 is provided, and the semiconductor substrate 100/column is a germanium substrate doped with a P-type dopant. A full oxide layer 102 and a patterned mask layer 1〇4 are sequentially formed on the substrate 1 , and the patterned mask layer 104 includes rectangular (or square) blocks having several rows and columns, and the material thereof For example, tantalum nitride. Then, using the patterned mask layer 1〇4 as a mask, the substrate 1 is etched to form a plurality of rows and columns of semiconductor pillars. The value of the F is noted. The patterned mask layer 104 has a block of The shape may also be a circle, an ellipse or other polygon, etc., and the first money is shown as a rectangle or a square, but the invention is not limited to the above. The shape of the semiconductor pillar 11G may also be a column or any polygonal cylinder that is viewed from the shape of the block of the patterned mask layer 104. Jcr's 4th day is worth paying special attention to. For the sake of convenience, in this description, the semiconductor column U〇 sometimes represents the semiconductor pillar 125133⁄4 38twf.doc/006 110 and is located on it. Part of the mask layer just. Referring to the first _, the formation of H on the surface of the doping is first performed on the semiconductor pillar U. An oxide layer having a predetermined depth t dream layer rric, ^_g) is formed and filled into the inter-semiconductor column f electrode 112. This dopant process includes, for example, the following: = ie, the oxidized material 'until its depth reaches a predetermined t. In addition, the formation method of the oxidized stone layer can also be performed on the sidewall of the two-body cylinder 110 and the deposition on the substrate _ arsenic doping = stone =, and then the photoresist filling method is used to fill the semiconductor pillar ιι〇^ Then, the etch back photoresist is removed and the arsenic t-doped oxidation which is not covered by the photoresist is removed, and the predetermined depth is determined. After the oxidized dream layer is over, after the doping of the oxygen-cut layer, heat (4) is then performed to provide the thermal energy of the 4 atom in the layer 11 of the Kun-doped oxidation, which is diffused to the doped oxidized stone layer. The common electrode 112 is formed by contacting the semiconductor pillar 11 (10) and the filament of the substrate 1GG. ★ Fig. 2 to Fig. 6 are diagrams for explaining the subsequent process steps of the capacitor, and Figs. 2 to 6 are sectional views of the Ι-Γ portion of Fig. 1. Referring to FIG. 2, a dielectric layer 114 is formed on the substrate 1 〇〇 and the semiconductor pillar 11 ,, and preferably, an oxide layer/nitride layer/oxide layer (0/N/ 0) A composite layer composed of a nitride layer/oxide layer (N/〇) serves as the dielectric layer 114 of the capacitor. Then, in the semiconductor pillar 1251335 ll438twf.doc/006, if it is doped with N-type dopants (4), the formation method 4 is as follows: depositing a polycrystalline stone on the substrate 100 to form a field-substituting (tetra)itu N_t^dopmg) The layer is filled and filled into the gap between the semiconductor pillars and then back to the (10) (four) type of polycrystalline layer until the depth reaches: After the pre-depreciation, the re-synchronization is stopped. Referring to Section 3®, the portion of the dielectric layer (1) that is not covered by the conductive 116 is removed, and the method of removing the dielectric layer 114 is, for example, removed by wet side. For example, if the dielectric layer 114 is a composite layer, that is, the dielectric layer 114 is a composite layer composed of an oxide layer, a nitride layer, and an oxide layer in sequence, for removal. The engraving liquid located at the uppermost and lowermost oxide layers of the composite layer is, for example, diluted hydrofluoric acid (HF), and the etching liquid for removing the nitride layer is, for example, phosphoric acid. Referring to FIG. 4, an insulating spacer H8 is formed on the sidewall of each of the semiconductor pillars n6 on the conductive layer n6, and the material of the insulating spacers 118 is, for example, oxidized oxide, and the forming method thereof is, for example, The chemical vapor deposition method deposits the oxidized stone on the conductive layer 116 and etches it back by an anisotropic method. It should be noted that although in this cross-sectional view, the insulating spacers 118 are disposed on both sides of the semiconductor pillar 11 ,, the insulating spacers 118 are actually disposed around the semiconductor pillar 110 and Surrounding the semiconductor pillar 110. A conductive layer 12A is then formed over the conductive layer 116 and covers the lower portion of each of the insulating spacers 118. The material of the conductive layer 120 is, for example, a polysilicon doped with an N-type dopant, and the formation method thereof is, for example, depositing a plurality of (four) layers of n-type doping on the substrate 1〇〇11 I2513^8twfdoc/006, and then (10) Doping urethanes ^ Day: 'Layer, until its depth depends on the New Zealand, it will stop returning. Referring to the 5th, the insulating spacers 118 which are not covered by the conductive layer 120 are removed from each of the semi-conducting body walls to form an annular insulating layer 11a surrounding the semiconductor body 110. Next, another conductive layer 122 is formed on the conductive layer 120 and the annular insulating layer 118a between the semi-conductive bodies 11G. The material of the conductive layer 122 is, for example, a polycrystalline germanium doped with a Chinese-type dopant, and the formation thereof is, for example, first depositing a polycrystalline germanium layer on the substrate 100, followed by etch back the doped N-type dopant. The polysilicon layer stops etch back until its depth reaches a predetermined value. Thereafter, a mask spacer 124 is formed on the sidewall of each of the semiconductor pillars 110 on the conductive layer 122 for defining an upper electrode of the capacitor described below, and the thickness thereof is, for example, greater than the thickness of the annular insulating layer 118a. . Referring to FIG. 5 and FIG. 6 simultaneously, the mask spacer 124 is used as a mask to sequentially etch the conductive layer 122, the conductive layer 120 and the conductive layer 116 on the sidewall of the lower portion of each of the semiconductor pillars 110. The upper electrode 126 is formed. It is noted that the conductive layer remaining after the etching process is at the top of the upper electrode 126, which is in direct contact with the sidewall of the semiconductor pillar 11 turns. The upper electrode 126 is formed as a capacitor 127 together with the dielectric layer H4 and the common electrode 112. Thereafter, the mask spacers 124 are removed, and an insulating layer 128 is formed between the semiconductors and the bodies 110 to cover the capacitors 127 between the semiconductor pillars 11. The material of the insulating layer 128 is, for example, yttrium oxide, and is formed by, for example, depositing a layer of yttrium oxide on the substrate 100 to etch back the substrate 100 to a predetermined depth. Eight 12 125133⁄4 38twf.doc/006 and
言月參照第2A圖，在基底100上定義 ^形成共用電極⑴，錢再形成共形之介電層114^於 基底刚上。接者在每—半導體柱體11()_壁上形成 間隙壁216」再於半導體柱體1_形成絕緣層218，且其 上表面^深度例如是與共用電極112之上表面的深度^目 同，或較其為低。絕緣層218的材質例如是氧化矽，而其 ，成方式例如是先在基底刚上沈積—層氧切，使其覆 蓋於基底100上，再將其回餘至所預定之深度。 請參照第3A圖，移除未被絕緣層218所覆蓋的部分導 體間隙壁216以及部分共形之介電層114。而所剩餘的導體 間隙壁216a即為即將形成的上電極之第一部份。Referring to FIG. 2A, a common electrode (1) is formed on the substrate 100, and a conformal dielectric layer 114 is formed on the substrate. The spacers 216 are formed on each of the semiconductor pillars 11'' and the insulating pillars 218 are formed on the semiconductor pillars 1_, and the upper surface thereof is, for example, a depth from the upper surface of the common electrode 112. Same, or lower than it. The material of the insulating layer 218 is, for example, ruthenium oxide, which is formed, for example, by depositing a layer of oxygen on the substrate, covering it on the substrate 100, and returning it to a predetermined depth. Referring to Figure 3A, a portion of the conductor spacers 216 and a portion of the conformal dielectric layer 114 that are not covered by the insulating layer 218 are removed. The remaining conductor spacers 216a are the first portions of the upper electrode to be formed.
請參照第4A圖，在絕緣層上之每一半導體柱體11〇的 側壁上形成絕緣間隙壁118，再於半導體柱體11〇間的導電 層216a與絕緣層218之上形成導電層120，且覆蓋住絕緣間 隙壁118下部。 請參照第5A圖，將每一半導體柱體11〇侧壁上未被導 電層120所覆蓋的部分絕緣間隙壁118移除，以形成圍繞半 導體柱體110的環狀絕緣層118a。接著在半導體柱體110間 的導電層120及環狀絕緣層118a上形成另一導電層122。之 後，於導電層122上的每一半導體柱體110之侧壁上形成罩 幕間隙壁124，用以定義以下所述之電容器的上電極，而 13 1251335 11438twf.doc/0〇6 其厚度例如是大於環狀絕緣層118a之厚度。 請同時參照第5A圖以及第6A圖，以罩幕間隙壁丨24作 為罩幕，依序蝕刻導電層丨22以及導電層120。而蝕刻後所 剩餘之導電層122以及導電層120即與導體間隙壁216a構成 上電極126。其中，導電層122,也就是上電極126的頂部， =係與半導體柱體no的側壁直接接觸。而上電極126係與 ： 介電層114以及共用電極112 —同構成電容器127。之後， · 將罩幕間隙壁124移除，並在半導體柱體110間形成絕緣層 ’ 128 ’使其覆蓋住剩餘之導電層122以及導電層12〇盥絕緣 _ 層 218。 ’、 然而，在上述兩種形成電容器圍繞於每一半導體柱體 的方法中，例如是每一膜層的材質或形成方法，或是膜層 的形成順序，係可存在有些許的修正或變化，而此些修正 或變化，皆可能是涵蓋在本發明之範圍内的。 一/ 〈電晶體之製造方法〉 y請f照第7圖，在形成絕緣層128以使上電極126絕緣 後，接著在每-半導體柱體11G所暴露出的侧壁上形成閘 =層=，且此閘絕緣層130例如是-層薄氧化石夕層，或· 是薄，化物/氮化物層’而其形成方法例如是熱氧化 法或是熱氧化-氮化法。之後在半導體柱體11〇間的絕緣層 ^上形成導電層132，並覆蓋住閘絕緣層130的下部。且 ^電層132的材質例如是掺雜N型摻質的多晶；5夕，而其形 ，方法例如是先在基底丨〇〇上沈積一層臨場N型摻雜 晶石夕層’接著回敍摻雜N型摻質之多晶石夕層，直到其深度 14 1251335 11438twf.doc/006 達到預定值後即停止回餘。 請參照第8圖’在每—半導體柱體H0間的導電層132 j成罩幕_彻4,用以在後續製程中定義閘極。而 罩幕間隙壁134的材質為—絕緣材f，例如是氧化石夕或氮 化石夕。 請參照第9圖至第10圖，其中，第1〇圖是完成以下製 私後所域之結構的上視圖，而第9_是第_2ΐχ_ιχ， 部分的剖面圖。在基底上形成具有圖案之罩幕層ΐ36，其 例如疋具有圖案之轨層。且具有圖案之罩幕層136包括 幻目平行j__1361，其巾每―_贿随在單一 j係覆k住半導體柱體11(m及同行之半導體柱體ιι〇間 的導電層！32。接著以罩幕間隙壁134以及具有圖案之罩幕 層136為罩幕，進行―钱刻製程敍刻導電層132，以在每一 半導體柱體11G的側壁上形成閘極132a。且即使在形成具 有圖案之罩幕層136的過程巾有發生未準確對位的情形， 而導致具有圖案之罩幕層136並未配置在所預期之位置， 但仍然能夠藉由罩幕間隙壁134使閘極132a形成於與其對 應的半導體柱體110四周，並圍繞著其所對應之半導體柱 體110。在單一行中之半導體柱體110侧壁上的閘極132&與 半導體柱體110間蝕刻後剩餘之導電層132a連接而成為閘 2線132a (第1〇圖中之黑點區域），且其可直接作為動態 機存取6己憶體之字元線。而且，在後續製程中可於閘極 線132a上形成另一條低電阻的導電線，並使其與閘極線 132a電性連接以降低其電阻，而此導電線之製程將在之後 15 1251335 11438twf.doc/006 詳細說明。 以是絕緣層130以射細2a之閘極結構還可 動能隨機魏『Γ成’第7AW至第舰圖精示本發明之 二：存取咖陣列的垂直式電晶趙之另一種製造流 产德圖’在形成絕緣層128以使上電極126絕 ^二在基底咖上形成共形之導電層232，其材質例如是 声者在半導體柱體110間的絕緣 I置H x覆蓋住導様32之底部部位。 有足_厚度，可㈣抵抗在後續製程中， =義閘極線之非等向性姓刻製程中所使用的電聚。而 =34的材質例如是氧化石夕，其形成方法例如是先在導 Η ^ !^沈積—層氧切’並將其填人半導體柱體110之 ，隙’然後在騎_製如將氧切_至預定 度。 、請參照第8Α圖以及第1〇Α圖，其中，第ι〇α圖是完成 =下製転後所形成之結構的上視圖，而第8Α_是第職 圖之vm-vnr部分的剖面圖。在基底1〇〇上形成具有圖案 之罩幕層236，其包括有互相平行之線形圖案，而^ =線形圖#2361係在單—行巾的半導體柱體丨闕部上覆 蓋住導電層232以及在同行巾之半導體柱體i關的導電層 232與罩幕層234。接著將未被具有圖案之罩幕層236覆蓋 ，的罩幕層234㈣，叫露出每兩行半導體柱體而 導電層232。 ； 12513¾ twf.doc/006 請參照第9A圖、第8A圖以及第10Λ圖，在每—— 半導體柱體11G間移除罩幕層236,以暴露出剩餘的罩^ 234以及未被其覆蓋住的導電層232。接著利用罩幕層23曰4 作為罩幕，進行一非等向性蝕刻製程，以移除每兩行9 體柱體110間之導電層232在罩幕層234頂端的部分。而$ 同行之半導體柱體110間，由於罩幕層234係覆蓋在導電芦 232之上，相當於導電層232之保護層，因此使得此處之& 電層232在非等向性蝕刻製程中免於被移除。且此非等向 性蝕刻製程需持續進行直到將半導體柱體丨丨〇側壁上的^ 電層232之南度降低至預定的水平面。經過蝕刻製程後， 在每一半導體柱體110侧壁上所剩餘的似間隙壁之導電層 232即為閘極232a。在一行中之半導體柱體11〇側壁上的閘 極232a係與同行之半導體柱體11〇間的導電層幻2相連接而 形成閘極線232a。其中，半導體柱體間的導電層232係因 罩幕層234之保護而未在非等向性蝕刻製程中被移除。而 閘極線232a可直接作為動態隨機存取記憶體之字元線。在 後續製程中可於閘極線132a上形成另一條低電阻的導電 線，並使其與閘極線132a電性連接以降低其電阻。 然而，在上述兩種形成閘極結構圍繞於每一半導體柱 體的方法中，例如是每一膜層的材質或形成方法，或是膜 層的形成的順序，係可存在有些許的修正或變化，而此些 修正或變化，皆可能是涵蓋在本發明之範圍内的。 〈源極/汲極區之形成方法〉 請參照第11圖，形成絕緣層138並填滿半導體柱體u〇 17 125131 f.doc/006 間的間隙，且絕緣層138的材質例如是氧化；g夕，而其形成 方法例如是依序進行化學氣相沈積（Chemical VaporReferring to FIG. 4A, an insulating spacer 118 is formed on a sidewall of each of the semiconductor pillars 11 on the insulating layer, and a conductive layer 120 is formed on the conductive layer 216a and the insulating layer 218 between the semiconductor pillars 11 and And covering the lower portion of the insulating spacer 118. Referring to FIG. 5A, a portion of the insulating spacers 118 on the sidewalls of each of the semiconductor pillars 11 that are not covered by the conductive layer 120 are removed to form an annular insulating layer 118a surrounding the semiconductor pillars 110. Next, another conductive layer 122 is formed on the conductive layer 120 and the annular insulating layer 118a between the semiconductor pillars 110. Thereafter, a mask spacer 124 is formed on the sidewall of each of the semiconductor pillars 110 on the conductive layer 122 for defining the upper electrode of the capacitor described below, and 13 1251335 11438 twf.doc / 0 〇 6 It is larger than the thickness of the annular insulating layer 118a. Referring to FIG. 5A and FIG. 6A simultaneously, the conductive spacer layer 22 and the conductive layer 120 are sequentially etched by using the mask gap wall 24 as a mask. The conductive layer 122 and the conductive layer 120 remaining after the etching constitute the upper electrode 126 with the conductor spacer 216a. Wherein, the conductive layer 122, that is, the top of the upper electrode 126, is in direct contact with the sidewall of the semiconductor pillar no. The upper electrode 126 and the dielectric layer 114 and the common electrode 112 constitute the capacitor 127. Thereafter, the mask spacers 124 are removed and an insulating layer '128' is formed between the semiconductor pillars 110 to cover the remaining conductive layer 122 and the conductive layer 12 insulating layer 218. ', However, in the above two methods of forming a capacitor surrounding each semiconductor pillar, for example, the material or formation method of each film layer, or the order in which the film layer is formed, there may be some correction or variation. And such modifications or variations are possible within the scope of the invention. 1 / <Method of Manufacturing Oxide> y f, according to Fig. 7, after insulating layer 128 is formed to insulate upper electrode 126, then gate = layer is formed on the sidewall exposed by each semiconductor pillar 11G = And the gate insulating layer 130 is, for example, a thin oxide layer, or a thin, compound/nitride layer, and is formed by a thermal oxidation method or a thermal oxidation-nitridation method, for example. Then, a conductive layer 132 is formed on the insulating layer 半导体 between the semiconductor pillars 11 and covers the lower portion of the gate insulating layer 130. And the material of the electric layer 132 is, for example, a polycrystal doped with an N-type dopant; the shape of the method is, for example, first depositing a layer of N-doped crystallized layer on the substrate crucible. The doped layer of doped N-type dopant is stopped until its depth 14 1251335 11438twf.doc/006 reaches a predetermined value. Referring to Fig. 8, the conductive layer 132j between each of the semiconductor pillars H0 is formed as a mask to define a gate in a subsequent process. The material of the mask spacer 134 is - an insulating material f, such as oxidized stone or nitrogen hydride. Please refer to Fig. 9 to Fig. 10, wherein the first drawing is a top view of the structure of the domain after the following manufacturing is completed, and the 9th is a sectional view of the part _2ΐχ_ιχ. A patterned mask layer 36 is formed on the substrate, such as a track layer having a pattern. And the patterned mask layer 136 includes a magical parallel j__1361, and the towel is filled with a semiconductor layer 11 (m and a conductive layer between the semiconductor pillars of the peers! 32). With the mask spacer 134 and the patterned mask layer 136 as a mask, a conductive etching layer 132 is formed to form a gate 132a on the sidewall of each semiconductor pillar 11G. The process towel of the patterned mask layer 136 has an inaccurate alignment, resulting in the patterned mask layer 136 not being disposed at the desired location, but the gate 132a can still be made by the mask spacer 134. Formed around the corresponding semiconductor pillar 110 and surrounding the corresponding semiconductor pillar 110. The gate 132& on the sidewall of the semiconductor pillar 110 in a single row is etched between the semiconductor pillar 110 and the remaining The conductive layer 132a is connected to form the gate 2 line 132a (the black dot area in the first drawing), and it can directly be used as a dynamic machine to access the word line of the memory. Moreover, it can be gated in the subsequent process. Another low resistance conductive is formed on line 132a The wire is electrically connected to the gate line 132a to reduce its resistance, and the process of the conductive line will be described in detail later on 15 1251335 11438 twf.doc/006. Thus, the gate layer of the insulating layer 130 is thinned 2a. The kinetic energy can also be arbitrarily Wei Γ ' ' 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 : : : : : : : : : : : : : : : : : The common conductive layer 232 is formed on the base coffee, and the material thereof is, for example, the insulation between the semiconductor pillars 110 and the H x covering the bottom portion of the guide 32. The thickness of the foot can be (four) resistant In the subsequent process, the non-isotropic surname of the =-gate gate is used for the electro-convergence used in the process. The material of =34 is, for example, oxidized stone, and the formation method is, for example, first deposited in the guide ^ ^ ^ The layer is cut and filled with the semiconductor pillar 110, and then the gap is 'cut, such as oxygen is cut to a predetermined degree. Please refer to Fig. 8 and Fig. 1, where ι〇α The figure is a top view of the structure formed after the completion = lower system, and the eighth Α _ is the vm-vnr part of the first job picture A patterned mask layer 236 is formed on the substrate 1B, which includes linear patterns parallel to each other, and the ^=line pattern #2361 is overlaid on the semiconductor cylinder of the single-row towel. The conductive layer 232 and the conductive layer 232 and the mask layer 234 which are closed in the semiconductor pillars of the wafers. Then, the mask layer 234 (four) which is not covered by the mask layer 236 is called to expose every two rows of semiconductor pillars. The conductive layer 232. 125133⁄4 twf.doc/006 Referring to FIG. 9A, FIG. 8A and FIG. 10, the mask layer 236 is removed between each of the semiconductor pillars 11G to expose the remaining masks 234. And a conductive layer 232 that is not covered by it. Then, using the mask layer 23曰4 as a mask, an anisotropic etching process is performed to remove the portion of the conductive layer 232 between the two rows of the nine-body pillars 110 at the top of the mask layer 234. In the semiconductor pillar 110 between the peers, since the mask layer 234 is over the conductive reed 232, which is equivalent to the protective layer of the conductive layer 232, the electric layer 232 is electrically anisotropically etched. Free from being removed. And the anisotropic etching process is continued until the south of the electroless layer 232 on the sidewalls of the semiconductor pillar is lowered to a predetermined horizontal plane. After the etching process, the spacer-like conductive layer 232 remaining on the sidewall of each of the semiconductor pillars 110 is the gate 232a. The gate 232a on the sidewall of the semiconductor pillar 11 in one row is connected to the conductive layer between the semiconductor pillars 11 of the same row to form a gate line 232a. The conductive layer 232 between the semiconductor pillars is not removed in the anisotropic etching process due to the protection of the mask layer 234. The gate line 232a can be directly used as the word line of the dynamic random access memory. Another low-resistance conductive line may be formed on the gate line 132a in a subsequent process and electrically connected to the gate line 132a to reduce its resistance. However, in the above two methods of forming a gate structure surrounding each semiconductor pillar, for example, the material or formation method of each film layer, or the order in which the film layer is formed, there may be some correction or Variations, and such modifications or variations are possible within the scope of the invention. <Method of Forming Source/Drain Region> Referring to FIG. 11, the insulating layer 138 is formed and filled with a gap between the semiconductor pillars u 125 17131 f.doc/006, and the material of the insulating layer 138 is, for example, oxidized; g, and its formation method is, for example, sequential chemical vapor deposition (Chemical Vapor)
Deposition, CVD)製程以及化學機械研磨（chemical Mechanical Polishing，CMP )製程。 請參照第12圖，將具有圖案之罩幕層1〇4、墊氧化層 102、部分的罩幕間隙壁134以及部分的絕緣層丨38移除， 且例如是進行化學機械研磨製程以移除上述四部分，以便 於罩幕間隙壁134及絕緣層138之上表面與半導體柱體11〇 之上表面共平面。接著將離子束14〇植入每一半導體柱體 110的頂部，以形成摻雜區142作為源極/汲極區，且摻雜 區142可以是掺磷或是摻砷之]^型摻雜區。之後再進行高 溫回火製程，以修復半導體柱體110内部在離子植入製程 中受離子束14G轟擊而產生缺陷的晶格，並驅使上電極126 2摻質擴散至每-半導體柱體11()的側壁中，以形成換 绍^1:4 ^摻雜區142即與摻雜區144、閘極132a以及閘 、文錢直式電晶體145。值躲意的是，雖然前 、’未對雜區144加錢明，但實社，麵紅電極122 ^頂部122後的每—熱製 t 成摻雜區144。6雜區142之後的—高溫回火製程中形 〈位f線與字元線之製造方法〉 方4=至==示此記憶體陣列之位元線的形成 八中弟14圖是完成以下步驟後，最後形成之 18 ltwf.doc/006 結構的上視圖，而第13圖則是第14圖中ΧΙΙΙ·ΧΠΓ部位之 剖面圖。在垂直式電晶體145製造完成後，於基底觸上形 成位疋線146 ’其中’―列中的每-條位元線146係與半導 體柱體11G頂端部狀摻雜區142直接躺。且位元線146 的材質例如是摻雜Ν型摻質之多晶石夕而其形成方法例如是 沈積_圖案化法或是鑲嵌法。此外，還可以在每一條位元 線1J6上沈積-層頂蓋層146卜而且，若形成位元線146與 ，蓋層1461的方法係利用沈積-圖案化製程，則其可以在 每一包括位元線146與頂蓋層1461的結構之侧壁上形成保⑩ 隙壁1462。而頂蓋層1461與保護間隙壁购較佳的是 ^化石夕所構成，且其係用以在後續之接觸窗開口的姓刻 ^転中防止字元線146暴露出，以便於以自行對準（sdf_ gned)之方式形成接觸窗開口。之後，在基底1⑽上形 成絕緣層148覆蓋於位猶146之上，並填滿每兩條位元線 146間的間隙，用以將位元線146與下一步驟所要形 元線絕緣。 弟15圖至弟I6(a)/(b)圖是繪示記憶體陣列中與已形成 之閘極線電性連接之字元線的形成方法流程圖。其中，第 15圖是繪示完成以下步驟後，最後形成之結構的上視圖， ，第16(a)/(b)圖則是分別繪示第丨5圖之A_A，及B-B，部位之 4面圖。在形成絕緣層148後，於基底1〇〇上形成字元線 15〇，且單一行中之每一條字元線150係透過至少一接觸窗 52而在半導體柱體的側壁上與閘極線132a電性連接。 而接觸窗152係與連接同一行中的兩相鄰之半導體柱體u〇 19 I438twf.doc/006 侧壁上的兩閘極132a之導電層132a直接接觸。而接觸窗M2 及字元線150的形成方法例如是先在絕緣層148中形成接觸 窗開口，以暴露出部分的導電層132a，再於絕緣層148上 形成一層導電層，並使其填滿接觸窗開口，以形成接觸窗 152。然後再圖案化此導電層以形成字元線15〇。另外，接 觸窗152及字元線150的形成方法還可以是鑲嵌製程。 请參照弟15圖及第16(a)/(b)圖，由於本發明之dram 中係將電容器127形成於半導體柱體110周圍並圍繞著半導 體柱體110，而不是將其形成於深溝渠中，因此習知之電 谷态難以填入殊溝渠的問題並不存在於本發明中。而且， 由於電谷器127係配置在半導體柱體ho之四邊侧壁上，因 此電容器127的表面面積也較習知之電容器表面面積大。 再者，由於本發明係將DRAM的電晶體製作成垂直 式電晶體，因此能夠有效地縮小每一記憶胞的尺寸，並明 顯地增加DRAM陣列的積集度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖至第16圖是繪示本發明之一較佳實施例的動態 隨機存取記憶體（Dynamic Random Access Memory， DRAM)陣列之製造流程圖。其中，第丨圖至第6圖是繪示 DRAM陣列之電容器的製造流程圖，第7圖至第12圖是繪 12513¾ 38twf.doc/006 示DRAM陣列之垂直式電晶體的製造流程圖，而第13圖至 第16圖則是繪示後續製程之製造流程圖，包括位元線及字 元線之製造流程圖。 第2A圖至第6A圖是本發明之另一較佳實施例的動態 P遺機存取記憶體陣财，其電容||的製造流程剖面圖。 第7A圖至第10A圖是本發明之另—“ a P遺機存取記憶體陣财，其垂直式實施例的動態 造流程剖面圖。 \1體之閘極結構的製Deposition, CVD) process and chemical mechanical polishing (CMP) process. Referring to FIG. 12, the patterned mask layer 1〇4, the pad oxide layer 102, a portion of the mask spacer 134, and a portion of the insulating layer 38 are removed, and for example, a chemical mechanical polishing process is performed to remove The above four parts are such that the upper surface of the mask spacer 134 and the insulating layer 138 are coplanar with the upper surface of the semiconductor pillar 11?. The ion beam 14〇 is then implanted on top of each of the semiconductor pillars 110 to form a doped region 142 as a source/drain region, and the doped region 142 may be doped with phosphorus or doped with arsenic. Area. Then, a high-temperature tempering process is performed to repair the crystal lattice of the semiconductor pillar 110 which is damaged by the ion beam 14G during the ion implantation process, and drives the upper electrode 126 2 dopant to diffuse to each of the semiconductor pillars 11 ( In the sidewall of the substrate, a doping region 142 is formed, that is, a doped region 144, a gate 132a, and a gate and a transistor 145. The value is hidden, although the front, 'not added to the miscellaneous area 144, but the real thing, the red electrode 122 ^ the top 122 after each of the hot t into the doped area 144. 6 after the miscellaneous area 142 — High-temperature tempering process shape <Method of manufacturing bit f line and word line> Square 4 = to == The formation of the bit line of this memory array is shown in Figure 18 after the completion of the following steps. The top view of the ltwf.doc/006 structure, and the 13th view is a cross-sectional view of the ΧΙΙΙ·ΧΠΓ part of Fig. 14. After the vertical transistor 145 is fabricated, the via line 146' is formed on the substrate contact, and each of the - bit lines 146 in the column is directly lying with the top doped region 142 of the semiconductor pillar 11G. Further, the material of the bit line 146 is, for example, a doped yttrium-doped polycrystal, and the formation method thereof is, for example, a deposition-patterning method or a damascene method. In addition, a layer cap layer 146 may be deposited on each bit line 1J6 and, if the bit line 146 and the cap layer 1461 are formed using a deposition-patterning process, they may be included in each A spacer 1062 is formed on the sidewalls of the structure of the bit line 146 and the cap layer 1461. The top cover layer 1461 and the protective gap wall are preferably formed by the fossil eve, and are used to prevent the word line 146 from being exposed in the subsequent contact opening of the contact window opening, so as to be self-aligned. The contact window opening is formed in a sdf_gned manner. Thereafter, an insulating layer 148 is formed over the substrate 1 (10) over the bit 146 and fills the gap between each of the bit lines 146 to insulate the bit line 146 from the desired line of the next step. Figure 15 to Figure I6(a)/(b) is a flow chart showing a method of forming a word line electrically connected to a formed gate line in a memory array. 15 is a top view showing the structure finally formed after the completion of the following steps, and FIG. 16(a)/(b) is a diagram showing A_A of FIG. 5 and BB, respectively. Surface map. After the insulating layer 148 is formed, word lines 15A are formed on the substrate 1 〇, and each of the word lines 150 in a single row is transmitted through at least one contact window 52 on the sidewalls of the semiconductor pillars and the gate lines. 132a is electrically connected. The contact window 152 is in direct contact with the conductive layer 132a of the two gates 132a on the side walls of the two adjacent semiconductor pillars I 19 I438twf.doc/006 in the same row. The contact window M2 and the word line 150 are formed by, for example, forming a contact opening in the insulating layer 148 to expose a portion of the conductive layer 132a, and then forming a conductive layer on the insulating layer 148 and filling it. The window opening is contacted to form a contact window 152. This conductive layer is then patterned to form word lines 15A. In addition, the method of forming the contact window 152 and the word line 150 may also be a damascene process. Referring to FIG. 15 and FIG. 16(a)/(b), since the capacitor 127 is formed around the semiconductor pillar 110 and surrounds the semiconductor pillar 110 in the dram of the present invention, instead of forming it in the deep trench Therefore, the problem that the conventional electric valley state is difficult to fill in the special ditch is not present in the present invention. Further, since the electric grid 127 is disposed on the four side walls of the semiconductor post ho, the surface area of the capacitor 127 is also larger than that of the conventional capacitor. Furthermore, since the present invention fabricates the transistor of the DRAM into a vertical transistor, it is possible to effectively reduce the size of each memory cell and significantly increase the degree of integration of the DRAM array. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 16 are flowcharts showing the manufacture of a dynamic random access memory (DRAM) array in accordance with a preferred embodiment of the present invention. FIG. 6 to FIG. 6 are flowcharts showing the manufacturing process of the capacitor of the DRAM array, and FIGS. 7 to 12 are flowcharts showing the manufacturing process of the vertical transistor of the DRAM array of 125133⁄4 38 twf.doc/006. Figures 13 to 16 are manufacturing flow diagrams showing subsequent processes, including manufacturing flow diagrams of bit lines and word lines. 2A to 6A are cross-sectional views showing the manufacturing process of the dynamic P-transition memory memory of the other preferred embodiment of the present invention. Fig. 7A to Fig. 10A are diagrams showing the dynamic process flow of the vertical embodiment of the "A P legacy access memory array."
【主要元件符號說明】 100 ·基底 102 :墊氧化層 104、136、236 :具有圖案之罩幕層 110 :半導體柱體 9 112 ·共用電極 114 :介電層[Main component symbol description] 100 · Substrate 102 : pad oxide layer 104, 136, 236 : patterned mask layer 110 : semiconductor pillar 9 112 · common electrode 114 : dielectric layer
116、120、122、132、232 :導電層 118 :絕緣間隙壁 118a :環狀絕緣層 124、134 :罩幕間隙壁 126 :上電極 127 :電容器 128、138、218、148 :絕緣層 130 :閘絕緣層 140 :離子束 21 12513¾ 38twf.doc/006 142、144 :摻雜區 145 :垂直式電晶體 146 :位元線 1461 :頂蓋層 1462 :保護間隙壁 150 :字元線 152 :接觸窗 216、216a :導體間隙壁 1361、2361 :線形圖案 132a、232a :閘極（線） 234 :罩幕層116, 120, 122, 132, 232: conductive layer 118: insulating spacer 118a: annular insulating layer 124, 134: mask spacer 126: upper electrode 127: capacitor 128, 138, 218, 148: insulating layer 130: Gate insulating layer 140: ion beam 21 125133⁄4 38twf.doc/006 142, 144: doped region 145: vertical transistor 146: bit line 1461: cap layer 1462: protective spacer 150: word line 152: contact Window 216, 216a: conductor spacers 1361, 2361: linear patterns 132a, 232a: gate (line) 234: mask layer
22twenty two