1248158 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種複合式單邊埋入導電帶結構與製程 方法，尤指一種整合一金屬插塞於單邊埋入導電帶中之複 合式早邊埋入導電f結構與製作方法。 【先前技術】 溝渠式動態隨機存取記憶體(Trench-DRAM)結構是先 在半導體基材中餘刻出深溝渠（deep trench)，再於深溝渠中 製作溝渠電容，然後利用埋入導電帶電連接溝渠電容與金 屬乳化半導體(metal-oxide semiconductor，MOS)電晶體，以 大幅降低記憶胞(memory cell)的橫向單位面積，進而增加 半導體元件的積集度。由於半導體元件的積集度大幅的提 升’為避免二元件之間的相互干擾，埋入導電帶也逐漸演 變成僅具有單邊之埋入導電帶(single sided buried strap， SSBS) ’但由於製程的困難度高，往往造成單邊埋入導電 帶寬度變異性大，進而使得電阻值不穩定而影響電性的表 現’並且因為單邊埋入導電帶較習知埋入導電帶小，所以 1248158 也造成電阻值過高的缺點。 請參考第1圖，第1圖為習知單邊埋入導電帶10之結 構。如第1圖所示，習知單邊埋入導電帶10之結構係設於 一基底12之一深溝渠14中，且深溝渠14分為上溝渠區 16以及下溝渠區18，其中下溝渠區18内設置有一溝渠電 容（圖未示）以及一導電層20與一絕緣氧化層22位於深溝 渠14侧壁表面，而單邊埋入導電帶10設於上溝渠區16 内，並覆蓋於部分下溝渠區18上方。其中上溝渠區16之 側壁與導電層20上方表面另包含一薄氮化矽層24，基底 12表面另包含一墊氮化層26，單邊埋入導電帶10上方則 覆蓋一硬遮罩28。 如習知相關技術者所熟悉，單邊埋入導電帶1〇係利用 硬遮罩28定義出的圖案，接著進行蝕刻製程，以形成單邊 埋入導電帶10。所以硬遮罩28的圖案為製程的關鍵所在。 然而形成硬遮罩28的圖案深受硬遮罩28所位於深溝渠14 中的深度、深溝渠14之臨界尺寸（critical dimension)以及對 位的精確度（alignment accuracy)等之影響，由此可知硬遮 罩28的圖案不易控制，尤其在90nm以下的製程，因此常 常造成前述之單邊埋入導電帶寬度變異性大、電阻值不穩 1248158 定以及電性表現不佳等問題。此外，越來越小的單邊埋入 導電帶及其全由多晶矽組成的結構，也導致電阻值過高的 缺點。 【發明内容】 本發明之主要目的在於提供一種複合式單邊埋入導電 帶結構與製作方法，以改善上述問題。 本發明係揭露一種複合式單邊埋入導電帶結構，此複 合式單邊埋入導電帶結構係設於一基底之一深溝渠中，且 深溝渠係分為上溝渠區以及下溝渠區，而下溝渠區内設置 有一溝渠電容。根據本發明之申請專利範圍，本發明之複 合式單邊埋入導電帶結構包含有一單邊埋入導電帶，設於 上溝渠區内並覆蓋部分下溝渠區，一金屬插塞(metal plug)，鄰接單邊埋入導電帶並與單邊埋入導電帶構成複合 式單邊埋入導電帶，以及一絕緣氧化層，設於深溝渠中並 覆蓋複合式單邊埋入導電帶與下溝渠區。 根據本發明之申請專利範圍，本發明另揭露一種複合 式單邊埋入導電帶之製作方法，其步驟依序包含有提供一 1248158 基底，基底中包含有至少一深溝渠，且深溝渠係分為一上 溝渠區以及一下溝渠區。接著於下溝渠區内形成一溝渠電 容，再於上溝渠區側壁表面與下溝渠區上方形成一襯多晶 石夕層（liner poly)，且襯多晶石夕層於深溝渠内形成一凹洞 (recess)。然後利用自行對準於凹洞中形成一金屬插塞，接 著移除部分概多晶砍層，再形成一硬遮罩覆蓋於部分之概 多晶矽層與金屬插塞，隨後蝕刻未被硬遮罩遮蔽之部分襯 多晶矽層，以形成由部分襯多晶矽層與金屬插塞所構成之 複合式單邊埋入導電帶。最後移除硬遮罩以及形成一絕緣 氧化層於深溝渠中，並覆蓋複合式單邊埋入導電帶與下溝 渠區。 由於本發明之複合式單邊埋入導電帶包含一自行對準 之金屬插塞，所以可以改善習知單邊埋入導電帶電阻值過 高的缺點，並且自行對準之金屬插塞亦是蝕刻時之檔層， 因此可減低硬遮罩圖案不易控制的影響，進而減少單邊埋 入導電帶寬度之變異性，大幅降低電阻值與提高電性表現 的穩定度，所以非常有利於量產的均一性(uniformity)。 為了使貴審查委員能更近一步暸解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 1248158 而所附圖式僅供參考與辅助說明用，並非用來對本發明加 以限制者。 【實施方式】 請參考第2圖與第3圖，第2圖為本發明複合式單邊 埋入導電帶結構應用於陣列佈局之溝渠式動態隨機存取記 憶體30的剖面示意圖，第3圖為依據本發明複合式單邊埋 入導電帶結構70之較佳實施例的剖面示意圖。如第2圖所 示，陣列佈局之溝渠式動態隨機存取記憶體30設於基底 32中，包含有閘極34、36及38、位元線接觸節點(bit line contact node)40、42及44、絕緣氧化層46及48、離子換 雜區50、52、54、56、58及60、具有溝渠電容（圖未示） 之下溝渠區62及64以及本發明之複合式單邊埋入導電帶 66及68。其中閘極34、36及38用以控制電流流量，而電 流係經由位元線接觸節點40、42及44通過相對應之離子 摻雜區50、52、54、56、58及60、複合式單邊埋入導電 帶66及68與下溝渠區62及64内之溝渠電容（圖未示）電 連接。 如第3圖所示，本發明之複合式單邊埋入導電帶結構 1248158 70設於一基底72之一深溝渠74中，且深溝渠74分為上 溝渠區76以及下溝渠區78，而下溝渠區78内設置有一溝 渠電容（圖未示）。本發明之單邊埋入導電帶結構70包含有 一由未摻雜多晶石夕(undoped polysilicon)所構成之單邊埋入 導電帶80設於上溝渠區76内並覆蓋於部分下溝渠區78上 ， 方、一金屬插塞(metal plug) 82鄰接單邊埋入導電帶80並 與單邊埋入導電帶80構成本發明之複合式單邊埋入導電 帶84以及一第一絕緣氧化層86設於深溝渠74中並覆蓋複 籲 合式單邊埋入導電帶84與下溝渠區78。其中，金屬插塞 82係被包覆於單邊埋入導電帶80以及第一絕緣氧化層86 中，並且部分上溝渠區76之侧壁與下溝渠區78上方表面 ， 另包含一薄氮化矽層88，以防止單邊埋入導電帶80與深 溝渠74侧壁間的介面產生差排（dislocation)的現象。其中， 溝渠電容由一摻雜多晶石夕(doped polysilicon)所構成之第一 導電層（圖未示）、一介電層（圖未示）與一埋入電極（圖未示）® 所組成，且埋入電極係位於環繞下溝渠區78之基底72中。 另外，本發明另包含一第二導電層90與一第二絕緣氧化層 92位於下溝渠區78内並連接複合式單邊埋入導電帶84與 · 溝渠電容，其中第二導電層90係為摻雜多晶矽並且第二絕 — 緣氧化層92係位於深溝渠74側壁表面。 · 11 1248158 請參考第4圖至第8圖，第4圖至第8圖為製作本發明 複合式單邊埋人導電帶結構⑽之方法示意圖。如第4圖 所示’首先提供-基底102,且基底搬包含—深溝準辦、 -墊氧化層遍以及-墊氮化層1〇8。其中深溝竿⑽分 為上溝渠區11〇以及下溝渠區112，而下溝渠區内： 置有-溝渠電容（圖未示）、一由摻雜多晶石夕所構成之第一 導電層114以及-第-絕緣氧化層116。其中溝竿 由一換雜多晶石夕第二導電層（圖未示）、一介電層（圖未示/ 與一埋入電極（圖未示)所構成，且埋人電極係位於環繞下 f渠區112之基底102 +。由於深溝渠104中製作溝渠電 容之方法為f知相關技藝者所熟知，故在此不多加資:。 料在上溝渠區no侧壁與第—導電層114表面具有 氮化石夕層118。 如第5圖所示，利用沉積製程於上溝渠區ιι〇側壁表 :與下溝渠區112上方形成均勻性階梯覆蓋之一襯多晶矽 目（WP〇聊0，且襯多晶石夕層12〇於深溝渠1〇4内形成 —凹洞(獄SS)122’接著利用沉積暨回姓刻製程於凹洞122 内形成-自行對準之金屬指塞124。其中概多晶石夕層⑽ 係由未摻雜多晶矽所構成。 12 1248158 如第6圖所示，利用蝕刻製程移除部分襯多晶矽層 120’接著於部分襯多晶矽層120與金屬插塞124上方表面 形成-硬遮罩126 ’硬遮罩126可由氮化石夕所構成。其中 硬遮罩126係定義出接下來欲移除之襯多晶矽層。 如第7圖所示’利用硬遮罩126與部分之金屬插塞 作為㈣擋層，進行蝴製轉除部分襯多⑽層i2Q， 其中未被移除之襯多晶矽層120與金屬插塞124構成本發籲 明之複合式單邊埋入導電帶128。由於本發明係利用硬遮 罩126與部分之金屬插塞124作為蝕刻擋層，所以可以改 善習知僅利用硬遮罩作為蝕刻擋層，而使得單邊埋入導電 帶之形狀及大小深受硬遮罩影響的弊病。 如第8圖所示，接著利用蝕刻製程移除硬遮罩，其 中在蝕刻的過程中，部份未受到遮蔽之薄氮化矽層US以' # 及墊氮化層108亦被移除。另利用沉積製程於深二渠 中形成一第二絕緣氧化層130覆蓋複合式單邊埋入=電帶 128與下溝渠區112，並可利用化學機械研磨, mechanical polish，CMP)等製程來進行平坦化 (planarization) 〇 13 1248158 相較於習知技術，本發明之複合式單邊埋入導電帶包 含一自行對準之金屬插塞，所以可以改善習知單邊埋入導 電帶電阻值過高的缺點，並且自行對準之金屬插塞亦是蝕 刻時之擋層，因此可減低硬遮罩圖案不易控制的影響，進 而減少單邊埋入導電帶寬度之變異性，大幅降低電阻值與 _ 提高電性表現的穩定度，所以非常有利於量產的均一性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 籲 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知單邊埋入導電帶之結構。 第2圖為本發明複合式單邊埋入導電帶結構應用於陣列佈 局之溝渠電容動態隨機存取記憶體的剖面示意圖。 ® 第3圖為依據本發明複合式單邊埋入導電帶結構之較佳實 施例的剖面示意圖。 第4圖至第8圖為製作本發明複合式單邊埋入導電帶結構 、 之方法示意圖。 - 14 1248158 【主要元件符號說明】 10 單邊埋入導電帶 12 基底 14 深溝渠 16 上溝渠區 18 下溝渠區 20 導電層 22 絕緣氧化層 24 薄氣化石夕層 26 墊氮化層 28 硬遮罩 30 溝渠式動態隨機存取 記憶體 32 基底 34 閘極 36 閘極 38 閘極 40 位元線接觸節點 42 位元線接觸節點 44 位元線接觸節點 46 絕緣氧化層 48 絕緣氧化層 50 離子摻雜區 52 離子摻雜區 54 離子摻雜區 56 離子摻雜區 58 離子摻雜區 60 離子摻雜區 62 下溝渠區 64 下溝渠區 66 複合式單邊埋入導電 帶 68 複合式單邊埋入導電 帶 70 複合式單邊埋入導電 帶結構 72 基底 1248158 74 深溝渠 76 上溝渠區 78 下溝渠區 80 單邊埋入導電帶 82 金屬插塞 84 複合式單邊埋入導電 帶 86 第一絕緣氧化層 88 薄氮化矽層 90 第二導電層 92 第二絕緣氧化層 100 複合式單邊埋入導電 帶結構 102 基底 104 深溝渠 106 墊氧化層 108 墊氮化層 110 上溝渠區 112 下溝渠區 114 第一導電層 116 第一絕緣氧化層 118 薄氛化矽層 120 襯多晶矽層 122 凹洞 124 金屬插塞 126 硬遮罩 128 複合式單邊埋入導電 帶 130 第二絕緣氧化層1248158 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a composite single-sided buried conductive strip structure and process method, and more particularly to a composite method in which a metal plug is integrated into a single-sided buried conductive strip. The conductive f structure and the manufacturing method are buried in the early side. [Prior Art] The trench-type dynamic random access memory (Trench-DRAM) structure first fills deep trenches in the semiconductor substrate, and then forms trench capacitances in the deep trenches, and then uses buried conductive strips. A trench capacitor and a metal-oxide semiconductor (MOS) transistor are connected to substantially reduce the lateral unit area of the memory cell, thereby increasing the integration of the semiconductor device. Due to the large increase in the degree of integration of semiconductor components, in order to avoid mutual interference between the two components, the buried conductive tape has gradually evolved into a single sided buried strap (SSBS), but due to the process The difficulty is high, which often results in a large variability in the width of the unilateral buried conductive strip, which in turn makes the resistance value unstable and affects the electrical performance' and because the unilateral buried conductive strip is smaller than the conventional buried conductive strip, 1248158 It also causes the disadvantage that the resistance value is too high. Please refer to Fig. 1. Fig. 1 shows the structure of a conventional one-side buried conductive strip 10. As shown in FIG. 1, the structure in which the conductive strip 10 is buried in one side is disposed in a deep trench 14 of a substrate 12, and the deep trench 14 is divided into an upper trench region 16 and a lower trench region 18, wherein the lower trench A trench capacitor (not shown) is disposed in the region 18, and a conductive layer 20 and an insulating oxide layer 22 are disposed on the sidewall surface of the deep trench 14. The single-sided buried conductive strip 10 is disposed in the upper trench region 16 and is covered by Part of the lower ditch area 18 is above. The sidewall of the upper trench region 16 and the upper surface of the conductive layer 20 further comprise a thin tantalum nitride layer 24, and the surface of the substrate 12 further comprises a pad nitride layer 26, and a single side buried above the conductive strip 10 covers a hard mask 28 . As is well known to those skilled in the art, a single-sided buried conductive strip 1 is patterned using a hard mask 28, followed by an etching process to form a single-sided buried conductive strip 10. Therefore, the pattern of the hard mask 28 is the key to the process. However, the pattern forming the hard mask 28 is deeply affected by the depth of the hard mask 28 in the deep trench 14, the critical dimension of the deep trench 14, and the alignment accuracy. The pattern of the hard mask 28 is not easy to control, especially in the process of 90 nm or less, and thus the above-mentioned single-sided buried conductive strip width variability, resistance value instability 1248158, and poor electrical performance are often caused. In addition, the smaller and smaller single-sided buried conductive strips and their structures consisting entirely of polycrystalline germanium also lead to the disadvantage of excessive resistance. SUMMARY OF THE INVENTION The main object of the present invention is to provide a composite single-sided buried conductive strip structure and a manufacturing method thereof to improve the above problems. The invention discloses a composite single-sided buried conductive strip structure, the composite single-sided buried conductive strip structure is arranged in a deep trench of a base, and the deep trench canal is divided into an upper ditch zone and a lower ditch zone. A trench capacitor is disposed in the lower trench region. According to the patent application scope of the present invention, the composite single-sided buried conductive strip structure of the present invention comprises a single-sided buried conductive strip disposed in the upper trench region and covering a portion of the lower trench region, a metal plug. Adjacent to the single-sided buried conductive strip and embedded with a single-sided conductive strip to form a composite single-sided buried conductive strip, and an insulating oxide layer, which is disposed in the deep trench and covers the composite single-sided buried conductive strip and the lower trench Area. According to the patent application scope of the present invention, the present invention further discloses a method for fabricating a composite single-sided buried conductive strip, the steps of which include providing a 1248158 substrate, the substrate including at least one deep trench, and the deep trench system It is an upper ditch area and a ditch area. Then, a trench capacitor is formed in the lower trench region, and a liner polylin layer is formed on the sidewall surface of the upper trench region and the lower trench region, and the polycrystalline lining layer forms a concave in the deep trench. Recess. Then, a metal plug is formed by self-aligning into the cavity, and then a portion of the polycrystalline layer is removed, and then a hard mask is formed to cover a portion of the polysilicon layer and the metal plug, and then the etching is not hard masked. The masked portion is lined with a polysilicon layer to form a composite single-sided buried conductive strip composed of a partially lined polysilicon layer and a metal plug. Finally, the hard mask is removed and an insulating oxide layer is formed in the deep trench, and the composite single-sided buried conductive strip and the lower trench region are covered. Since the composite single-sided buried conductive strip of the present invention comprises a self-aligned metal plug, the disadvantage of the conventional single-sided buried conductive strip having an excessively high resistance value can be improved, and the self-aligned metal plug is also The layer layer during etching can reduce the influence of the hard mask pattern from being difficult to control, thereby reducing the variability of the width of the buried side of the conductive strip, greatly reducing the resistance value and improving the stability of the electrical performance, so that it is very advantageous for mass production. Uniformity. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The accompanying drawings are for reference only, and are not intended to limit the invention. [Embodiment] Please refer to FIG. 2 and FIG. 3, and FIG. 2 is a schematic cross-sectional view of a trench type dynamic random access memory 30 in which a composite single-sided buried conductive strip structure is applied to an array layout, FIG. A cross-sectional view of a preferred embodiment of a composite single-sided buried conductive strip structure 70 in accordance with the present invention. As shown in FIG. 2, the trench-type dynamic random access memory 30 of the array layout is disposed in the substrate 32 and includes gates 34, 36 and 38, bit line contact nodes 40, 42 and 44. Insulating oxide layers 46 and 48, ion exchange regions 50, 52, 54, 56, 58 and 60, with trench capacitances (not shown) under trench regions 62 and 64 and composite unilateral embedding of the present invention Conductive strips 66 and 68. The gates 34, 36 and 38 are used to control the current flow, and the current is passed through the bit line contact nodes 40, 42 and 44 through the corresponding ion doping regions 50, 52, 54, 56, 58 and 60, composite The unilateral buried conductive strips 66 and 68 are electrically connected to the trench capacitors (not shown) in the lower trench regions 62 and 64. As shown in FIG. 3, the composite single-sided buried conductive strip structure 1248158 70 of the present invention is disposed in a deep trench 74 of a substrate 72, and the deep trench 74 is divided into an upper trench region 76 and a lower trench region 78, and A trench capacitor (not shown) is disposed in the lower trench region 78. The single-sided buried conductive strip structure 70 of the present invention comprises a single-sided buried conductive strip 80 composed of undoped polysilicon disposed in the upper trench region 76 and covering a portion of the lower trench region 78. The metal plug 82 is adjacent to the single-sided buried conductive strip 80 and is embedded with the conductive strip 80 on one side to form the composite single-sided buried conductive strip 84 of the present invention and a first insulating oxide layer. 86 is disposed in the deep trench 74 and covers the double-embedded conductive strip 84 and the lower trench region 78. The metal plug 82 is coated on the single-sided buried conductive strip 80 and the first insulating oxide layer 86, and partially on the sidewall of the trench region 76 and the upper surface of the lower trench region 78, and further comprises a thin nitride. The layer 88 is formed to prevent the dislocation of the interface between the conductive strip 80 and the sidewall of the deep trench 74 on one side. The trench capacitor is composed of a doped polysilicon, a first conductive layer (not shown), a dielectric layer (not shown), and a buried electrode (not shown). The composition and buried electrodes are located in the substrate 72 surrounding the lower trench region 78. In addition, the present invention further includes a second conductive layer 90 and a second insulating oxide layer 92 in the lower trench region 78 and connected to the composite single-sided buried conductive strip 84 and the trench capacitor, wherein the second conductive layer 90 is The polycrystalline germanium is doped and the second insulating edge oxide layer 92 is located on the sidewall surface of the deep trench 74. · 11 1248158 Please refer to Figures 4 to 8, and Figures 4 to 8 are schematic views showing the method of fabricating the composite single-sided buried conductive strip structure (10) of the present invention. As shown in Fig. 4, the substrate 102 is first provided, and the substrate is loaded with a deep trench, a pad oxide layer, and a pad nitride layer 1〇8. The deep gully (10) is divided into an upper ditch zone 11 〇 and a lower ditch zone 112, and a lower ditch zone: a ditch capacitor (not shown), a first conductive layer 114 composed of doped polysilicon And a -th insulating oxide layer 116. The gully is composed of a second conductive layer (not shown) and a dielectric layer (not shown/embedded with an embedded electrode (not shown), and the buried electrode is located around The base 102 + of the lower d-channel region 112. Since the method of making the trench capacitance in the deep trench 104 is well known to those skilled in the art, there is no additional capital here: the no-side wall and the first conductive layer in the upper trench area The surface of 114 has a nitride layer 118. As shown in Fig. 5, a deposition process is used in the upper dam area of the upper ditch area: a uniform step coverage is formed over the lower ditch area 112 to line the polycrystalline eye (WP 0 0, The lining of the polycrystalline stone layer 12 is formed in the deep trench 1〇4—the recess (prison SS) 122', and then the self-aligned metal finger plug 124 is formed in the cavity 122 by the deposition and etch process. The polycrystalline spine layer (10) is composed of undoped polysilicon. 12 1248158 As shown in FIG. 6, the partially lined polysilicon layer 120' is removed by an etching process, followed by the partially lined polysilicon layer 120 and the metal plug 124. Surface Forming - Hard Mask 126 'The hard mask 126 may be formed by a nitride ray. The mask 126 defines the polysilicon layer to be removed next. As shown in Fig. 7, 'using the hard mask 126 and a part of the metal plug as the (four) barrier layer, the butterfly is removed and the partial lining (10) layer i2Q is performed. The lining polysilicon layer 120 and the metal plug 124, which are not removed, constitute the composite single-sided buried conductive strip 128 of the present invention. Since the present invention utilizes the hard mask 126 and a portion of the metal plug 124 as an etch stop. Layer, so it can be improved to use only the hard mask as the etch stop layer, so that the shape and size of the single-sided buried conductive strip is deeply affected by the hard mask. As shown in Fig. 8, the etching process is then used. In addition to the hard mask, during the etching process, part of the unmasked thin tantalum nitride layer US is removed by the '# and pad nitride layer 108. Another deposition process is used to form a first layer in the deep two channels. The second insulating oxide layer 130 covers the composite single-sided buried=electric strip 128 and the lower trench region 112, and can be planarized by a chemical mechanical polishing, mechanical polish, CMP) process. 13 1248158 compared to the ha Known technology, composite form of the invention The buried conductive strip includes a self-aligned metal plug, so that the conventional one-side buried conductive strip has a high resistance value, and the self-aligned metal plug is also a barrier layer during etching, so Reducing the influence of the hard mask pattern that is difficult to control, thereby reducing the variability of the width of the buried side of the conductive strip, greatly reducing the resistance value and improving the stability of the electrical performance, so it is very advantageous for the uniformity of mass production. For the preferred embodiment of the present invention, the equivalent changes and modifications made to the specific scope of the application of the present invention are within the scope of the present invention. [Simplified Schematic] FIG. 1 is a conventional unilateral The structure of the buried conductive tape. Fig. 2 is a schematic cross-sectional view showing a trench-capacitor dynamic random access memory of a composite single-sided buried conductive strip structure applied to an array layout. ® Fig. 3 is a schematic cross-sectional view showing a preferred embodiment of a composite single-sided buried conductive strip structure in accordance with the present invention. 4 to 8 are schematic views showing a method of fabricating the composite single-sided buried conductive strip structure of the present invention. - 14 1248158 [Description of main components] 10 Single-sided buried conductive strip 12 Substrate 14 Deep trench 16 Upper trench area 18 Lower trench area 20 Conductive layer 22 Insulating oxide layer 24 Thin gas fossil layer 26 Pad nitride layer 28 Hard cover Cover 30 Ditch Dynamic Random Access Memory 32 Substrate 34 Gate 36 Gate 38 Gate 40 Bit Line Contact Node 42 Bit Line Contact Node 44 Bit Line Contact Node 46 Insulation Oxide Layer 48 Insulation Oxide Layer 50 Ion Doping Miscellaneous region 52 ion doped region 54 ion doped region 56 ion doped region 58 ion doped region 60 ion doped region 62 lower trench region 64 lower trench region 66 composite unilateral buried conductive strip 68 composite unilateral burial Into the conductive strip 70 composite single-sided buried conductive strip structure 72 base 1248158 74 deep trench 76 upper ditch area 78 lower ditch area 80 single side buried conductive strip 82 metal plug 84 composite single side buried conductive strip 86 first Insulating oxide layer 88 thin tantalum nitride layer 90 second conductive layer 92 second insulating oxide layer 100 composite single-sided buried conductive strip structure 102 substrate 104 deep trench 106 pad oxide layer 108 pad Layer 110 Upper Ditch Zone 112 Lower Ditch Zone 114 First Conductive Layer 116 First Insulating Oxide Layer 118 Thin Cavitation Layer 120 Lined Polysilicon Layer 122 Cavity 124 Metal Plug 126 Hard Mask 128 Composite Single Side Buried Conductor Strip 130 second insulating oxide layer