200907907 九、發明說明： 【發明所屬之技術領域】 本發明係關於-翻觸示找f時間輕方法及其相關裝 置’尤指-_於顯示器透過調整—水平信號時間，以縮短影像 資料輸出時間之充電時間調整方法及其相關裝置。 【先前技術】 隨著顯示技術進步，新—代的低溫多晶㈣膜電晶體液晶顯 示器（LowTemperatureP〇ly柳c〇nTFT_LCD，ltpstftlcd) 逐漸又到重視’其具有低成本、高開口率、外型輕薄及省電等優 點，因而廣泛應用於如數位相機、攝影機、車用電視等中小尺忖 的電子產品。低溫多晶石夕液晶顯示器的製程過雷射回火㈤财 Α_υ ’將非紗（a-Si)的_轉變為多晶_膜層，進而於 玻璃基板上形成薄膜電晶體。因此，她於非晶魏晶顯示器， 低溫多晶魏晶顯示n之電晶體的電子移鱗大幅提昇百倍，使 反應時間籠10倍以上。除此之外，部分的驅動電路可製作於玻 璃基板上’以郎省印刷電路板的面積。 一明參考第1圖’第1圖為習知低溫多晶石夕液晶之一顯示器1〇 之示意圖。顯示器10包含一面板12、一時序控制器（Timing Controller) 100、一源極驅動器（s〇urceDriver) ιι〇、一閘極驅動 器（GateDriver) 120及多工切換器贿―sw〜Μυχ sw2〇。 面板12為-解析度·X24〇的低溫多晶石夕面板，且閘極驅動器 200907907 120及多工切換器MUX—SW1〜mux__SW2〇皆設置於面板12上。 閘極驅動器120控制掃描線1〜240的開關；源極驅動器11〇 一次 能輸出24個通道的影像資料；多工切換器Μυχ swi〜 MUX一SW20則分別負責24條通道的資料輸出。時序控制器1〇〇 傳送影像資料至源極驅動器110，並傳送掃描控制信號ΕΝβν、起 始控制信號STH、時脈信號CKH1及極性信號VC〇M至面板12。 掃描控制信號ENBV用來驅動閘極驅動器12〇打開或關閉一條掃 描線；起始控制信號STH為一資料輸出的起始信號；極性信號 VCOM时提供面板u上液晶電容醇考賴，並於每條掃描線 之間轉換極性。請繼續參考第2圖，第2圖為顯示器ω之相關信 號波形圖。-般來說，顯示器1G遵循#界相的顯示定時規範， 如視訊電子標準協會（Video Electr〇nics StandardsA_iatiQn， VESA)所提出的廣義定時公式（GeneralizedTim^gF瞻也， GTF)。因此’根據相關規範，顯示器戦利用—水平信號時間 來處理-條掃描線的資料輸出及控制。水平信號時間即為一水平 同=信號HSyne的兩個低態的相隔時間，且包含—前廊時間附、 -資料顯示時間DT及—後廊時間Βρτ。在第2圖中，—資料輸 入信號DIN絲源铜則接收影像:雜的時間，並且也^ :時脈信號CKm之_ SR1〜㈣的總時間長度。根據第2圖， =板12接收到掃描控制信號ENBV及起始控制信號咖後，200907907 IX. INSTRUCTIONS: [Technical field of the invention] The present invention relates to a method of flipping light and a related device, especially a display-adjusting-level signal time, to shorten the output time of image data. The charging time adjustment method and related devices. [Prior Art] With the advancement of display technology, the new generation of low-temperature polycrystalline (tetra) film transistor liquid crystal display (LowTemperatureP〇ly willow c〇nTFT_LCD, ltpstftlcd) gradually pays attention to its low cost, high aperture ratio, appearance Lightweight and power-saving, it is widely used in electronic products such as digital cameras, cameras, and TVs. The process of low-temperature polycrystalline celite liquid crystal display has been subjected to laser tempering (5) Α υ υ ’ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, in the amorphous Weijing display, the low-temperature polycrystalline Weijing shows that the electron transfer scale of the crystal of n is greatly increased by a hundred times, and the reaction time cage is more than 10 times. In addition to this, part of the drive circuit can be fabricated on a glass substrate to the area of the printed circuit board. 1 is a schematic view of a conventional display of a low temperature polycrystalline lithospherical liquid crystal. The display 10 includes a panel 12, a Timing Controller 100, a source driver (s〇urceDriver) ιι〇, a gate driver (GateDriver) 120, and a multiplexer switch-sw~Μυχsw2〇. The panel 12 is a low temperature polycrystalline slab of - resolution X24, and the gate driver 200907907 120 and the multiplexer switches MUX_SW1 to mux__SW2 are all disposed on the panel 12. The gate driver 120 controls the switches of the scan lines 1 to 240; the source driver 11 能 can output image data of 24 channels at a time; the multiplexer Μυχ swi~ MUX-SW20 is responsible for data output of 24 channels respectively. The timing controller 1 transmits image data to the source driver 110, and transmits a scan control signal ΕΝβν, a start control signal STH, a clock signal CKH1, and a polarity signal VC〇M to the panel 12. The scan control signal ENBV is used to drive the gate driver 12 to turn on or off a scan line; the start control signal STH is the start signal of a data output; the polarity signal VCOM provides the liquid crystal capacitor on the panel u, and each The polarity is switched between the scan lines. Please continue to refer to Figure 2, which is a waveform diagram of the associated signal of display ω. In general, the display 1G follows the display timing specification of the #boundary phase, such as the generalized timing formula proposed by the Video Electr〇nics Standards A_iatiQn (VESA) (Generalized Tim^gF, also, GTF). Therefore, according to the relevant specifications, the display uses the horizontal signal time to process the data output and control of the -scan lines. The horizontal signal time is the interval between the two low states of the same signal = HSyne, and includes - front corridor time attachment, - data display time DT and - porch time Β ρτ. In Fig. 2, the data input signal DIN wire source copper receives the image: the time of the impurity, and also ^: the total time length of the clock signal CKm_SR1~(4). According to FIG. 2, after the = board 12 receives the scan control signal ENBV and the start control signal,
〜SR20之間，源極驅動請輪出影像資料至通道！ 〜彻。其中，輸出的方式為於時脈_獨，多工切U _^-$谓4了開，而源極驅動器則透過多卫切換器職_ 200907907Between ~SR20, the source driver please turn out the image data to the channel! ~thorough. Among them, the output mode is in the clock_independence, the multiplex cut U _^-$ is 4, and the source driver is through the multi-switch switch _ 200907907
Qiamiell〜Channel%的影像#料；於時脈啦期 間’多工切換器mux_SW2打開’而源極驅動器ιι〇透過多工切 換器MUX—SW2依序輸出通道Channd25〜channd48的影像資 料’以此類推，最後於時脈SR2〇_，多工切換器刚^—S侧 打開，而源極驅動器i!〇透過多工切換器MUX_sw2〇依序輸出通 道Channe1457〜Channe_的影像資料。因此，時脈SRi〜s㈣ 的總時間長度即為水平信號時間的資料顯示時間DT。顯示器10 =用線極性轉換（LineInversi()n)的顯示方式，因此於掃描控制 信號ENBV打_描線之時，極性信號vc〇M開始轉態，並於時 脈SR20之前維持其極性。 在顯示器10巾，時序控制器100的輸出資料與源極驅動器 no的輸出具有即時輸出關係。也就是說，當影像資料及控制信號 由時2控制器100輸出至源極驅動器11()時，經過數個時脈週期 的運算後，立即輸出至面板12上。此外，由於顯示器1〇採用線 和f轉換所以極街s^|VC〇M的起始轉態時間與時脈如相隔 的時間為11定的。在此情況下，若面板12上的極性信號Vc〇M 迴路的rc負載效應過大時，極性信號vc〇M可能無法於影像資 料輸出的第—個時脈（時脈SR1)之前到達預定的電壓準位，導 致通道1〜24的影像資料與極性信號VCOM的電壓差不同於通道 25 480的影像資料與極性信號的電壓差。在此情形下， 通道1〜24與通道25〜48〇的液晶分子偏轉相位不一致，將產生 ‘.、、貝丁〜像不均勻’也就是「前Band」的現象，其相關信號波形圖 200907907 如弟3圖所示。 此外，當顯示器10的環境溫度低於(TC時，面板12上電路 的電子移動轉因溫度過低而魏，導致影像倾的輸出電壓對 液晶的充電速度隨之變慢。如此一來，每條掃描線後端的通道（通 道457 480)在未充電到職的電壓準位之前，控制信號e湘v 已經關閉掃描線，亦造成顯示影像不均勻，也就是「後㈤」的 現象。請同時參考第4圖及第5圖，第4圖為顯示器1〇之面板12 上之相關充電電容之示意圖；第5圖為顯示器1〇在「後 的現象下糊信號波形圖。由第4圖可知，透過控制錢enbv， 閘極信號Gate可導通電容CDatal〜CData48〇與液晶電容cLa 〜CLC480的對應連結。在時脈SR1〜SR2〇期間，多工切換信號 HSR1〜HSR20會依序打開多工切換器湖^』，〜 MUX_SW2G ’使f彡像㈣輸出賴奶血對電容⑽拉卜 CData480進行充電。電容cDatal〜CData480接著對液晶電容 CLC1〜CLC480進行充電’而液晶電容CLC1〜CLC48_充電參 考電壓即為極性信號VCOM的電壓。第5圖顯示輸出資料電壓 VData以及液晶電容電壓VLC在25°C及-l〇°C下的充電波形。由 第5圖可知，25°C的液晶電容電壓VLC充電速度較_1〇<5(：的快，且 在控制信號ENBV關閉掃描線時，通道457〜48〇的_1〇c>c的液晶 電容電壓VLC尚未充至輸出資料電壓.VData的準位，造成「後 Band」的現象。請參考第ό圖，第ό圖為顯示器1〇同時出現「前 Band」及「後Band」現象的顯示畫面之示意圖。第6圖顯示畫面 200907907 左右端與中央部份的色彩顯示不均。 【發明内容】 因此，本發明提供一種 ㈣ 相關裝置，魏卿繼方= 過長或液晶充電時間不μ造成_畫面色彩 本發明係揭露一種用於一顧 法包含有贿—影像資 4之充树_整方法。該方 組錢數伽二像資料分成複數個影像資料群 _包含一前廊料間，該_ 該水伴倾現貞和销及—麵咖；以及於 群組。間之§_顯示時間，依序輸出該複數個影像資料 含有一預存7揭路—種用於—顯示器之充電時間調整裳置，其包 較佳地 一影像資料多晶销示11。該預存單元用來儲存 資料八成、11料處理單元耦接於該預存單元，用來將該影像 序控“:，===制_根據複數個時 前廊時間…Γ 虎關，其中該水平信號時間包含— 預存單元及^料顯示時間及一後廊時間。該輸出單元執接於該 示時間，依序 =!!處理單元，用來於該水平信號時間之該資料顯 序輪出該複數個影像資料群組。 200907907 【實施方式】 二 > 考第7圖’第7圖為本發明實施例一充電時間調整流程 之不思®。充電時間調整流程％用於一顯示器中調整充電時 間，其包含下列步驟： 步驟700 :開始。 步驟702:储存—影像資料。 步驟71將該影像資料分成複數個影像資料群組。 4 706根據複數個時序控制信號，調整一水平信號時間， 該水平彳§號時間包含—前廊時間、—資料顯示時間 及一後廊時間。 步驟708 於該水平信號時間之該資料顯示時間，依序輸出該 複數個影像資料群組。 步驟710 :開始。 旦整流程7〇，本發明係將影像資料分成複數個 :=二並根據時序控制信號，調整水平信號時間，進而 植因I ^ Γ該資料顯示時間，依序輸出複數個影像資料群 听=’「if财平錄咖，充树_整餘％可解決 .，，、頁不旦面月ϋ Band」及「後Band」的問題。 較佳地’ feU &含數歸躲及 «.I ^ (Line,,Line) 示器另提供一時脈信號及一極性信號，其中極性;個旦面。顯 的影像資料群叫權。❹卜，姻來給輸出 不料1的像素可分成 200907907 複數個像素群組’並對應至複數個影像f 充電時間調整流程70巾，難水平·、、、另—方面’在 時間，或輕倾顯科間之—可包含驗資料顯示 ;二對於，時__二:== 曰加時脈仏唬的頻率來縮短資料顯示過 ^時間狀咖下，_軸奴㈣ 二示器時，透過增加前廊時間，顯示器内部的極性信 間，輪㈣後一組像:群=:增， ^的_位’也就是對應__群組之輸_ ^下，充電軸腫流㈣可解麵示晝面Qiamiell~Channel% of the image #料; during the clock period, the 'multiplexer switch mux_SW2 is turned on' and the source driver ιι〇 through the multiplexer switch MUX-SW2 sequentially outputs the channel Channd25~channd48 image data and so on and so on Finally, at the clock SR2〇_, the multiplexer switch is turned on, and the source driver i!〇 outputs the image data of the channels Channe1457~Channe_ sequentially through the multiplexer MUX_sw2. Therefore, the total time length of the clock SRi~s(4) is the data display time DT of the horizontal signal time. Display 10 = display mode with line polarity switching (LineInversi()n). Therefore, when the scan control signal ENBV is drawn, the polarity signal vc〇M starts to change state and maintains its polarity before the clock SR20. At the display 10, the output of the timing controller 100 has an immediate output relationship with the output of the source driver no. That is, when the video data and the control signal are output from the controller 2 to the source driver 11 (), the operation is output to the panel 12 immediately after the calculation of several clock cycles. In addition, since the display 1〇 uses line and f conversion, the initial transition time of the pole street s^|VC〇M is set to 11 as the time interval between the clocks. In this case, if the rc load effect of the polarity signal Vc〇M loop on the panel 12 is too large, the polarity signal vc〇M may not reach the predetermined voltage before the first clock (clock SR1) of the image data output. The level difference causes the voltage difference between the image data of the channels 1 to 24 and the polarity signal VCOM to be different from the voltage difference between the image data of the channel 25 480 and the polarity signal. In this case, the deflection phases of the liquid crystal molecules of the channels 1 to 24 and the channels 25 to 48 are inconsistent, and a phenomenon of '., bedding ~ image unevenness, that is, "front band" is generated, and the related signal waveform diagram is 200907907. As shown in Figure 3. In addition, when the ambient temperature of the display 10 is lower than (TC, the electronic movement of the circuit on the panel 12 is too low due to the temperature, so that the output voltage of the image tilts the charging speed of the liquid crystal to be slower. Thus, each The channel at the back end of the scan line (channel 457 480) has turned off the scan line before the uncharged voltage level is applied. This also causes the display image to be uneven, which is the "post (five)" phenomenon. Referring to Figures 4 and 5, Figure 4 is a schematic diagram of the relevant charging capacitor on the panel 12 of the display 1; Figure 5 is a waveform diagram of the paste signal under the phenomenon of the display 1 。. It can be seen from Fig. 4. By controlling the money enbv, the gate signal Gate can turn on the corresponding connections of the capacitors CData1~CData48〇 and the liquid crystal capacitors cLa to CLC480. During the clocks SR1 to SR2, the multiplexed switching signals HSR1 to HSR20 will sequentially turn on the multiplex switching.器湖^』,~ MUX_SW2G 'make the image of the 彡 (4) output Lai milk to charge the capacitor (10) Rab CData480. Capacitors cData1~CData480 then charge the liquid crystal capacitors CLC1~CLC480' and the liquid crystal capacitors CLC1~CLC48_ The electrical reference voltage is the voltage of the polarity signal VCOM. Figure 5 shows the charging waveform of the output data voltage VData and the liquid crystal capacitor voltage VLC at 25 ° C and -10 ° C. As can be seen from Fig. 5, the liquid crystal at 25 ° C The charging voltage VLC charging speed is faster than _1 〇 < 5 (:, and when the control signal ENBV turns off the scanning line, the liquid crystal capacitor voltage VLC of the channel 457 〜 48 〇 〇 & c > c is not charged to the output data voltage The position of .VData causes the phenomenon of “Post Band”. Please refer to the figure below. The figure below shows the display screen of the “Before Band” and “Bear Band” phenomenon at the same time. Figure 6 shows the screen. 200907907 The color display of the left and right ends and the central part is uneven. [Invention] Therefore, the present invention provides a (4) related device, Wei Qing Jifang = too long or the liquid crystal charging time is not caused by _ screen color. The present invention discloses a use In one method, there is a method of bribery-images. The method is divided into a plurality of image data groups, including a front porch, which - face coffee; and in the group. §_Display time, sequentially output the plurality of image data, including a pre-stored 7-road, which is used for the charging time adjustment of the display, and the package preferably has an image data polycrystalline display 11. The pre-stored unit is used for To store data 80%, 11 material processing unit is coupled to the pre-stored unit, used to sequence the image ":, === system_ according to a plurality of time front corridor time ... 虎 Tiger off, where the horizontal signal time contains - pre-stored The unit and the material display time and a porch time. The output unit is connected to the display time, and the processing unit is used to rotate the plurality of image data groups in the data display sequence of the horizontal signal time. group. 200907907 [Embodiment] FIG. 7 is a diagram of the charging time adjustment process in the embodiment of the present invention. The charging time adjustment process % is used to adjust the charging time in a display, which includes the following steps: Step 700: Start. Step 702: Store - image data. Step 71 divides the image data into a plurality of image data groups. 4 706 adjusts a horizontal signal time according to a plurality of timing control signals, the horizontal 彳 § time includes - front corridor time, - data display time and a porch time. Step 708: output the plurality of image data groups in sequence according to the data display time of the horizontal signal time. Step 710: Start. The whole process is 7〇, the invention divides the image data into a plurality of:=2 and adjusts the horizontal signal time according to the timing control signal, and then the cause I ^ Γ the data display time, sequentially outputs a plurality of image data groups to listen = 'If I can record the coffee, fill the tree _ the whole amount can be solved.,,, the page is not the face of the moon, the band" and the "post-Band" problem. Preferably, the 'feU & contains the number and the «.I ^ (Line,, Line) indicator provides a clock signal and a polarity signal, wherein the polarity; The group of visible image data is called. ❹ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,显科-- can include the test data display; second, when __ two: == 曰加脉仏唬 frequency to shorten the data display ^ time-like coffee, _ axis slave (four) two display, through Increase the front corridor time, the polarity inside the display, the round (four) after the group like: group =: increase, ^ _ bit 'that is corresponding to the __ group of the loss _ ^, the charging shaft swollen (four) solvable Demonstration
Band」的問題。 」久傻 。月參考第8圖，第8圖為本發明實施例用於一顯示器之 電時間調整|置8G之示意圖。顯示^包含數條掃描線及資料線， 其=成矩陣示像素排列，並__示方式aine-by_Line)來顯 不整各晝面。其中，每一列的像素分成像素群組PG1〜PGn。此外， *、、、八器hi、時脈U虎及一極性信號，其用來給充電時間調整裝 置⑽所輸出的貧料當參考電遷。充電時間調整裝置8〇包含一預 存單7G 800、-資料處理單元81〇、一時序控制器㈣及一輸出單 兀㈣。預存單70 800用來儲存-影像資料SDATA，其可為—列 =不貝料。資料處理單元81〇用來將該影像資料SDATA分成影像 i ##iaSGDATAl〜SGDATAn4_、；i?H|^_PG】〜l>Gii。 200907907 t序控制$ 82〇用來根據時序控制信號sci〜心，調整一水平 2時間ΗΊ1，其包含—前廊時間FpT卜—資料顯示時間如 後廊時間ΒΡΉ。輸丨單元㈣用來於資料顯科間而期 間’依序輪出影像資料群組SGDATA1〜SGDATAn至像素群組 PG1〜PGn。較佳地’根據時序控制信號奶〜心，時序控制器 820可先增加時脈信號的頻率，以縮短資料顯示時間如，進而縮 短輸出單元830輸出影像資料群組SGDAmi〜SGDATAn的時 間。此外，時序控制器820調整資料顯示時間而的一起始點， 亦即控制影像資料群組SGDATA1的輸出時間點，以增加前廊時 間FPT1或後廊時間BPT1的長度。如此一來，本發明實施例能提 供充足的前廊時間FPT1，讓極性信號在輸出單元謂輸出第一組 影像資轉組SGDATA1之前完成轉態。另外，本發明實施例也 能提供足夠的後廊時間BPT1，讓最後一組像素群組概能在掃 描線關閉之前，充電至影像資料群組SGDATAn的電壓準位。因 此’本發明實施例能解決顯示晝面「前Band」及「後Band」的問 題。 凊參考第9圖，第9圖為本發明實施例一顯示器之架構示 意圖。顯示器90係一低溫多晶矽薄膜電晶體液晶顯示器（L〇wThe problem of Band. Long time silly. Referring to Figure 8, Figure 8 is a schematic diagram of an electrical time adjustment | 8G for a display according to an embodiment of the present invention. The display ^ contains a plurality of scan lines and data lines, which are arranged in a matrix to indicate pixel arrangement, and __ shows the way aine-by_Line) to display the various faces. Among them, the pixels of each column are divided into pixel groups PG1 PG PGn. In addition, *, ,, eight devices hi, clock U tiger and a polarity signal are used to refer to the electromigration of the lean material outputted by the charging time adjusting device (10). The charging time adjustment device 8A includes a memory list 7G 800, a data processing unit 81, a timing controller (4), and an output unit (4). The pre-storage sheet 70 800 is used to store the image data SDATA, which can be - column = no material. The data processing unit 81 is configured to divide the image data SDATA into images i ##iaSGDATA1~SGDATAn4_,; i?H|^_PG]~l>Gii. 200907907 The t-order control $82〇 is used to adjust a level 2 time 根据1 according to the timing control signal sci~heart, which includes - front porch time FpT - data display time such as vestibule time ΒΡΉ. The input unit (4) is used to sequentially rotate the image data groups SGDATA1 to SGDATAn to the pixel groups PG1 to PGn during the data display period. Preferably, the timing controller 820 can increase the frequency of the clock signal according to the timing control signal to shorten the data display time, for example, thereby shortening the output timing of the output image unit SGDAmi~SGDATAn by the output unit 830. In addition, the timing controller 820 adjusts a starting point of the data display time, that is, controls the output time point of the image data group SGDATA1 to increase the length of the front gallery time FPT1 or the porch time BPT1. In this way, the embodiment of the present invention can provide sufficient front shelf time FPT1 to complete the transition state before the output unit outputs the first group of image transfer groups SGDATA1. In addition, the embodiment of the present invention can also provide sufficient backcourt time BPT1 so that the last group of pixels can be charged to the voltage level of the image data group SGDATAn before the scan line is turned off. Therefore, the embodiment of the present invention can solve the problem of displaying "frontband" and "postband". Referring to Figure 9, Figure 9 is a schematic illustration of the architecture of a display in accordance with an embodiment of the present invention. Display 90 is a low temperature polycrystalline germanium thin film transistor liquid crystal display (L〇w
Temperature Poly-Silicon TFT-LCD，LTPS TFT-LCD )，且包含一充 電時間調整裝置900、一面板92、一源極驅動器94及多工切換器 MUX_SW1〜MUX—SW20。面板92上的裝置及架構與第1圖之面 板12相同’因此不再贅述。充電時間調整裝置9〇〇每次可輸出％ 12 200907907 通道的影像資料，並依序透過多工切換器贿―剛〜 MUX_SW2G，完成-條掃描、_影輸備出。請參考第 第1〇圖為充電時間調整裝置㈣之架構示意圖。在充電時^ 裝置9〇0中，一輸入輸出單元搬利用資料輸入信號_叩 、Dm一G[7 ·· 0]及臟—B[7 : 〇]從外部接收影像資料後— 衝器904預先儲存影像資料。#影像資料經過數位運算（如野比 度或伽碼值調整）之後’―輸出緩衝器_透過一資料輸出 D〇UT[24:輸出24個通道的影像資料至面板92。而為了解決^ B-」及「後Band」的問題，在影像資料輸出之前，時序控制= 906根據-時序控制錢CKH—_，縮短一時脈訊號c咖的 時脈週期，以縮短時脈SR1〜S謂的總時間長度，並另根據—時 序控制信號STH—offset，調整時脈如的起始時間，也就是調整 輸出緩衝器908的起始輸出時間。 明接著參考第11圖’第Η圖為第9圖之顯示器，中相關传 號波形之示意圖。_信號由上至下為—水平同步信號脚加、二 資料輸入錢DIN、-掃描控制錢ENBV、—起始控制信號 STH、-時脈信號CKH2及一極性信號vc〇M。水平同步信號 Hsync的兩健態之_時間定義為—水平錢咖ht2，其盘 第2圖之水平信號時間HT1長度相同。資料輸入信號丽對應於 資料輸入信號 DIN一R[7 : 〇]、DIN_Gp : 〇]及 DINJB[7 : 〇]，而資 料輸入區間表示輸入輸出單元9G2用來接收外部資料的時間。掃 描控制健ENBV时控娜猶的關，其錢高絲示某掃 13 200907907 描線處於開啟狀態。起始和 .及面㈣，彻行影^：Γ咖輸緩衝器908 液晶電容_電壓。輸出。極性職V⑽為面板上 存器908透過一多工切換R1〜SR2G之每一辦脈’輸出暫 _時脈輸出20組影像^ ^由第U圖可知，為了配合於 週期，縮短每條掃描線二號⑽2的時脈 時間ΒΡΤ2及前廊時間Fp 則日，S除此之外，後廊 時間卿來的長。如此一來:第2圖之後廊時間BPT1及前廊Temperature Poly-Silicon TFT-LCD, LTPS TFT-LCD), and includes a charging time adjustment device 900, a panel 92, a source driver 94, and multiplexers MUX_SW1 to MUX-SW20. The device and structure on the panel 92 are the same as those of the panel 12 of Fig. 1 and therefore will not be described again. The charging time adjustment device 9 can output the image data of the channel of % 12 200907907 at a time, and sequentially through the multiplexer to bribe - just ~ MUX_SW2G, complete - strip scanning, _ shadow output. Please refer to the first diagram for the structure of the charging time adjustment device (4). In the charging device ^ device 9〇0, an input/output unit uses the data input signals _叩, Dm_G[7··0] and dirty-B[7: 〇] to receive image data from the outside - the buffer 904 Store image data in advance. #Image data after digital operation (such as wild scale or gamma value adjustment) ‘“Output buffer _ through a data output D〇UT[24: Output 24 channels of image data to panel 92. In order to solve the problem of ^B-" and "post-Band", before the output of the image data, the timing control = 906 according to the - timing control money CKH__, shortening the clock period of a clock signal c coffee to shorten the clock SR1 The total length of time is ~S, and according to the timing control signal STH_offset, the start time of the clock is adjusted, that is, the initial output time of the output buffer 908 is adjusted. Referring to Figure 11, the figure is the display of Figure 9, the schematic diagram of the relevant signal waveforms. The _ signal is from top to bottom - horizontal sync signal pin, two data input money DIN, - scan control money ENBV, - start control signal STH, - clock signal CKH2 and one polarity signal vc 〇 M. The horizontal synchronization signal Hsync has the same _ time as the horizontal money ht2, and the horizontal signal time HT1 of the second picture is the same length. The data input signal corresponds to the data input signals DIN_R[7: 〇], DIN_Gp: 〇], and DINJB[7: 〇], and the data input interval indicates the time at which the input/output unit 9G2 receives external data. When scanning the control ENBV, the control is still closed. The money is high and the wire shows a sweep. 2009 2009907 The line is open. Start and . and face (four), the full shadow ^: Γ coffee transmission buffer 908 liquid crystal capacitor _ voltage. Output. The polarity job V (10) is the panel memory 908 through a multiplex switch R1 ~ SR2G each pulse 'output temporary _ clock output 20 groups of images ^ ^ from the U map, in order to match the cycle, shorten each scan line On the second (10) 2 clock time ΒΡΤ 2 and front porch time Fp on the day, S in addition to the vestibule time from the long. So: Figure 2, the back time BPT1 and front porch
足夠時間於時脈SR1之前1轉If間BPT2提供極性信號VC〇M 時脈如的液晶電容有H 前廊時間附2提供對應於 履曰曰電4足_間充電至預期的電壓準位。 題，而少批、戟放應過大時，顯示晝面會出現「前Band」問 電*騎境下電子移動率過慢，使掃描線後端液晶電容充 顯不晝面出現「後Band」問題。本發明利用辦 二出於極性信號完成轉態之後，並·增長前 位因/ 端液晶電容有足夠的時間充電至預期電鲜 題因此，本發明可有效地解決顯示畫面「前細d」及「後Band」 以上所述僅為本發明之較佳實施例，凡 圍所做之解·與修飾1闕本㈣之涵蓋細她 14 200907907 【圖式簡單說明】 第1圖為習知一顯示器之示意圖。 第2圖為根據第1 ®之顯示器之相關信號波形圖。 第3圖為根據第1 ®之顯示ϋ在「前Band」的現象下相 形之示意目。 域波 第4圖為根據第1圖之顯示器之—面板上之相關充電電容之厂、土 圖。 不思 第5圖為根據第1圖之顯示器在「後Band」的現象下相關信 形之示意圖。 。纪波 第6圖為根據第1圖之顯示器在同時出現「前Band」及「後 現象的顯不晝面之示意圖。 第7圖為本發明實施例一充電時間調整流程之示意圖。 第8圖為本發明實施例用於一顯示器之一充電時間調整裝置之示 意圖。 第9圖為本發明實施例用於一顯示器之一充電時間調整裝置之示 意圖。 第10圖為根據第9圖之充電時間調整裝置之架構示意圖。 第U圖為根據第9圖之顯示器之相關信號波形之示意圖。 【主要元件符號說明】 10、90 顯示器 12 > 92 面板 100 時序控制器 15 200907907 110 源極驅動器 120、94 閘極驅動器 ENBV 掃描控制信號 STH 起始控制信號 CKH1 ' CKH2 時脈信號 VCOM 極性信號 Hsync 水平同步信號 HT1 ' HT2 水平信號時間 FPT 前廊時間 DT 資料顯示時間 BPT 後廊時間 DIN 資料輸入信號 sm、SR2、SR19、SR20 時脈 Gate 閘極信號 HSR1 ' HSR2 ' HSR20 多工切換信號 VData 輸出資料電壓 80、900 充電時間調整裝置 800 預存單元 810 資料處理單元 820、906 時序控制器 830 輸出單元 SDATA 影像資料 PG1 ' PG2 ' PGn-1 > PGn 像素群組 16 200907907 902 904 908 70 輪入輪出單元 線緩衝器 輪出緩衝器 充電時間調整流程 MUX—SW1、MUX一SW2、MUX—SW19、MUX SW20 多工 電容 液晶電容 步驟 時序控制信號 CDatal、Cdata24、Cdata479、CData480 CLC1 ' CLC24 > CLC479 > CLC480 700、702、704、706、708、710 SCI 〜SCm、CKH_Width、STH_offset SGDATA卜 SGDATA2、SGDATAn-1、SGDATAn 影像資料群組 Channel 1、Channel 24、Channel25、Channel48、Channel433、Sufficient time before the clock SR1 1 turn If the BPT2 provides the polarity signal VC〇M clock pulse such as the liquid crystal capacitor has H front porch time attached 2 provides corresponding to the voltage of the 曰曰 曰曰 electric battery to the expected voltage level. The problem is that when the batch is too small and the release should be too large, the "front band" will appear when the display is displayed. * The electronic movement rate is too slow under the riding environment, so that the rear-end LCD capacitor of the scanning line appears to be "back". problem. After the invention completes the transition state by the polarity signal, and the pre-growth source/end liquid crystal capacitor has sufficient time to charge to the expected electro-optical problem, the present invention can effectively solve the display picture "front fine d" and "Post Band" The above description is only a preferred embodiment of the present invention, and the solution and modification of the surrounding one (4) is covered by her 14 200907907 [Simplified Schematic] FIG. 1 is a conventional display Schematic diagram. Figure 2 is a diagram of the relevant signal waveforms of the display according to the 1st. Fig. 3 is a schematic diagram showing the shape of the "front band" phenomenon according to the display of the 1st. Domain Wave Figure 4 shows the plant and soil map of the relevant charging capacitor on the panel according to the display in Figure 1. No. Figure 5 is a schematic diagram of the relevant signal of the display according to Fig. 1 under the phenomenon of "post Band". . Fig. 6 is a schematic diagram showing the appearance of "front band" and "post phenomenon" in the display according to Fig. 1. Fig. 7 is a schematic view showing a charging time adjustment process according to an embodiment of the present invention. A schematic diagram of a charging time adjusting device for a display according to an embodiment of the present invention. FIG. 9 is a schematic diagram of a charging time adjusting device for a display according to an embodiment of the present invention. FIG. 10 is a charging time according to FIG. Schematic diagram of the adjustment device. Figure U is a schematic diagram of the relevant signal waveform of the display according to Figure 9. [Main component symbol description] 10, 90 display 12 > 92 panel 100 timing controller 15 200907907 110 source driver 120, 94 Gate driver ENBV Scan control signal STH Start control signal CKH1 ' CKH2 Clock signal VCOM Polarity signal Hsync Horizontal sync signal HT1 ' HT2 Horizontal signal time FPT Front corridor time DT Data display time BPT Backyard time DIN data input signal sm, SR2, SR19, SR20 Clock Gate Gate Signal HSR1 ' HSR2 ' HSR20 Multiplex Switch Signal VData Output data voltage 80, 900 Charging time adjustment device 800 Pre-stored unit 810 Data processing unit 820, 906 Timing controller 830 Output unit SDATA Image data PG1 'PG2' PGn-1 > PGn pixel group 16 200907907 902 904 908 70 Wheeling Round-out unit line buffer wheel-out buffer charging time adjustment process MUX-SW1, MUX-SW2, MUX-SW19, MUX SW20 multiplex capacitor liquid crystal capacitor step timing control signals CDatal, Cdata24, Cdata479, CData480 CLC1 'CLC24 > CLC479 > CLC480 700, 702, 704, 706, 708, 710 SCI ~ SCm, CKH_Width, STH_offset SGDATA Bu SGDATA2, SGDATAn-1, SGDATAn Image data group Channel 1, Channel 24, Channel25, Channel48, Channel433,
Channel456、Channel457、Channel480 通道 DOUT[24 ： 1] > DIN_R[7 ： 0] ' DIN_G[7 ： 0] ' DIN_B[7 ： 0] 資料輸出信號 17Channel456, Channel457, Channel480 channel DOUT[24 : 1] > DIN_R[7 : 0] ' DIN_G[7 : 0] ' DIN_B[7 : 0] Data output signal 17