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TW200703507A - Semiconductor structures and methods for formign the same - Google Patents

Semiconductor structures and methods for formign the same

Info

Publication number
TW200703507A
TW200703507A TW095102449A TW95102449A TW200703507A TW 200703507 A TW200703507 A TW 200703507A TW 095102449 A TW095102449 A TW 095102449A TW 95102449 A TW95102449 A TW 95102449A TW 200703507 A TW200703507 A TW 200703507A
Authority
TW
Taiwan
Prior art keywords
gate structure
nitrogen
formign
methods
same
Prior art date
Application number
TW095102449A
Other languages
English (en)
Other versions
TWI271802B (en
Inventor
Jhon-Jhy Liaw
Tze-Liang Lee
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200703507A publication Critical patent/TW200703507A/zh
Application granted granted Critical
Publication of TWI271802B publication Critical patent/TWI271802B/zh

Links

Classifications

    • H10W20/098—
    • H10W20/077—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW095102449A 2005-07-13 2006-01-23 Semiconductor structures and methods for forming the same TWI271802B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/180,935 US20070013012A1 (en) 2005-07-13 2005-07-13 Etch-stop layer structure

Publications (2)

Publication Number Publication Date
TW200703507A true TW200703507A (en) 2007-01-16
TWI271802B TWI271802B (en) 2007-01-21

Family

ID=37609729

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095102449A TWI271802B (en) 2005-07-13 2006-01-23 Semiconductor structures and methods for forming the same

Country Status (3)

Country Link
US (1) US20070013012A1 (zh)
CN (1) CN1897280A (zh)
TW (1) TWI271802B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070202688A1 (en) * 2006-02-24 2007-08-30 Pei-Yu Chou Method for forming contact opening
US20090065841A1 (en) * 2007-09-06 2009-03-12 Assaf Shappir SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS
US20130320411A1 (en) * 2012-06-05 2013-12-05 International Business Machines Corporation Borderless contacts for metal gates through selective cap deposition
CN103872094A (zh) * 2012-12-11 2014-06-18 旺宏电子股份有限公司 半导体装置及其形成方法

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JPH0950986A (ja) * 1995-05-29 1997-02-18 Sony Corp 接続孔の形成方法
JPH10284438A (ja) * 1997-04-02 1998-10-23 Toshiba Corp 半導体集積回路及びその製造方法
KR100268443B1 (ko) * 1998-08-29 2000-10-16 윤종용 반도체 장치의 자기 정렬 콘택 형성 방법
KR100281692B1 (ko) * 1998-10-17 2001-03-02 윤종용 반도체 장치의 자기정렬 콘택 패드 및 그 형성 방법
KR100307287B1 (ko) * 1998-11-20 2001-12-05 윤종용 반도체장치의패드제조방법
US6258648B1 (en) * 1999-02-08 2001-07-10 Chartered Semiconductor Manufacturing Ltd. Selective salicide process by reformation of silicon nitride sidewall spacers
US6420250B1 (en) * 2000-03-03 2002-07-16 Micron Technology, Inc. Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
US6649517B2 (en) * 2001-05-18 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Copper metal structure for the reduction of intra-metal capacitance
KR100434495B1 (ko) * 2001-11-10 2004-06-05 삼성전자주식회사 반도체 소자의 제조방법
KR100443082B1 (ko) * 2002-10-18 2004-08-04 삼성전자주식회사 반도체 장치의 트랜지스터 제조 방법
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6969646B2 (en) * 2003-02-10 2005-11-29 Chartered Semiconductor Manufacturing Ltd. Method of activating polysilicon gate structure dopants after offset spacer deposition
KR100500451B1 (ko) * 2003-06-16 2005-07-12 삼성전자주식회사 인장된 채널을 갖는 모스 트랜지스터를 구비하는반도체소자의 제조 방법
US7473929B2 (en) * 2003-07-02 2009-01-06 Panasonic Corporation Semiconductor device and method for fabricating the same
US6905922B2 (en) * 2003-10-03 2005-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dual fully-silicided gate MOSFETs
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
JP2005203619A (ja) * 2004-01-16 2005-07-28 Sharp Corp 層間絶縁膜の形成方法
KR100526059B1 (ko) * 2004-02-19 2005-11-08 삼성전자주식회사 반도체 소자 제조 공정에서의 자기-정렬 컨택 형성 방법
JP2005286341A (ja) * 2004-03-30 2005-10-13 Samsung Electronics Co Ltd 低ノイズ及び高性能のｌｓｉ素子、レイアウト及びその製造方法
JP4469651B2 (ja) * 2004-04-23 2010-05-26 株式会社東芝 不揮発性半導体記憶装置
US7190047B2 (en) * 2004-06-03 2007-03-13 Lucent Technologies Inc. Transistors and methods for making the same
US20060024879A1 (en) * 2004-07-31 2006-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Selectively strained MOSFETs to improve drive current
DE102004052577B4 (de) * 2004-10-29 2010-08-12 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer dielektrischen Ätzstoppschicht über einer Struktur, die Leitungen mit kleinem Abstand enthält
JP2006202928A (ja) * 2005-01-19 2006-08-03 Nec Electronics Corp 半導体装置の製造方法
US7265009B2 (en) * 2005-02-24 2007-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. HDP-CVD methodology for forming PMD layer
US20060292775A1 (en) * 2005-06-28 2006-12-28 Nanya Technology Corporation Method of manufacturing DRAM capable of avoiding bit line leakage

Also Published As

Publication number Publication date
TWI271802B (en) 2007-01-21
CN1897280A (zh) 2007-01-17
US20070013012A1 (en) 2007-01-18

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