TW200532812A - Semiconductor molding structure and method thereof - Google Patents

Abstract

A semiconductor package and method thereof are proposed, wherein a chip carrier including a plurality of semiconductor chips arrayed thereon and an encapsulant formed thereon for covering the semiconductor chips is provided. A plurality of package units is respectively defined by the encapsulant covering the semiconductor chips, and at least a pair of adjacent package units is connected by at least a connected portion made by the encapsulant, thereby preventing the semiconductor molding structure from warpage and deformation.

Description

200532812 丨 V. Description of the invention α) i [Technical field to which the invention belongs] I The present invention relates to a semiconductor molding method and a molding structure thereof, in particular, it refers to a semiconductor molding method and a molding method capable of reducing lightness and deformation of a semiconductor device. structure. [Previous technology] Ball grid array semiconductor packaging technology is an advanced semiconductor packaging technology. As shown in Figure 5, the substrate 5 1 is used as the carrier of the semiconductor wafer 5 2 and is laid on both the upper and lower surfaces. The conductive trace layer 54 is used to electrically connect the chip 5 2 to the conductive trace layer 54 on the upper surface with a bonding wire 5 3 so as to transmit the electrical signal by the solder ball 5 6 implanted on the lower surface thereof. To the outside, and protect the package by an encapsulant 5 5 formed on the upper surface thereof and covering the chip 5 2 and the bonding wire 5 3. This ball grid array package 50 takes into account the cost considerations and production requirements of the manufacturing method, and is generally produced in batch mode (Batch T ype), that is, a whole substrate strip (S ubstrate S On the trip), a plurality of grid-interleaved i-package boundary lines are used to predefine a plurality of packaging units arranged in a matrix, and after applying steps such as die bonding, welding bond, and colloidal packaging, they are applied. Singulation (S ingu 1 ATI) removes the connection between adjacent packaging units to form a single semiconductor package 50 as shown in FIG. 5. Conventionally, in order to improve the process efficiency and reduce the time and cost of colloidal packaging, such as the thin ball grid array (Thin Fine Ball Grid Array, TFBGA) semiconductor disclosed in US Patent No. 5,7 7 6, 7 98 As shown in FIG. 6, a method for molding a package is to form a plurality of array-type predetermined packaging areas on the substrate 100 (such as component symbols 1 0 1, 1 0 2, 1 0 3, 1 0 4,

B11IS

17437 联 测 .ptd Page 5 200532812 丨 V. Description of the invention (2) j | 1 0 5, 1 6 6) 'Each of this packaging area is surrounded by a surrounding gap; [q 7 each other | S | i separated . Wherein, the substrate 100 is packaged in the form of a substrate strip, and a dam structure 108 (D ambar) is formed around the substrate 100 so that the predetermined packaging areas are located in the substrate 100. Dam structure within 108. Then, an array-type packaging area within the dam structure 1 § is covered with a packaging gel 10 9 such as resin (E ρ ο X y), and a plurality of packaging areas on the substrate 100 are packaged after the molding operation. Among them, because the dam structure 108 surrounds the entire encapsulation area, the encapsulation gel 107 covering it can form a flat surface. Finally, after post molding curing (PMC) to complete the resin bonding, the packaging gel 1 009 and the substrate 1 〇 below are cut at the gap of the packaging area of the obtained package to be divided. For each package area, an individual semiconductor package as shown in FIG. 5 is obtained. However, the predetermined packaging area of this conventional method is arranged in an array. After packaging the entire packaging area, the packaging gel 10 has a large area, generally 42.5 mm X 42.5 mm. After the PMC process, which is easy to handle at high temperature, The thermal expansion coefficient of the package gel 1 〇9 does not match the thermal expansion coefficient of the substrate 100 (c but e Mismatch), and the thickness of the thin ball grid array substrate 100 is thinner, and the package gel i 〇9 The contact with the substrate i 〇 5 is extremely large, causing the package to produce the Warpage phenomenon as shown in Figure 7, which causes a major problem in process yield and structural strength. Furthermore, due to its poor flatness, it is difficult to cut or damage the cutting tool. Therefore, as shown in U.S. Patent No. 5,8,9,7,3,4, a plurality of packaging lines 6 3 are constructed on the substrate strip 6 1 shown in FIG. 8.

200532812 丨 V. Description of the invention (3) i (Package Line) divided and adjacent square substrate units 62,

17437 Joint Test. Ptd Page 7 200532812 i. Description of the Invention (4) The urgent problem in the field of & i [Contents of the Invention] The main object of the present invention is to provide a method for preventing thermal expansion coefficient.

17437 联 测 .ptd Page 8 200532812 丨 V. Description of the invention (5) I shape, and its height is lower than the height of the packaging unit; At the same time, each group of I adjacent two packaging units are formed The connection portion is not formed at the packaging unit space between the groups, or the design I may be changed so that the connection portion is formed between all adjacent packaging units. Therefore, by the aforementioned connection portion design, an appropriate binding force can be maintained between the packaging units on the wafer carrier I, and the semiconductor molding method and the molding structure proposed by the present invention I can be made. Give play to the effect of stabilizing the overall structure I, which will not cause warpage and breakage due to the mismatch of the thermal expansion coefficient of the material, nor will it cause the structure to bend and deform due to the effect of gravity, which fully improves the structural strength and process yield, and solves the conventional technology The dilemma encountered. [Embodiment] The following is a description of the embodiment of the present invention by means of a specific embodiment! The person skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. _ Figures 1A and 1B show preferred embodiments of the semiconductor molding method and the molding structure of the present invention. First, as shown in Figure 1A, a wafer carrier 20 is provided. The wafer carrier 20 can Is, for example, a thin ball grid array substrate, and

I A plurality of grid-shaped staggered predetermined cutting lines are formed on the surface thereof, and a plurality of semiconductor wafers 2 1 arranged in a matrix are defined by the predetermined cutting lines and a final cutting line, wherein the semiconductor wafer 2 1 With welding wire 2 2 and

17437 联 测 .ptd Page 9 200532812 V. Description of the invention (6) ^ ---- 讧 Wafer ▲ The conductive traces on the carrier 20 are electrically connected; then, the pressing process of the present invention is performed, which is shown in the figure Shown is a special upper and lower mold bean 2 3, 丨 Γΐίί ^ ^ bearing 2 ° 'so that each wafer 21 and its bonding wire; 2 containing = the corresponding cavity 25 of the tool 23 The two adjacent mold cavities 25 are equipped with f, so that the two mold cavities 25 in the same group form a connection with a height lower than that of the mold cavity 25 to connect 3 0, so that the encapsulation gel 2 6 self-injection port (not shown) Note: After inserting the cavity 25, the encapsulating gel 26 can also be filled in the two connection channels 30 between two adjacent cavities. Then, when the body 26 is installed, the semiconductor device 40, a group, Adjacent two wafers on the upper mold are composed of Cheng Chun, Lien 3 0 Design 3. The soap is made larger by the force of f, and the force is pressed by force, and the same connection portion 2 3 is connected to the carrier 21 of the wafer 21 The connection portion 31 can be connected to adjacent wafers at the same time, so that the wafer can be forced into the wafer, and the cavity 2 5 and the connection channel 3 0 are filled in. Fill the seal and perform the demolding step, as shown in Figure 1 jg. At this time, you can see that two adjacent packaging units 41 are configured as two packaging units 4 1 and 2 are made of packaging gel 2 6 3 1 are connected to each other, and the connecting portion 31 is the encapsulating gel 2 6 corresponding to the position of the aforementioned channel 30, so that the encapsulating gel 2 6 is integrally formed by the connecting portion 31, as shown in FIG. As shown in the upper view of Fig. 2, the design shape can be seen more clearly. It is a colloidal connecting part that is long and spaced apart from each other by the connecting channel of the cavity 25. The encapsulating colloid 2 of the two packaging units 41. In the central position, the contact area between the component 20 and all the encapsulants 2 and 6 cannot be used to open the two adjacent packaging units 41 by the connecting portion 31, and the packaging units 2 at both ends of the packaging unit 41. Do not cause bending deformation due to its heavy load bearing member 20. As described above, the connecting channel 3 (h and

17437 United Test. Ptd Page 10 200532812 V. Description of the invention (7) Design, can form two long connecting parts 3 1 between two adjacent packaging units 4 1 after molding, at this time because of the long connecting part 3 The contact area between 1 and the wafer carrier 20 is not large, so it will not cause the packaging gel 26 to produce excessive restraints when thermally expanded, and the thermal expansion stress can be released by the two sides of the connection portion 31. Warping does not occur due to mismatch in thermal expansion between the packaging colloid 26 and the wafer carrier 20; at the same time, since the connection portion 31 is used to connect two adjacent packaging units 41, it can still be used. It exerts moderate restraint on the packaging unit 41 on both sides to counteract the gravity effect of the packaging unit 41, so that it will not cause bending and deformation due to gravity. It solves two conventional problems in one fell swoop. Its structural design controls the restraint 1 I force between the packaging units 41 to an ideal value to exert the effect of stabilizing the overall molding structure. The previously-molded semiconductor device 40 can be used as a conventional manufacturing process. After performing the steps of ball implantation, cutting, and testing at i, it becomes a thin ball grid array i-row semiconductor package. These steps are familiar The manufacturing process is the same, and I will not repeat it here. In addition, in the foregoing molding process, the wafer 21 is covered and formed.

The packaging gel 2 6 of the connecting portion 31 designed in the present invention is, for example, a thermosetting resin such as epoxy resin (EpoXyResi η) or polycarbonate (Polycarbonate Ester), Thermoplastic resin of acrylic acid resin, polychloromethane and polyester resin (Polyester resin), but the material is not limited to this. The semiconductor molding method and the molding structure disclosed in the present invention are not limited to the foregoing embodiments, but as shown in FIG. 3A, the design of the connection channel 3 0 of the upper mold 2 3 I can be changed so that each corresponds to Adjacent mold cavities 2 5 1 of wafer 21 are each formed with a connecting channel 30, and the cavity 2 5 and the connecting channel 30 are both

200532812 V. Description of the invention (8) The encapsulation gel 2 6 is filled during the pressing process, and after the demolding step as shown in FIG. 3B, all the packaging units 41 are connected to each other and the encapsulation gel 2 is formed. 6 connecting portions 31, so the encapsulant 2 6 on the wafer carrier 20 will be integrally formed to cover each wafer 21, and since the connecting portion 3 1 is as shown in the top view of FIG. 4 Shown are two long strips of packaging gel 26 which are spaced apart from each other, so that the integrally formed packaging gel 26 will not contact the wafer carrier 20 with an excessively large area, but can be made as in the previous embodiment. Each of the packaging units 41 maintains a proper restraint force to prevent the mismatch of the expansion coefficient of the molded structure and the warping deformation caused by gravity, and exerts the effect of stabilization. In summary, the semiconductor molding method and the molding structure proposed by the present invention can indeed play a role in stabilizing the overall structure by the design of the connection portion, which will not cause warpage damage due to the mismatch of the thermal expansion coefficients of the materials, nor will it cause damage. The bending deformation of the structure due to the effect of gravity fully improves the strength of the structure and the yield of the process, and solves the problems encountered in the conventional technology. The above are only used to explain specific examples of the present invention, and are not intended to limit the implementable scope of the present invention. For example, those who are familiar with the technology can do all without departing from the spirit and technical ideas disclosed by the present invention. The zither decoration or alteration shall still be covered by the patent application scope mentioned later.

17437 联 测 .ptd Page 12 200532812 丨 Simple illustration i [Simplified illustration]

17437 Joint test. Ptd Page 13 200532812 Brief description of the drawings 24 Lower mold 25 Mold 26 Encapsulation gel 30 Connection channel 31 Connection portion 40 Semiconductor device 41 Packaging unit 50 Dome · Array package 51 Substrate 52 Wafer 53 Welding wire 54 Conductive trace Line layer 5 5 Encapsulant 56 Solder ball 61 Substrate strip 62 Substrate unit 6 · Encapsulation line 64 Substrate connection 65 Chip 66 Weld wire 67 Encapsulation unit 68 Encapsulation gel 69 Gap

17437 Joint Test.ptd Page 14

Claims (1)

200532812 I Sixth, the scope of patent application i 1. A semiconductor molding method, which includes the following steps:! Preparing a wafer carrier carrying a plurality of semiconductor wafers, and making the semiconductor wafer and the wafer carrier electrically connected; A molding step for filling a packaging colloid on the wafer carrier and forming a plurality of packaging units respectively covering the semiconductor wafer; at the same time, forming at least one group of two adjacent packaging units to form the packaging colloid At least one connection portion; and I performing a demolding step to form a semiconductor molding structure. 2. According to the semiconductor molding method of the first patent application scope, wherein the connection part is formed by filling the pre-set connection channel in the mold of the molding step with the packaging gel. I 3. The semiconductor molding method according to item 1 of the scope of patent application, wherein two adjacent packaging units are formed with two connecting portions spaced apart from each other by a distance. 4. For the semiconductor molding method according to item 1 of the patent application scope, wherein the shape of the connecting portion is a long shape. 5. The semiconductor molding method according to item 1 of the patent application scope, wherein the height of the connection portion is lower than the height of the packaging unit. 6. For example, the semiconductor molding method of the scope of the patent application, wherein the connection portion is formed between each two adjacent packaging and packaging units, and the connection is not formed between the packaging unit spaces between the groups. unit. 7. The semiconductor molding method according to item 1 of the patent application scope, wherein the connection portion is formed between all adjacent packaging units. 8. The semiconductor die-pressing method according to item 1 of the patent application scope, wherein the wafer I wafer carrier is a thin ball grid array substrate. 17437 联 测 .ptd Page 15 200532812 i Six. Patent application scope I 1¾. For the semiconductor molding method of the first patent application scope, wherein a plurality of grid-like staggered plans are formed on the II wafer carrier The I line is cut to define each package unit by the predetermined cut lines. 10. The semiconductor molding method according to item 1 of the application, wherein the semiconductor wafer is electrically connected to the wafer carrier by a bonding wire. 11. A semiconductor molding structure, comprising: a wafer carrier, a plurality of semiconductor wafers connected to the wafer carrier and electrically connected to the wafer carrier; and a packaging gel filled in the wafer carrier to form a plurality of wafers. The packaging units respectively covering the semiconductor wafer; and at least one connection portion are composed of the packaging gel and are formed between at least one adjacent two packaging units. 1 2. As in the semiconductor mold structure of item 11 in the scope of patent application, wherein adjacent packaging units are formed with two connecting portions spaced apart from each other by a distance ° 1 3. As in semiconductor mold structure in the area of patent application 11 The structure, wherein the shape of the connecting portion is a long shape. ] φ. The semiconductor mold structure of item 11 in the patent application, wherein the height of the connecting portion is lower than the height of the packaging unit. 1 5. According to the semiconductor molded structure of item 11 in the scope of patent application, wherein the connection portion is formed between two adjacent packaging units of each group, and the connection is not formed at the packaging unit interval between each group. unit. 16. The semiconductor molded structure according to item 11 of the patent application scope, wherein 17437 联 测 .ptd Page 16 200532812 I Sixth, the scope of patent application: The connection is formed between adjacent packaging units. : 1 7. The semiconductor mold structure according to item 11 of the patent application scope, wherein the i-chip carrier is a thin ball grid array substrate. l8. According to the semiconductor mold structure of the scope of application for patent No. 11, wherein, on the wafer carrier, there are formed a plurality of grid-like staggered predetermined cutting lines! Each of the predetermined cutting lines is defined by these predetermined cutting lines. A packaging unit. Il9. The semiconductor molded structure according to item 11 of the application, wherein the j semiconductor wafer is electrically connected to the wafer carrier with a bonding wire. 17437 Joint Test.ptd Page 17