KR20120017832A - Semiconductor storage device and method of controlling performance of semiconductor storage device - Google Patents

Abstract

Disclosed are a semiconductor storage device and a method of controlling performance of the semiconductor storage device. A performance control method of a semiconductor storage device including a nonvolatile memory device and a controller for controlling the nonvolatile memory device, the method comprising: operating the semiconductor storage device according to a first performance level; Calculating a new performance level; Comparing the calculated performance level with a predetermined criterion; Determining the calculated performance level as a second performance level according to the comparison result; Operating the semiconductor storage device according to the second performance level.

Description

Semiconductor storage device and method for throttling performance of the semiconductor storage device

The present invention relates to a data storage device, and more particularly, to a semiconductor storage device for storing data in a nonvolatile memory and a method of adjusting the performance thereof.

A semiconductor storage device is a device that stores data using a semiconductor (particularly, a nonvolatile memory). The semiconductor storage device is faster than a disk storage medium (ie, a hard disk drive), which has been widely used as a mass storage device, and is resistant to physical shocks. Less heat and noise, there is an advantage that can be miniaturized. One example of a semiconductor storage device is a solid state drive (SSD).

Meanwhile, the semiconductor storage device may have a limited service life. For example, NAND flash memory is typical. In NAND flash memory, memory devices are divided into blocks, and a plurality of pages exist in one block. The user utilizes NAND flash memory by first erasing the block and then sequentially programming the pages within the block with specific data. In order to program a block with all pages programmed with new data, the block must be erased again. This series of processes is called a program-erase cycle (PE-cycle), and in NAND flash memory, there is a limit to the number of PE-cycles a block can withstand. This is called the endurance of NAND flash memory.

If the number of PE-cycles experienced by a block exceeds the endurance limit, the block is more likely to malfunction later. In addition to the above-described program and erase operations, a memory malfunction may include a read operation and a natural charge loss. When the probability of malfunction increases, it should not be used anymore for the data integrity of the semiconductor storage device. For this reason, semiconductor storage devices employing NAND flash memories have a limited lifetime.

In the above example, when an excessive workload (eg, a write operation, an erase operation, a read operation, etc.) is applied to the semiconductor storage device, the life of the semiconductor storage device may be shortened or the expected life may not be guaranteed. Therefore, in order to ensure the expected life of the semiconductor storage device, the processing capacity of the semiconductor storage device needs to be adjusted according to the intensity or amount of the workload applied to the semiconductor storage device.

This can be found in solid state drives (SSDs) consisting of multi-level cell (MLC) NAND flash memory targeted at recent server applications. Server-side storage not only requires high performance, ie high I / O per second, but also varies greatly in the amount of workload applied to the storage. The application of MLC NAND flash memory with limited endurance limitations in these applications makes it difficult to guarantee the lifetime of SSDs.

However, the storage device for guaranteeing the lifespan is not limited to the server-side storage device described above, and the lifespan of the storage device to be applied to a personal computer (PC), a notebook computer, a mobile device, and the like also needs to be guaranteed.

Examples of memory with an endurance limit include, in addition to the above-described NAND flash memory, PRAM (Phase-change Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistive RAM), and FeRAM (Ferroelectric RAM). ) And the like. In addition, NAND flash memory with an endurance limit includes NAND flash memory using a floating gate and NAND flash memory of a charge trapping flash (CTF) method.

As such, there is a need for a method for extending the life of a semiconductor storage device using a nonvolatile memory having an endurance limit or for ensuring an expected life.

Accordingly, the technical problem to be achieved by the present invention is to provide a semiconductor storage device and a method of adjusting the performance of the semiconductor storage device that can adaptively adjust the performance according to the workload to ensure the required life.

According to another aspect of the present invention, there is provided a method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller controlling the nonvolatile memory device. Operating according to the level; Calculating a new performance level; Comparing the calculated performance level with a predetermined criterion; Determining the calculated performance level as a second performance level according to the comparison result; Operating the semiconductor storage device according to the second performance level.

As described above, according to the present invention, the performance may be adaptively adjusted according to the workload of the semiconductor storage device. Accordingly, there is an effect of extending the life of the semiconductor storage device or ensuring the required life.

1 is a schematic block diagram of a data storage system according to an embodiment of the present invention.
2 is a schematic block diagram of a controller according to an embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating a structure of the nonvolatile memory device shown in FIG. 2.
4 is a schematic block diagram of a host according to an embodiment of the present invention.
5A is a flowchart illustrating a method of controlling performance of a semiconductor storage device according to an embodiment of the present invention.
5B is a flowchart illustrating a method of controlling performance of a semiconductor storage device according to an embodiment of the present invention.
5C is a flowchart illustrating a performance adjusting method of a semiconductor storage device according to another exemplary embodiment of the present invention.
FIG. 6 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device illustrated in FIG. 5B.
7 is a flowchart illustrating a performance adjusting method of a semiconductor storage device according to another exemplary embodiment of the present invention.
FIG. 8 is a graph illustrating a change in performance level according to the performance adjusting method of the semiconductor storage device illustrated in FIG. 7.
9 is a flowchart illustrating a method of controlling performance of a semiconductor storage device according to another exemplary embodiment of the present invention.
FIG. 10 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device illustrated in FIG. 9.
11 is a flowchart illustrating a method of controlling performance of a semiconductor storage device according to still another embodiment of the present invention.
FIG. 12A is a graph illustrating a change in performance level according to the performance adjusting method of the semiconductor storage device illustrated in FIG. 11.
12B is a graph for explaining a method of selecting a discrete level according to the calculated performance level.
13 is a table illustrating a format of a host command according to an embodiment of the present invention.
14 is a block diagram of an electronic system including a semiconductor storage device according to an embodiment of the present invention.
15A and 15B are each a block diagram of an electronic system according to another embodiment of the present invention.
16 is a block diagram of a computing system including a semiconductor storage device according to an embodiment of the present invention.

Specific structural to functional descriptions of embodiments according to the inventive concept disclosed in the specification or the application are only illustrated for the purpose of describing embodiments according to the inventive concept, and according to the inventive concept. The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

For example, when one component 'transmits or outputs' data or a signal to another component, the component may 'transmit or output' the data or signal directly to the other component, and at least one This means that the data or signal may be transmitted or output to the other component through another component of.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a schematic block diagram of a data storage system 1 according to an embodiment of the present invention. The data storage system 1 according to an embodiment of the present invention includes a semiconductor storage device 10 and a host 20. The semiconductor storage device 10 may include a controller 100 and a nonvolatile memory device 200.

The host 20 uses a semiconductor protocol such as a peripheral component interconnect-express (PCI-E), Advanced Technology Attachment (ATA), serial ATA (SATA), parallel ATA (PATA), or serial attached SCSI (SAS). Communicate with the storage device 10. However, the interface protocols between the host 20 and the semiconductor storage device 10 are not limited to the examples described above, but may include Universal Serial Bus (USB), multi-media card (MMC), enhanced small disk interface (ESDI), or IDE. It may be one of other interface protocols such as (Integrated Drive Electronics).

The semiconductor storage device 10 according to an embodiment of the present invention may be a solid state drive (hereinafter, referred to as an 'SSD'). In addition, the nonvolatile memory device 200 may be a flash memory device, but is not limited thereto.

The controller 100 controls overall operations of the semiconductor storage device 10 and also controls overall data exchange between the host 20 and the nonvolatile memory device 200. For example, the controller 100 controls the nonvolatile memory device 200 in response to a request of the host 20 to write or read data. In addition, the controller 100 controls a series of internal operations (eg, performance adjustment, merging, wear leveling, etc.) necessary for the characteristics of the nonvolatile memory or the efficient management of the nonvolatile memory.

The nonvolatile memory device 200 is a storage location for nonvolatile storage of data, and stores user data and metadata. The nonvolatile memory device 220 may store an operating system (OS), various programs, and various data.

2 is a schematic block diagram of a controller 100 according to an embodiment of the present invention. 2, the controller 100 includes a host interface 110, a DRAM 120, an SRAM 130, a nonvolatile memory interface 140, a CPU 150, a system bus 160, and a workload module ( 170, a timer 180, a performance adjustment module 190, and a clock generator 195.

The host interface 110 has an interface protocol for communicating with the host 20. DRAM 120 and SRAM 130 each store data and / or programs volatile. The nonvolatile memory interface 140 interfaces with the nonvolatile memory device 200.

The CPU 150 performs various control operations for writing / reading data to / from the nonvolatile memory device 200.

The workload module 170 may collect workload data related to the workload applied to the semiconductor storage device 10 and predict the workload based on the collected workload data.

The performance adjusting module 190 determines the target performance level according to the workload predicted by the workload module 170, and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 180 provides time information to the CPU 150, the workload module 170, and the performance adjustment module 190. The workload module 170 and the performance tuning module 190 may be implemented in hardware, software or a combination of hardware and software.

When the workload module 170 and the performance tuning module 190 are implemented in software, the corresponding program is stored in the nonvolatile memory device 200, and when the semiconductor storage device 10 is powered on, the nonvolatile memory device It may be loaded from S200 into SRAM 130 and executed by CPU 150.

The timer 180 may also be implemented in hardware or software.

The clock generator 195 generates a clock signal necessary for the operation of the CPU 150, the DRAM 120, and the nonvolatile memory device 200, and provides the clock signal to a corresponding component. Speeds of clock signals provided to the CPU 150, the DRAM 120, and the nonvolatile memory device 200 may be different. The clock generator 195 adjusts the speed of the clock signal applied to the CPU 150, the DRAM 120, and the nonvolatile memory device 200 according to the performance level determined by the performance adjusting module 190. The performance of the storage device 10 can be adjusted.

Although not shown in the drawings, the semiconductor storage device 10 may include a ROM (not shown) and a nonvolatile memory device 200 that store code data executed at power-on of the semiconductor storage device 10. A component such as an ECC engine (not shown) for encoding data to be stored in the data and decoding data read from the nonvolatile memory device 200 may be further included.

3 is a diagram schematically illustrating a structure of the nonvolatile memory device 200 shown in FIG. 2. Referring to this, the nonvolatile memory device 200 may include a plurality of memory chips. 3 illustrates a nonvolatile memory device 200 having a hardware structure of a 4-channel / 3-bank scheme, but the present invention is not limited thereto.

In the semiconductor storage device 10 illustrated in FIG. 3, the controller 100 and the nonvolatile memory device 200 are connected to four channels A, B, C, and D, and three flash memories are provided in each channel. Chips CA0 to CA2, CB0 to CB2, CC0 to CC2, and CD0 to CD2 are connected to each other. However, it is obvious that the number of channels and the number of banks can be changed without being limited thereto.

In the semiconductor storage device 10 having such a structure, the performance control unit of the semiconductor storage device 10 is shared by the entire nonvolatile memory device 200 and individual memory devices (memory chips) of the nonvolatile memory device 200. It may be a bus unit, a bank unit, or an individual device unit. Here, a bank is a group of memory devices located at the same offset on different channels.

4 is a schematic block diagram of a host 20 according to an embodiment of the present invention. Referring to FIG. 4, the host 20 may include a CPU 210, a memory 220, a bus 230, an SSD interface 240, a workload module 250, a timer 260, and a performance adjustment module 270. ) May be included.

The SSD interface 240 includes an interface protocol for communicating with the semiconductor storage device 10.

The CPU 210 performs various control operations for writing / reading data to / from the semiconductor storage device 10.

The workload module 250 may collect workload data related to the workload applied to the semiconductor storage device 10 and predict the workload based on the collected workload data.

The performance adjusting module 270 determines the target performance level according to the workload predicted by the workload module 250, and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 260 provides time information to the CPU 210, the workload module 250, and the performance tuning module 270. Workload module 250, timer 260 and performance tuning module 270 may be implemented in software, hardware or a combination of software and hardware, respectively.

5A is a flowchart illustrating a performance adjusting method of the semiconductor storage device 10 according to an exemplary embodiment of the present invention. Method for adjusting the performance of the semiconductor storage device 10 according to an embodiment of the present invention is distributed to the semiconductor storage device 10, the host 20 or both the semiconductor storage device 10 and the host 20 shown in FIG. Can be implemented.

A method of adjusting performance according to an embodiment of the present invention will be described based on an example implemented in the semiconductor storage device 10, but as described above, the present invention is not limited thereto.

Referring to FIG. 5A, the controller 100 may collect workload data related to a workload applied to the semiconductor storage device 10 (S100) and predict a workload based on the collected workload data (S110). . The controller 100 may calculate a performance level according to the predicted workload and determine the performance level according to the performance adjustment policy (S120). Next, the determined performance level may be applied to the operation of the semiconductor storage device 10 (S130).

Embodiments of the present invention present a specific method for the step (S120) of determining the performance level according to the performance adjustment policy of the steps shown in FIG.

5B is a flowchart illustrating a performance adjusting method of the semiconductor storage device 10 according to an exemplary embodiment of the present invention. FIG. 6 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device 10 shown in FIG. 5B.

The controller 100 calculates a new performance level (S121). The new performance level may be calculated using the workload prediction value, but is not limited thereto (S121). Next, the new performance level, that is, the calculated performance level is compared with a predetermined criterion (S122). In this embodiment, the predetermined criterion is the minimum performance level. Therefore, in order to check whether the calculated new performance level is lower than the minimum performance level, the new performance level is compared with a predetermined minimum level (S122). As a result of the comparison, if the new performance level is lower than the minimum performance level, the minimum performance level is selected and the selected minimum performance level is applied (S123).

As a result of the comparison, if the new performance level is higher than or equal to the minimum level, the new performance level is selected as it is, and the selected new performance level is applied (S124).

The steps shown in FIG. 5B may correspond to steps S120 and S130 of FIG. 5A.

FIG. 6 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device 10 shown in FIG. 5B. Referring to this, as the workload changes, the performance level is also adjusted, but it does not go below the lowest performance level.

As described above, according to the embodiment of the present invention, if the newly calculated performance level is higher than or equal to the minimum performance level, the calculated performance level is determined and applied as it is, but the newly calculated performance level is the minimum performance level. If lower, select the minimum performance level so that the performance level is not lower than the minimum performance level. Accordingly, the lowest performance of the semiconductor storage device 10 is guaranteed even under adverse conditions with a maximum workload.

5C is a flowchart illustrating a method of controlling performance of the semiconductor storage device 10 according to another exemplary embodiment of the present invention.

Referring to FIG. 5C, the controller 100 calculates a new performance level (S121). The new performance level may be calculated using the workload prediction value, but is not limited thereto (S131). Next, the new performance level, that is, the calculated performance level is compared with a predetermined criterion (S132). In this embodiment, the predetermined criterion is the maximum performance level. Therefore, in order to check whether the calculated new performance level is higher than the maximum performance level, the new performance level is compared with a predetermined maximum level (S132). As a result of the comparison, if the new performance level is higher than the maximum performance level, the maximum performance level is selected, and the selected maximum performance level is applied (S133).

As a result of the comparison, if the new performance level is lower than or equal to the maximum performance level, the calculated performance level is selected as it is and the selected performance level is applied (S134).

As described above, according to another embodiment of the present invention, if the newly calculated performance level is lower than or equal to the maximum performance level, the calculated performance level is determined and applied as it is, but the newly calculated performance level is maximum. If it is higher than the performance level, the maximum performance level is determined as the new performance level so that the performance level is not higher than the maximum performance level.

The steps illustrated in FIG. 5C may correspond to steps S120 and S130 of FIG. 5A.

7 is a flowchart illustrating a performance adjusting method of the semiconductor storage device 10 according to another exemplary embodiment of the present invention. Referring to FIG. 7, when a new performance level is calculated and set (S210 and S220), the performance level is not changed for a predetermined period (S230).

To this end, it is checked whether a predetermined period has elapsed from when the new performance level is applied (S240), and when a predetermined period has elapsed from the time when the new performance level is applied, a new performance level is calculated (S210). This may be maintained (S230).

Alternatively, a new performance level may be calculated for each predetermined performance adjustment cycle, and the calculated new performance level may be applied to the semiconductor storage device 10. In this case, the performance level applied during the predetermined performance adjustment cycle is maintained, and when the performance adjustment cycle ends, a new performance level can be calculated and applied again. Here, the predetermined period or performance adjustment cycle may be a unit of time, day, week, month, etc., but is not limited thereto. In addition, the performance adjustment cycle may or may not coincide with the performance prediction cycle. For example, performance prediction may be in hours, but performance adjustment may be in days, and vice versa.

The predetermined period or performance adjustment period may be set in response to a period setting command received from the host. The period setting command may have a host command format shown in FIG. 13. The format of the period setting command of the host will be described later with reference to FIG. 13.

The host may set the time and length of the performance adjustment cycle as needed using the cycle setting command described above. The predetermined period or performance adjustment period may be set by a command from the host, but may be set in advance in the semiconductor storage device 10.

Adjusting storage performance only once every fixed period (e.g. 24 hours, 12 hours, 6 hours), and keeping the storage performance constant during that one cycle is too frequent. This is to prevent the predictability of storage performance from the host's perspective in case of change.

FIG. 8 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device 10 shown in FIG. 7. Referring to this, as the workload changes, it can be seen that the performance level is adjusted every performance tuning cycle.

9 is a flowchart illustrating a performance adjusting method of the semiconductor storage device 10 according to another exemplary embodiment of the present invention. Referring to FIG. 9, a new performance level is calculated (S310). The difference between the calculated performance level and the current performance level (hereinafter referred to as the first performance level) is compared with a predetermined reference difference (x%) (S320), and as a result of the comparison, the calculated performance level and the first performance If the difference between levels is lower than the reference difference, the calculated performance level is determined and applied as a new performance level (hereinafter referred to as a second performance level) (S350).

As a result of the comparison (S320), when the difference between the calculated performance level and the first performance level is higher than the reference difference, the difference between the calculated performance level and the first performance level is the reference difference (eg, x%). The calculated performance level is adjusted to be performed (S330), and the adjusted performance level is determined and applied as the second performance level (S340).

The reference difference may be preset to any value or to any ratio (eg, x%). When the reference difference is set as a ratio (eg, x%), the ratio (eg, x%) may be a ratio of the previous performance or the ratio of the highest performance, but is not limited thereto.

According to the exemplary embodiment of the present invention, when the performance of the semiconductor storage device 10 is adjusted, the reference difference (+/− x%) compared to the performance (or the highest performance) immediately before the adjusted performance is adjusted, the value of x is For example, 10%, 20%, 5%) to maintain within. This is to prevent the predictability of the performance of the semiconductor storage device 10 from deteriorating from the host point of view when the performance of the semiconductor storage device 10 suddenly changes significantly.

In an embodiment of the present invention, the performance adjusted for successive periods is less than or equal to +/− y% (y values, for example, 3%, 4%, 2%) relative to the previous performance (or peak performance). If n is maintained more than n times (integer of 2 or more), the reference difference (x) can be adjusted upward. This is to ensure that the performance of semiconductor storage devices that adapt well to regular workloads can respond effectively to sudden changes in workload.

In another embodiment of the present invention, the performance adjusted for successive periods is greater than or equal to +/- (z% (the value of z is 8%, 16%, 4%, etc.) compared to the previous performance (or best performance). If it is maintained more than m times (integer of 2 or more), the reference difference (x) can be adjusted downward. This is to effectively adapt the performance of semiconductor storage devices to volatile workloads.

In another embodiment of the present invention, in contrast to the embodiment described above, the performance adjusted for successive periods is +/− y% relative to the previous performance (or pore performance) (the value of y is, for example, 3%, If you keep the value of 4%, 2% or less continuously more than n (an integer of 2 or more), the reference difference (x) is adjusted downward, and the performance adjusted for successive periods is compared to the previous performance (or the highest performance). If the value of +/- z% (z is 8%, 16%, 4%, etc.) is continuously maintained at least m (an integer of 2 or more), the reference difference x may be adjusted upward.

FIG. 10 is a graph illustrating a change in performance level according to the method for adjusting performance of the semiconductor storage device 10 illustrated in FIG. 9. Referring to this, as the workload changes, the performance level is adjusted. At this time, it can be seen that the new performance level is adjusted within a predetermined reference difference (+/− ×%) compared to the previous performance level. However, as described above, in other embodiments, the new performance level may be adjusted within a predetermined reference difference (+/− ×%) relative to the highest performance level.

11 is a flowchart illustrating a performance adjusting method of the semiconductor storage device 10 according to another exemplary embodiment of the present invention. FIG. 12A is a graph illustrating a change in performance level according to the performance adjusting method of the semiconductor storage device 10 illustrated in FIG. 11. 12B is a graph for explaining a method of selecting a discrete level according to the calculated performance level.

11 through 12B, a new performance level is calculated (S410). A discrete level closest to the calculated performance level is selected from among the plurality of predetermined discrete levels Lv.1 to Lv.9 (S420). In the present embodiment, the plurality of discrete levels Lv.1 to Lv.9 are nine different performance levels, but are not limited thereto, and the number of discrete levels and the interval between the levels may vary.

12B, when the current performance level (first performance level) is Lv.5 and the calculated performance level is CL1, CL1 is Lv.5 than Lv.5. Assuming a value closer to 6, Lv. Is the discrete level closest to the calculated performance level (CL1). 6 is selected. Therefore, if the calculated performance level CL1 belongs to the period D6, then Lv. 6 is selected. If it is an intermediate value between neighboring discrete levels, the nearest discrete level may be two levels, in which case either one may be selected.

A level gap between the selected discrete level and the current performance level (first performance level) is calculated, and the calculated level gap is compared with a predetermined reference gap (S430). The level gap means how many steps the selected discrete level differs from the current performance level (first performance level). For example, if the current performance level (first performance level) is Lv.4 and the selected discrete level is Lv.3 or Lv.5, the level gap is 1, and the current performance level (first performance level) is Lv.4. If 4 and the selected discrete level is Lv.2 or Lv.6, the level gap is two.

As a result of the comparison, if the calculated level gap is lower than or equal to a predetermined reference gap (i, i is an integer of 1 or more), the selected discrete level is determined and applied as a new performance level (second performance level) (S460). For example, when the calculated level gap is 1 and the reference gap is 2, the selected discrete level is determined as a new performance level (second performance level) and applied.

As a result of the comparison, if the calculated level gap is higher than the reference gap i, the calculated level gap is adjusted so that the calculated level gap becomes the reference gap (S440), and the discrete corresponding to the adjusted level gap is determined. The level is determined as the second performance level and applied (S450).

For example, if the calculated level gap is 3 and the reference gap is 2, instead of determining the selected discrete level as a new performance level (second performance level), the calculated level gap is a reference gap (eg, 2). ), And the discrete level corresponding to the adjusted level gap (eg, 2) is determined and applied as the second performance level.

Referring back to FIG. 12B, when the current performance level (first performance level) is Lv. 6 and the calculated performance level is CL2, in step S420, the discrete level Lv. 3 that is closest to CL2 is selected.

Then, the level gap Lv.6-Lv.3 = 3 between the selected discrete level Lv.3 and the current performance level (first performance level, Lv.6) is calculated to calculate the calculated level gap 3. ) Is compared with a predetermined reference gap (eg, 2) (S430). Since the calculated level gap 3 is larger than the reference gap (eg, 2), the calculated level gap is adjusted to be the reference gap (S440), and the discrete level Lv. Corresponding to the adjusted level gap 2 is adjusted. Determine 4) as the second performance level. The discrete level finally selected is Lv.4, not Lv.3.

As described above, when the reference gap is 2, the performance level is changed only within two steps at a time and cannot be changed more than two steps.

In another embodiment of the present invention, when the difference between the second performance level (i.e., the newly applied performance level) and the first performance level (currently applied performance level) has a plurality (two or more) level differences, You can move through at least one intermediate level without moving the level at one time.

For example, if the second performance level is Lv.5 and the first performance level is Lv.2, the intermediate level between Lv.5 and Lv.2 is not applied directly from Lv.2 to Lv.5. After changing to at least one of the levels (LV3, Lv4) and apply to the target performance Lv.5 can be applied.

In addition, when moving through the intermediate performance level, after the minimum time for each level (step), whether to move automatically or again may be moved to the next performance level.

13 is a table illustrating a format of a host command according to an embodiment of the present invention. Referring to FIG. 13, the host 20 may include a command signal including a feature field, a count field, a logic block address (LBA) field, a device field, and a command field in relation to performance control of the semiconductor storage device 10. May be applied to the semiconductor storage device 10. Each field included in the command may consist of predetermined bits. For example, each of the command field, device field, and count field may consist of 8 bits.

The period setting command described above may also be defined to have a format similar to that of the host command shown in FIG. 13. However, the period setting command includes information about the period. The information about the period may be included in any one of a feature field, a count field, and a logic block address (LBA) field.

The performance control method of the semiconductor storage device 10 according to the embodiment of the present invention described above may be implemented by hardware, software, or a combination thereof. When the embodiment of the present invention is implemented in software, the performance storage program code including a plurality of subroutines for executing the method for adjusting the performance of the semiconductor storage device 10 according to the embodiment of the present invention is stored in the semiconductor storage device 10. Can be stored in a nonvolatile memory.

In this case, the controller may execute the performance adjusting method code of the semiconductor storage device 10 according to the exemplary embodiment of the present invention by executing the performance adjusting program code stored in the nonvolatile memory.

14 is a block diagram of an electronic system including a semiconductor storage device according to an embodiment of the present invention.

Referring to FIG. 14, an electronic system 900 according to an embodiment of the present invention may include a semiconductor storage device 10, a power supply 910, and a central processing unit (CPU) 920 according to an embodiment of the present invention. ), A RAM 930, a user interface 940, and a system bus 950 that electrically connects these components.

The CPU 920 controls the overall operation of the system 900, the RAM 930 stores information necessary for the operation of the system 900, and the User Interface 940 interfaces with the system 900 and the user. To provide. The power supply unit 910 supplies power to internal components (ie, the CPU 920, the RAM 930, the user interface 940, the memory system 500, and the like).

The CPU 920 may correspond to the host 20 described above, and the semiconductor storage device 10 may store or read data in response to a command of the host 20.

15A and 15B are each a block diagram of an electronic system according to another embodiment of the present invention.

Since the electronic system 900 ′ shown in FIG. 15A has a configuration similar to that of the electronic system 900 shown in FIG. 14, differences will be mainly described in order to avoid duplication of explanation.

The electronic system 900 ′ shown in FIG. 15A further includes a RAID controller card 960 as compared to the electronic system 900 shown in FIG. 14. The semiconductor storage device 10 may not be directly interfaced with the host but may be mounted in the RAID controller card 960 to interface with the host through the RAID controller card 960. In this case, a plurality of (two or more) semiconductor storage devices 10-1 to 10-k, and k is an integer of two or more, may be mounted in the RAID controller card 960. The RAID controller card 960 of the electronic system 900 ′ shown in FIG. 15A is implemented as a separate product outside the semiconductor storage devices 10-1 through 10-k.

Since the electronic system 900 ″ shown in FIG. 15B has a similar configuration to that of the electronic system 900 ′ shown in FIG. 15A, the differences will be mainly described in order to avoid duplication of explanation.

The electronic system shown in FIG. 15A in that the RAID controller card 960 of the electronic system 900 "shown in FIG. 15B is implemented as a single product together with the semiconductor storage devices 10-1 through 10-k. (900 ') is different.

As such, when the RAID controller card 960 is provided, the above-described performance adjusting method according to the embodiment of the present invention may be implemented by the RAID controller card 960. To this end, the above-described timer, performance control module, etc. may be provided in the RAID controller card 960.

16 is a block diagram of a computing system 1000 (PC) having a semiconductor storage device 10 according to an embodiment of the present invention. Referring to this, the computing system 1000 may include a central processing unit 1110, an accelerated graphics port 1120, a main memory 1130, a north bridge 1140, and a semiconductor storage device 1. For example, the SSD 10, a keyboard controller 1160, a printer controller 1170, and a south bridge 1180 may be included.

The computing system 1100 may be a block diagram of a personal computer or notebook computer that the SSD 10 uses as a primary storage device instead of a hard disk drive. However, the scope of the present invention is not limited thereto.

In the computing system 1000, the central processing unit 1110, the AGP device 1120, the main memory 1130, and the like are connected to the north bridge 1140, and the SSD 10, the keyboard controller 1160, and the printer controller ( 1170, and various peripheral devices (not shown) and the like are connected to the South Bridge 180.

The north bridge 1140 is an integrated circuit located at the socket of the central processing unit 1110 based on the center of the main board, and generally refers to a system controller including a host interface connecting to the central processing unit 1110. do. The south bridge 1180 is an integrated circuit located in a peripheral component interconnect (PCI) slot with respect to the center of the motherboard, and generally refers to a bridge from a host bus to a bus connected via a PCI bus.

AGP is a bus specification that enables rapid implementation of three-dimensional graphical representations. The AGP device 1120 may include a video card or the like for playing back a monitor image. The main memory 1130 may be generally implemented as a random access memory (RAM), which is a volatile memory device, but the scope of the present invention is not limited thereto.

In addition, in the computing system 1100 according to an embodiment of the present invention, the structure in which the SSD 10 is connected to the south bridge 180 is not limited thereto, and the SSD 10 is connected to the north bridge 1140. Or a structure directly connected to the CPU 1110.

Although the invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Semiconductor Storage Devices: 10
Host: 20
Controller: 100
Nonvolatile Memory Device: 200
CPU: 150, 210
Host interface: 110
DRAM: 120
SRAM: 130
Memory interface: 140
Timer: 150, 260
Bus: 160, 230
Workload module: 170, 250
Performance Control Module: 190, 270
Clock Generator: 195
Storage interface: 240

Claims (40)

A nonvolatile memory device for storing data nonvolatile; And
A controller for controlling the nonvolatile memory device,
The controller,
Calculating a new performance level of the nonvolatile memory device, comparing the calculated performance level with a predetermined criterion, and determining the calculated performance level as an updated performance level according to the comparison result. The method of claim 1,
The predetermined criterion is the minimum level,
The controller
Compare the calculated performance level with the minimum level, and, if the calculated performance level is lower than the minimum level, determine the minimum level as the updated performance level, and the calculated performance level is the minimum And a performance adjustment module that determines the calculated performance level as the updated performance level if it is higher than or equal to a level. The method of claim 1,
The predetermined criterion is the minimum level,
The nonvolatile memory device stores performance control program code.
The controller executes the performance adjusting program code to calculate the new performance level, compare the calculated performance level with the minimum level, and, if the calculated performance level is lower than the minimum level, the And determine a minimum level as the updated performance level, and if the calculated performance level is higher than or equal to the minimum level, determining the calculated performance level as the updated performance level. A nonvolatile memory device for storing data nonvolatile; And
A controller for controlling the nonvolatile memory device,
The controller,
Calculate a new performance level of the nonvolatile memory device, compare the difference between the calculated performance level and the first performance level with a predetermined criterion, and according to the comparison result, convert the calculated performance level to a second performance level. Semiconductor storage device to determine. The method of claim 4, wherein the first performance level is
Is a performance level currently being applied, and the second performance level is a performance level to be newly applied. The method of claim 5,
The predetermined criterion is a first reference difference,
The nonvolatile memory device stores performance control program code.
The controller executes the performance control program code to calculate the new performance level,
As a result of the comparison, when the difference between the calculated performance level and the first performance level is lower than the first reference difference, the calculated performance level is determined as the second performance level, and the calculated performance level and the first performance are determined. Compare the difference between levels with a predetermined criterion,
As a result of the comparison, when the difference between the calculated performance level and the first performance level is higher than or equal to the first reference difference, the calculated difference between the calculated performance level and the first performance level becomes the first reference difference. And adjust the performance level and determine the adjusted performance level as the second performance level. The method of claim 5,
The predetermined criterion is a first reference difference,
The controller
As a result of the comparison, if the difference between the calculated performance level and the first performance level is lower than the first reference difference, the calculated performance level is determined as the second performance level,
As a result of the comparison, when the difference between the calculated performance level and the first performance level is higher than or equal to the first reference difference, the calculated difference between the calculated performance level and the first performance level becomes the first reference difference. And adjust the performance level and determine the adjusted performance level as the second performance level. The method of claim 6 or 7, wherein the first reference difference is
And a ratio to the first performance level or a ratio to the highest performance level. The method of claim 6 or 7, wherein the first reference difference is
A semiconductor storage device that is changed according to a command from a host or a result of a plurality of performance adjustments. A nonvolatile memory device for storing data nonvolatile; And
A controller for controlling the nonvolatile memory device,
The controller,
Calculating a new performance level, selecting a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels, and determining a second performance level using the selected discrete level. The method of claim 10,
The nonvolatile memory device stores performance control program code.
The controller executes the performance control program code to calculate the new performance level and to select a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels,
Comparing the difference between the calculated performance level and the first performance level with a predetermined criterion,
If the calculated level gap is lower than or equal to the reference gap, the selected discrete level is determined as the second performance level. If the calculated level gap is higher than the reference gap, the calculated level is determined. And adjust the calculated level gap so that the gap becomes the reference gap, and determine a discrete level corresponding to the adjusted level gap as the second performance level. The method of claim 10, wherein the controller
Calculate the new performance level and select a discrete level closest to the calculated performance level from among a plurality of predetermined discrete levels,
Comparing the difference between the calculated performance level and the first performance level with a predetermined criterion,
If the calculated level gap is lower than or equal to the reference gap, the selected discrete level is determined as the second performance level. If the calculated level gap is higher than the reference gap, the calculated level is determined. And a performance adjusting module for adjusting the calculated level gap so that the gap becomes the reference gap, and determining a discrete level corresponding to the adjusted level gap as the second performance level. A nonvolatile memory device for storing data nonvolatile; And
A controller for controlling the nonvolatile memory device,
The controller,
A new performance level is calculated, the second performance level is determined using the calculated performance level, and the semiconductor storage device operates according to a first performance level, and when the second performance level is determined, the second performance level is determined. And operate for at least a predetermined period of time. The method of claim 13,
The nonvolatile memory device stores performance control program code.
The controller executes the performance control program code, calculates the new performance level, and determines the second performance level using the calculated performance level. The method of claim 13, wherein the semiconductor storage device is
Semiconductor storage device, characterized in that the SSD or SD card. A host device for controlling a semiconductor storage device,
A performance adjusting module for calculating a new performance level, comparing the calculated performance level with a predetermined criterion, and determining the calculated performance level as a second performance level according to the comparison result; And
A storage device interface module configured to set the semiconductor storage device to operate according to a first performance level, and to set the semiconductor storage device to operate according to the second performance level when the second performance level is determined. . A host device for controlling a semiconductor storage device,
A performance adjustment module for calculating a new performance level, comparing the difference between the calculated performance level and the first performance level with a predetermined criterion, and determining, according to the comparison result, the calculated performance level as a second performance level: And
And a storage interface module configured to set the semiconductor storage device to operate according to the first performance level, and to set the semiconductor storage device to operate according to the second performance level when the second performance level is determined. Device. A host device for controlling a semiconductor storage device,
Calculating a new performance level and selecting a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels, comparing the difference between the calculated performance level and the first performance level with a predetermined criterion, A performance adjustment module for determining a second performance level using the selected discrete level; And
A storage device interface module configured to set the semiconductor storage device to operate according to a first performance level, and to set the semiconductor storage device to operate according to the second performance level when the second performance level is determined. . A host device for controlling a semiconductor storage device,
A performance adjustment module that calculates a new performance level and determines a second performance level using the calculated performance level; And
And a storage interface module configured to set the semiconductor storage device to operate according to the first performance level, and to set the semiconductor storage device to operate according to the second performance level when the second performance level is determined. A method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller controlling the nonvolatile memory device,
(a) operating the semiconductor storage device according to a first performance level;
(b) calculating a new performance level;
(c) comparing the calculated performance level with a predetermined criterion;
(d) determining the calculated performance level as a second performance level according to the comparison result; And
(e) operating the semiconductor storage device in accordance with the second performance level. The method of claim 20,
The predetermined criterion is the minimum level,
The step (d)
Determining that the minimum level is the second performance level if the calculated performance level is lower than the minimum level; And
And determining the calculated performance level as the second performance level if the calculated performance level is higher than or equal to the minimum level. The method of claim 20,
The predetermined criterion is the maximum level,
The step (d)
Determining the maximum level as the second performance level if the calculated performance level is higher than the maximum level as a result of the comparison; And
And determining the calculated performance level as the second performance level if the calculated performance level is lower than or equal to the maximum level. The method of claim 20, wherein the performance level is
And a write performance level of the semiconductor storage device, which is represented by any one of a number of write commands processed per unit time, an amount of data written per unit time, or a plurality of level values. The method of claim 20, wherein the performance level is
And a read performance level of the semiconductor storage device, wherein the read performance level is displayed as one of a number of read commands processed per unit time, an amount of data read per unit time, or a plurality of level values. A method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller controlling the nonvolatile memory device,
(a) operating the semiconductor storage device according to a first performance level;
(b) calculating a new performance level;
(c) comparing the difference between the calculated performance level and the first performance level with a predetermined criterion;
(d) adjusting the calculated performance level and determining the adjusted performance level as a second performance level according to the comparison result; And
(e) operating the semiconductor storage device in accordance with the second performance level. The method of claim 25,
The predetermined criterion is a first reference difference,
The step (d)
Determining the calculated performance level as the second performance level if a difference between the calculated performance level and the first performance level is lower than the first reference difference as a result of the comparison; And
As a result of the comparison, when the difference between the calculated performance level and the first performance level is higher than or equal to the first reference difference, the calculated difference between the calculated performance level and the first performance level becomes the first reference difference. Adjusting a performance level, and determining the adjusted performance level as the second performance level. The method of claim 26, wherein the first reference difference is
And a ratio of the first performance level or the ratio of the highest performance level. 27. The method of claim 26, wherein the method
And changing the first reference difference. 29. The method of claim 28, wherein changing the first reference difference is
Increasing the first reference difference when the second performance level maintains a value equal to or less than a second reference difference compared to the first performance level performance more than n times (an integer of 2 or more). How to tune performance. The method of claim 29, wherein the second reference difference is
And less than 1/2 of the first reference difference. 29. The method of claim 28, wherein changing the first reference difference is
Reducing the first reference difference when the second performance level maintains a value equal to or greater than a third reference difference relative to the first performance level performance more than m (an integer greater than or equal to) two times. How to adjust. The method of claim 31, wherein the third reference difference is
And a half or more of the first reference difference. A method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller controlling the nonvolatile memory device,
(a) operating the semiconductor storage device according to a first performance level;
(b) calculating a new performance level;
(c) selecting a discrete level closest to the calculated performance level among a plurality of predetermined discrete levels;
(d) determining a second performance level using the selected discrete level; And
(e) operating the semiconductor storage device in accordance with the second performance level. The method of claim 33, wherein step (d)
Calculating a level gap between the selected discrete level and the first performance level;
Comparing the calculated level gap with a predetermined reference gap;
Determining the selected discrete level as the second performance level if the calculated level gap is lower than or equal to the reference gap; And
As a result of the comparison, if the calculated level gap is higher than the reference gap, the calculated level gap is adjusted so that the calculated level gap becomes the reference gap, and the discrete level corresponding to the adjusted level gap is adjusted to the second performance. Determining the level of the semiconductor storage device. The method of claim 34, wherein the method is
Changing and applying at least one intermediate level between the second performance level and the first performance level when a level difference between the second performance level and the first performance level is a plurality of levels;
Wherein (e) is performed after the step of applying the change to the intermediate level. 36. The method of claim 35, wherein each of the at least one intermediate level is applied for a predetermined minimum time. A method of controlling performance of a semiconductor storage device including a nonvolatile memory device and a controller controlling the nonvolatile memory device,
(a) operating the semiconductor storage device according to a first performance level;
(b) calculating a new performance level; And
(c) determining a second performance level using the calculated performance level; And
(d) operating the semiconductor storage device according to the second performance level for at least a predetermined period. 38. The method of claim 37, wherein the period is
And setting the response in response to the period setting command received from the host. The method of claim 37, wherein the method is
And performing steps (a) to (d) at each cycle. A recording medium on which a program for executing the performance adjusting method of the semiconductor storage device according to any one of claims 20 to 39 is recorded.

Images