JPH0680735B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0680735B2 JPH0680735B2 JP18482186A JP18482186A JPH0680735B2 JP H0680735 B2 JPH0680735 B2 JP H0680735B2 JP 18482186 A JP18482186 A JP 18482186A JP 18482186 A JP18482186 A JP 18482186A JP H0680735 B2 JPH0680735 B2 JP H0680735B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- semiconductor device
- wiring
- layer wiring
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線構造を有する半導体装置に関し、特に
下層配線と上層配線の接続構造に関する。The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly to a connection structure for a lower layer wiring and an upper layer wiring.
従来、多層配線構造を有する半導体装置においては、ス
ルーホール１個に付き一対の下層配線と上層配線とを電
気的に接続する構造となっていた。すなわち、第３図に
示すように絶縁膜２上に形成されていた下層配線３は、
層間絶縁膜４に形成されたスルーホール6Aを介して上層
配線５に接続していた。Conventionally, a semiconductor device having a multilayer wiring structure has a structure in which a pair of lower layer wiring and upper layer wiring are electrically connected to each through hole. That is, the lower layer wiring 3 formed on the insulating film 2 as shown in FIG.
It was connected to the upper layer wiring 5 through a through hole 6A formed in the interlayer insulating film 4.
上述した従来の多層配線構造に用いられるスルーホール
は、半導体装置の微細化及び高集積化が進むにつれて、
寸法が極めて微細かつ、高密度で使用されるようになっ
てきている。しかし、スルーホールの寸法が微細化すれ
ばする程、スルーホールの開口部が狭くなり、上層配線
層を被着する時にスルーホール部でのステップカバレッ
ジが悪化する傾向が現われてくる。Through holes used in the above-mentioned conventional multilayer wiring structure are, as semiconductor devices are miniaturized and highly integrated,
The size is extremely fine and it is being used with high density. However, as the size of the through hole becomes finer, the opening portion of the through hole becomes narrower, and the step coverage in the through hole portion tends to deteriorate when the upper wiring layer is deposited.
この現象は、層間膜厚と、スルーホール寸法が同程度、
すなわちアスペクト比が１以上になったときに顕著とな
ってくる。しかし、層間膜厚を薄くすると寄生容量が増
大し、半導体装置の性能の劣化及び、ピンホール等によ
る信頼性の低下を引き起こすため、層間膜はある程度以
下には薄くできない。This phenomenon is because the interlayer film thickness and the through hole
That is, it becomes remarkable when the aspect ratio becomes 1 or more. However, if the thickness of the interlayer film is reduced, the parasitic capacitance increases, and the performance of the semiconductor device is deteriorated, and the reliability is deteriorated due to pinholes. Therefore, the thickness of the interlayer film cannot be reduced to a certain extent or less.
本発明の目的は、スルーホールの寸法を小さくすること
なく、実効的にスルーホールの密度を増加させ集積度を
向上させた半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device in which the density of through holes is effectively increased and the degree of integration is improved without reducing the size of the through holes.
本発明の半導体装置は、スルーホールにより下層配線と
上層配線とが接続されてなる多層配線構造を有する半導
体装置であって、少くとも１個の前記スルーホール内に
複数個の下層配線と上層配線の接続部をそれぞれ電気的
に分離して形成したものである。The semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure in which a lower layer wiring and an upper layer wiring are connected by a through hole, and a plurality of lower layer wirings and upper layer wirings are provided in at least one of the through holes. The connection portions of are electrically separated from each other.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ′線断面図である。1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of one embodiment of the present invention.
第１図（ａ），（ｂ）において、半導体基板１上に形成
された絶縁膜２上には複数の下層配線3A〜3Dが形成され
ており、更にその上には層間絶縁膜４を介して上層配線
5A〜5Dが形成されている。そしてこの下層配線と上層配
線の複数の接続部は、スルーホール６内において電気的
に分離されて形成されている。すなわち、下送配線3A〜
3Dと上層配線5A〜5Dとの接続部Ａ〜Ｄは、１つのスルー
ホール６内に形成されている。In FIGS. 1A and 1B, a plurality of lower layer wirings 3A to 3D are formed on an insulating film 2 formed on a semiconductor substrate 1, and an interlayer insulating film 4 is formed on the lower wirings 3A to 3D. Upper wiring
5A to 5D are formed. A plurality of connecting portions of the lower layer wiring and the upper layer wiring are formed in the through hole 6 while being electrically separated. That is, the lower wiring 3A ~
Connection portions A to D between the 3D and the upper layer wirings 5A to 5D are formed in one through hole 6.
本実施例をより詳しく説明するために、本実施例の製造
方法について第２図（ａ），（ｂ）を併用して説明す
る。In order to explain this example in more detail, the manufacturing method of this example will be described with reference to FIGS. 2 (a) and 2 (b).
まず、第２図（ａ）に示すように、シリコンからなる半
導体基板１上にSiO2等からなる絶縁膜２とAl又はAl合金
からなる下層配線3A〜3Dを形成する。First, as shown in FIG. 2A, an insulating film 2 made of SiO 2 or the like and lower wirings 3A to 3D made of Al or an Al alloy are formed on a semiconductor substrate 1 made of silicon.
次に、第２図（ｂ）に示すように、層間絶縁膜４及びス
ルーホール６を形成する。層間絶縁膜４は例えばプラズ
マ窒化膜等であり、スルーホールは所定の場所に通常の
フォトリソグラフ及びエッチング方法で形成する。例え
ば、エッチングは、パターンの形成されたレジストをマ
スクとしてCF4＋O2の反応ガスを用いるプラズマ等方性
エッチング法と、CF4系ガスを用いるRIE異方性エッチン
グ法とを組み合わせた方法などで行なう。Next, as shown in FIG. 2B, the interlayer insulating film 4 and the through hole 6 are formed. The interlayer insulating film 4 is, for example, a plasma nitride film or the like, and the through hole is formed at a predetermined place by a normal photolithography and etching method. For example, the etching is performed by combining a plasma isotropic etching method using a CF 4 + O 2 reaction gas with a patterned resist as a mask and a RIE anisotropic etching method using a CF 4 -based gas. To do.
次に、第１図（ａ），（ｂ）に示したように上層配線用
金属を被着したのち、上層配線のパターニングを行な
う。この工程により下層配線と上層配線との接続部Ａ〜
Ｄがそれぞれ電気的に分離されてスルーホール６内に形
成される。Next, as shown in FIGS. 1A and 1B, after depositing the metal for the upper layer wiring, the upper layer wiring is patterned. Through this step, the connection portion A between the lower layer wiring and the upper layer wiring
D is electrically isolated from each other and formed in the through hole 6.
上記実施例の接続部を従来の構造で実施するためには、
４個のスルーホールが必要となり、スルーホールのサイ
ズを本実施例と同じ大きさとするならば約４倍の面積が
必要となる。また、スルーホールのサイズを小さくし
て、本実施例と同等の面積に抑えようとするとスルーホ
ール部における上層配線のステップカバレッジが悪化し
半導体装置の信頼性は低下する。In order to implement the connecting portion of the above embodiment with the conventional structure,
Four through holes are required, and if the size of the through holes is the same as that of this embodiment, an area of about 4 times is required. Further, if the size of the through hole is made smaller so as to be suppressed to the same area as that of this embodiment, the step coverage of the upper layer wiring in the through hole portion is deteriorated and the reliability of the semiconductor device is lowered.
以上説明したように本発明は、１個のスルーホール内
に、複数個の下層配線と上層配線の接続部をそれぞれ電
気的に分離して形成することにより、スルーホール部に
おける上層配線層のステップカバレッジを悪化させるこ
となく、実効的にスルーホール密度を向上させることが
できる効果があるので、集積度の向上した半導体装置が
得られる。As described above, according to the present invention, a step of the upper wiring layer in the through hole portion is formed by electrically separating a plurality of connection portions of the lower wiring and the upper wiring in each through hole. Since there is an effect that the through hole density can be effectively increased without deteriorating the coverage, a semiconductor device with an improved degree of integration can be obtained.
第１図（ａ），（ｂ）は本発明の一実施例のスルーホー
ル部の平面図及びＡ−Ａ′線断面図、第２図（ａ），
（ｂ）は本発明の一実施例の製造方法を説明するための
工程順に示した断面図、第３図は従来の半導体装置のス
ルーホール部の断面図である。 １……半導体基板、２……絶縁膜、3,3A,3B,3C,3D……
下層配線、４……層間絶縁膜、5,5A,5B,5C,5D……上層
配線、6,6A……スルーホール、A,B,C,D……接続部。FIGS. 1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the through hole portion of one embodiment of the present invention, and FIGS.
FIG. 3B is a sectional view showing the order of steps for explaining the manufacturing method of the embodiment of the present invention, and FIG. 3 is a sectional view of a through hole portion of a conventional semiconductor device. 1 ... semiconductor substrate, 2 ... insulating film, 3,3A, 3B, 3C, 3D ...
Lower layer wiring, 4 ... Interlayer insulating film, 5,5A, 5B, 5C, 5D ... Upper layer wiring, 6,6A ... Through hole, A, B, C, D ... Connecting part.
Claims (1)
が接続されてなる多層配線構造を有する半導体装置にお
いて、少くとも１個の前記スルーホール内には、複数個
の下層配線と上層配線の接続部がそれぞれ電気的に分離
されて形成されていることを特徴とする半導体装置。1. A semiconductor device having a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a through hole, and a plurality of lower wirings and upper wirings are connected in at least one of the through holes. A semiconductor device, wherein the parts are formed electrically separated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18482186A JPH0680735B2 (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18482186A JPH0680735B2 (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6340344A JPS6340344A (en) | 1988-02-20 |
| JPH0680735B2 true JPH0680735B2 (en) | 1994-10-12 |
Family
ID=16159878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18482186A Expired - Lifetime JPH0680735B2 (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680735B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4841220B2 (en) * | 2005-10-14 | 2011-12-21 | 株式会社リコー | Semiconductor device |
-
1986
- 1986-08-05 JP JP18482186A patent/JPH0680735B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6340344A (en) | 1988-02-20 |
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