JP2019110280A - Method of manufacturing semiconductor device - Google Patents

Abstract

An object of the present invention is to suppress the formation of voids inside solder when soldering between a lower electrode of a semiconductor element and a conductor member. A method of manufacturing a semiconductor device disclosed in this specification includes a step of forming a lower electrode including a Ni-Sn alloy layer on a lower surface of a semiconductor element, and a method of forming a lower electrode of the semiconductor element by using a solder containing Sn. And soldering to the conductor member. In the soldering in this manufacturing method, the Ni-Sn alloy layer and the solder are integrated, and the conductor member is joined to the lower electrode. [Selection diagram] FIG.

Description

  The technology disclosed herein relates to a method of manufacturing a semiconductor device.

  Patent Document 1 discloses a method of manufacturing a semiconductor device. In this semiconductor device, the lower surface electrode of the semiconductor element and the conductor member are joined by soldering using a solder containing Sn (tin).

JP, 2015-162613, A

  In the above-mentioned soldering, in the lower surface electrode of the semiconductor element, Ni (nickel) contained in the lower surface electrode and Sn of the solder form a Ni-Sn (nickel-tin) alloy layer, thereby the lower surface electrode and the conductor member And are joined. However, when the Ni—Sn alloy layer is formed, a gas (for example, hydrogen, argon, etc.) is generated from the lower electrode (in particular, the nickel layer). The generated gas remains as it is in the solder and condenses to form a relatively large void. The present specification provides a technique for suppressing the formation of voids inside the solder in soldering between the lower electrode of the semiconductor element and the conductor member.

  In the method of manufacturing a semiconductor device disclosed in the present specification, a step of forming a lower surface electrode including a Ni—Sn alloy layer on the lower surface of the semiconductor element, and a lower surface electrode of the semiconductor element using a solder containing Sn. And soldering the conductor member. In the soldering in this manufacturing method, the Ni-Sn alloy layer and the solder are integrated, and the conductor member is joined to the lower surface electrode.

  The above manufacturing method includes the step of forming a lower surface electrode including a Ni-Sn alloy layer on the lower surface of the semiconductor element. Since this process is performed prior to the soldering process, even if a gas is generated when forming the Ni-Sn alloy layer, the gas can be discharged to the outside. Thereafter, the Ni-Sn alloy layer and the solder are integrated by soldering, and the conductor member is joined to the lower surface electrode. At this time, even if the Ni-Sn alloying reaction occurs, the gas is released in the step of forming the lower surface electrode (in particular, the step of forming the Ni-Sn alloy layer). The generation of gas is suppressed. This can suppress the formation of voids inside the solder.

FIG. 3 is a cross-sectional view showing an internal structure of the semiconductor device 10; A process of preparing the semiconductor element 12 having the Ni layer 44 and the Sn layer 46 on the lower surface 12 b is shown. A process of forming a Ni—Sn alloy layer 45 on the lower surface 12 b of the semiconductor element 12 is shown. A process of forming an Au (gold) layer 48 on the Ni—Sn alloy layer 45 is shown. A step of arranging the solder 50 between the lower surface electrode 16 of the semiconductor element 12 and the lower surface side conductor plate 20 is shown. A step of soldering between the lower surface electrode 16 of the semiconductor element 12 and the lower surface side conductor plate 20 is shown.

  A semiconductor device 10 and a method of manufacturing the same will be described as one embodiment with reference to the drawings. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12, a conductor spacer 18, a lower surface side conductor plate 20, an upper surface side conductor plate 22, and a mold resin 26. The semiconductor element 12 is sealed in a mold resin 26. The mold resin 26 is made of an insulating material. Although not particularly limited, the material forming the mold resin 26 may be a thermosetting resin material such as an epoxy resin.

  The semiconductor element 12 has an upper surface electrode 14 and a lower surface electrode 16. The semiconductor element 12 can adopt an IGBT (Insulated Gate Bipolar Transistor) element as an example. However, the semiconductor device 12 is not particularly limited to the IGBT device, and may be another power semiconductor device such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device. The semiconductor element 12 can be configured using various semiconductor materials such as Si (silicon), SiC (silicon carbide), or GaN (gallium nitride), for example. The upper surface electrode 14 is located on the upper surface 12 a of the semiconductor element 12, and the lower surface electrode 16 is located on the lower surface 12 b of the semiconductor element 12. Although it does not specifically limit as a material which comprises the upper surface electrode 14 and the lower surface electrode 16, For example, aluminum type or another metal is employable.

  The conductor spacer 18 can be configured using a conductive material such as copper or other metal. The conductor spacer 18 is a generally plate-shaped or block-shaped member, and has an upper surface 18a and a lower surface 18b opposite to the upper surface 18a. The upper surface 18 a of the conductor spacer 18 is joined to the lower surface 22 b of the upper surface side conductor plate 22 described later via the solder layer 36. The lower surface 18 b of the conductive spacer 18 is bonded to the upper surface electrode 14 of the semiconductor element 12 via the solder layer 34. Thus, the conductor spacer 18 is electrically connected to the semiconductor element 12. The conductor spacer 18 is not necessarily required, but secures a space when connecting the signal terminal (not shown) to the semiconductor element 12.

  The lower surface side conductor plate 20 and the upper surface side conductor plate 22 can be configured using a conductive material such as copper or other metal. The lower surface side conductor plate 20 is, for example, a member having a generally plate shape or a rectangular parallelepiped shape, and has an upper surface 20a and a lower surface 20b opposite to the upper surface 20a. The upper surface 20 a of the lower surface side conductor plate 20 is joined to the lower surface electrode 16 of the semiconductor element 12 via the solder layer 32. Thus, the lower surface side conductor plate 20 is electrically connected to the semiconductor element 12. In the present embodiment, the lower surface 20b of the lower surface side conductor plate 20 is exposed to the outside of the mold resin 26, although this is an example. Here, the lower surface side conductor plate 20 is an example of a conductor member in the present technology, but the conductor member is not particularly limited.

  The upper surface side conductor plate 22 is, for example, a member having a generally plate shape or a rectangular parallelepiped shape, and has an upper surface 22a and a lower surface 22b opposite to the upper surface 22a. As described above, the lower surface 22 b of the upper surface side conductor plate 22 is connected to the upper surface 18 a of the conductor spacer 18 via the solder 36 layer. Thus, the top side conductor plate 22 is electrically connected to the conductor spacer 18 and electrically connected to the semiconductor element 12 through the conductor spacer 18. In the present embodiment, the upper surface 22 a of the upper surface side conductor plate 22 is exposed to the outside of the mold resin 26, although this is an example. The lower surface side conductor plate 20 and the upper surface side conductor plate 22 are also thermally connected to the semiconductor element 12 and also function as a heat dissipation plate for releasing the heat generated by the semiconductor element 12 to the outside. That is, the semiconductor device 10 of the present embodiment has a double-sided cooling structure in which the heat sink is exposed on both sides of the mold resin 26. However, the semiconductor device 10 is not limited to the double-sided cooling structure, and, for example, either the lower surface 20b of the lower surface side conductor plate 20 or the upper surface 22a of the upper surface side conductor plate 22 is exposed to the outside of the mold resin 26 It may have a single sided cooling structure.

  A method of manufacturing the semiconductor device 10 will be described with reference to FIGS. As shown in FIG. 2, the Al-Si (aluminum-silicon) layer 40, the Ti (titanium) layer 42, and the Ni layer 44 are in this order on the lower surface 12b of the semiconductor element 12 prepared in this embodiment. It is laminated and formed. Furthermore, in the present embodiment, the Sn layer 46 is formed on the Ni layer 44. Each of these metal layers 40, 42, 44, 46 may be formed by sputtering, for example. In one example, the thickness dimensions of the Al-Si layer 40 and the Ti layer 42 formed at this time may be about 0.8 μm and about 0.2 μm, respectively. Also, the thickness dimension of the Ni layer 44 may be, for example, about 1 μm.

  As shown in FIG. 3, the Ni layer 44 and the Sn layer 46 on the lower surface 12 b of the semiconductor element 12 described above are heated to form a Ni—Sn alloy layer 45. For example, annealing or the like can be employed as this heat treatment. Thus, when the Ni layer 44 and the Sn layer 46 are heated and melted by annealing, Ni and Sn are alloyed to form an intermetallic compound containing Ni and Sn. During this alloying, the gas (for example, hydrogen, argon, etc.) contained inside the Ni layer 44 is released from the Ni layer 44, but the gas generated here may be released to the outside. it can. Thereby, the lower surface electrode 16 including the Ni—Sn alloy layer 45 in the present embodiment is formed. As shown in FIG. 4, an Au layer 48 is further formed on the Ni—Sn alloy layer 45 on the lower surface electrode 16. The Au layer 48 is formed to cover the Ni-Sn alloy layer 45, and can prevent the Ni-Sn alloy layer 45 from being oxidized. The Au layer 48 may be formed by sputtering or the like as the other metal layers 40, 42. The thickness dimension of the Au layer 48 may be, for example, about 0.1 μm.

  As shown in FIG. 5, the lower surface side conductor plate 20 is prepared, and the solder 50 is disposed between the lower surface electrode 16 and the lower surface side conductor plate 20 of the semiconductor element 12 formed in the previous step to form a laminate X. Do. Here, the solder 50 is mainly made of Sn, and for example, a sheet-shaped solder can be adopted. Further, the lower surface side conductor plate 20 may be prepared in the form of a lead frame together with other members (for example, external connection terminals). Next, as shown in FIG. 6, the lower surface electrode 16 of the semiconductor element 12 and the lower surface side conductor plate 20 are soldered, for example, in a reflow process. In this reflow step, the lower electrode 16 and the lower conductor plate 20 are joined by heating the laminate X in a reflow furnace to melt the solder 50. During this bonding, the Au layer 48 is diffused into the solder 50 or the Ni—Sn alloy layer 45, and the covering of the Ni—Sn alloy layer 45 by the Au layer 48 is eliminated. Then, the Ni—Sn alloy layer 45 and the solder 50 are integrated, and the solder layer 32 is formed. As a result, the lower surface side conductor plate 20 is joined to the lower surface electrode 16. However, the form of the integration of the Ni-Sn alloy layer 45 and the solder 50 is not particularly limited, and at least a part of the Ni-Sn alloy layer 45 may be integrated with the solder 50 to form the solder layer 32 .

  During the above-mentioned soldering, even if the Ni-Sn alloying reaction occurs, the gas is released in the step of forming the lower surface electrode 16 (in particular, the step of forming the Ni-Sn alloy layer 45). Therefore, the generation of gas in this soldering is suppressed. This can suppress the formation of voids inside the solder.

  Here, as an example, the above-mentioned Sn layer 46 may have a thickness dimension sufficient for an alloying reaction with the Ni layer 44. In this case, since all of the Ni layer 44 is alloyed in the stage of forming the Ni-Sn alloy layer 45, no gas is released during soldering in the later step, and the inside of the solder layer 32 is not generated. It is possible to prevent the formation of a void. In addition, if the Sn layer 46 is present in excess, the melting point is low and there is a possibility that the Sn may be melted by the heat in the subsequent step. For this reason, by forming the Sn layer 46 with the thickness dimension necessary for the reaction with the Ni layer 44, it is possible to avoid that Sn is unintentionally melted in the later steps. Furthermore, since Sn is alloyed with Ni, the melting point becomes high, and it is possible to manufacture the semiconductor device 10 having excellent bonding strength (e.g., tensile strength) between the lower surface electrode 16 and the lower surface side conductor plate 20.

  After the above manufacturing process, the conductor spacer 18 and the upper surface side conductor plate 22 are stacked on the upper surface electrode 14 of the semiconductor element 12 and soldered respectively. Here, as described above, solder layers 34 and 36 are interposed between the upper surface electrode 14 and the conductor spacer 18, and between the conductor spacer 18 and the upper surface side conductor plate 22, respectively. Next, the semiconductor element 12, the conductor spacer 18, the lower surface side conductor plate 20 and the upper surface side conductor plate 22 are sealed with the mold resin 26. However, for example, when the surface of each of these portions is not exposed after sealing, the surface of the mold resin 26 is ground to expose each surface. Finally, for example, an unnecessary portion (for example, a tie bar of a lead frame) is removed and the electric circuit is made independent to complete the semiconductor device 10.

  Although some specific examples have been described above in detail, these are merely examples and do not limit the scope of the claims. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations.

10: semiconductor device 12: semiconductor element 14: upper surface electrode 16: lower surface electrode 18: conductor spacer 20: lower surface side conductor plate 22: upper surface side conductor plate 26: mold resin 32, 34, 36: solder layer 40: Al-Si layer 42: Ti layer 44: Ni layer 45: Ni-Sn alloy layer 46: Sn layer 48: Au layer 50: solder X: laminate

Claims (1)

Forming a lower electrode including a Ni-Sn alloy layer on the lower surface of the semiconductor element;
Soldering the lower surface electrode of the semiconductor element to a conductor member using a solder containing Sn,
In the soldering, the Ni-Sn alloy layer and the solder are integrated, and the conductor member is joined to the lower surface electrode.
Semiconductor device manufacturing method.

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