JP2019008731A - Control board, control board backup power supply method, control board backup power supply program - Google Patents

Abstract

Provided is a control board capable of reducing a load in terms of cost, size, and environment by reducing batteries as much as possible while satisfying a conventional data retention period. In a communication control board 10A applied to this image forming apparatus, a voltage monitoring circuit 20 that monitors the voltage of a storage battery 19 stops power supply (the power supply voltage of 3.3V supplied to the communication control board 10A is reduced). If the battery voltage of the storage battery 19 exceeds the lower limit value of the recommended operating voltage of the SRAM 17 and the DRAM 18, the switch (SW) 21 is kept on and the backup power supply to the DRAM 18 together with the SRAM 17 is continued. Let me do it. In addition, when the battery voltage of the storage battery 19 becomes equal to or lower than the lower limit value of the recommended operating voltage, the voltage monitoring circuit 20 keeps the switch 21 off and stops the backup power supply to the DRAM 18 (the backup power supply to the SRAM 17 is continued). . [Selection] Figure 1

Description

  The present invention relates to a control board, a control board backup power supply method, and a control board backup power supply program.

  Conventionally, as an example of a control board on which a device is mounted and supplied with power at a predetermined voltage, a communication control board for FAX communication or the like mounted on an image forming apparatus can be cited. On this communication control board, a line control device for connecting to the public line and a CPU (Central Processing Unit) for communication control as a control unit responsible for overall control related to communication processing are mounted. The communication control board is mounted with a modem that is disposed between the line control device and the communication control CPU and modulates transmission data and demodulates reception data.

  Further, the communication control board is mounted with a reset IC that monitors the power supply voltage supplied to the communication control CPU and determines whether or not to perform a hard reset according to the voltage value. In addition, various memories are mounted on the communication control board. The various memories include a non-volatile memory in which a program (software) related to the control of the communication control CPU is stored, and a volatile memory for storing various data. The communication control board here can illustrate the case where power is supplied at a voltage of 3.3V.

  Non-volatile memory can be exemplified by ROM (Read Only Memory). The volatile memory may be an SRAM (Static Random Access Memory) that stores user setting data and management data of the image forming apparatus as data that needs to be stored during a product warranty period (hereinafter referred to as a warranty period). The data stored here is back-up powered to the SRAM using a primary battery so that the data can be retained even when the image forming apparatus is not powered (during shutdown). As another volatile memory, a DRAM (Dynamic Random Access Memory) that holds data transmitted or received for communication can be exemplified. The data stored here is also backed up using a secondary battery (storage battery) so that it can be retained even in the event of a momentary power failure.

  An SRAM generally consumes about 1 uA when holding its data. For this reason, even a button battery of about 600 mAh can retain data for more than 5 years, and can protect data over the warranty period. On the other hand, the current consumption at the time of data retention of DRAM is several mA compared to the case of SRAM, and a button battery of about 600 mAh has only about 100 hours. Therefore, for example, when backup power supply for both SRAM and DRAM is performed with one button battery, the remaining battery capacity becomes zero in about 100 hours. In this state, it means that the data in the SRAM that needs to be retained for the warranty period is lost.

  In order to counter these problems, the battery capacity may be increased, but for that purpose, a battery of about 300,000 mAh is required, which greatly affects the size and cost of the image forming apparatus. Therefore, if the SRAM battery and the DRAM battery are provided separately, the size and cost of the image forming apparatus are not greatly affected. In particular, the backup power supply for DRAM is originally intended to protect against short-time power outages, so that it can be protected for approximately one hour.

  However, when a primary battery is used for DRAM backup power supply, once the charge is emptied, backup power supply cannot be performed again. Therefore, it is preferable to use a secondary battery for DRAM backup power supply so that the backup power can be supplied any number of times. However, in order to charge the secondary battery, it is necessary to apply a voltage higher than the voltage to charge the secondary battery. Therefore, a booster circuit is provided on the FAX control board to charge the secondary battery.

  In short, since the data for storing the DRAM need only be able to be retained in the event of an instantaneous power failure, there is no problem with a retention period of about 100 hours. In addition, since devices such as image forming apparatuses are expected to undergo several power failures during the warranty period, it is preferable to use a secondary battery that can be repeatedly charged as a backup power supply for the DRAM.

  As a well-known technique related to backup power supply of such a volatile memory, in an image processing apparatus having a volatile storage means for storing image information, even when a failure occurs in a commercial power supply, the storage means is appropriately stored. A technique for preventing loss of image information is known. As an example, “image processing apparatus and image processing method” (see Patent Document 1) can be cited.

  The technique according to Patent Document 1 described above aims at backup power feeding to a RAM storing image information at the time of a power failure. Therefore, the image processing apparatus is connected to a PC (personal computer) via a USB (Universal Serial Bus) interface, and the power of the RAM is supplied by supplying USB power from the battery of the PC to the image processing apparatus. As a result, backup power is supplied to the RAM.

  However, with such a configuration, it is assumed that the image processing apparatus is connected to a PC and the PC is equipped with a secondary battery like a notebook PC so that the RAM can be backed up during a power failure. Yes. For this reason, a primary battery and a secondary battery are required in terms of configuration, and if applied to a control board for a mounting destination device, a large burden is imposed on the cost, size, and environment. The problem of ending up is not solved.

  Incidentally, the cost load indicates that the configuration requires a primary battery and a secondary battery, resulting in an increase in cost. In addition, the load on the size indicates that the area and height of the control board are limited or restricted. Furthermore, the environmental load indicates that the disposal process of the chemical-containing substance at the time of battery disposal is costly.

  The present invention has been made to solve such problems, and its technical problem is to reduce the number of batteries as much as possible while satisfying the conventional data retention period, in terms of cost, size, and environment. It is to reduce the load.

  In order to solve the above technical problem, one aspect of the present invention is a control board, which needs to be stored over the warranty period of the control unit responsible for overall control of the control board and the device on which the control board is mounted. Data stored in the first memory storing the data, the second memory storing the data transmitted or received for communication, and the first memory and the second memory to the control board A storage battery that supplies backup power while power supply is stopped, a voltage monitoring circuit that monitors the voltage of the storage battery, and a switch that switches on / off of backup power supply from the storage battery to the second memory. The monitoring circuit keeps the switch on when the battery voltage of the storage battery exceeds the lower limit value of the recommended operating voltage of the first memory and the second memory during backup power supply while the power supply is stopped. Continued backup power supply to said second memory with memory, characterized in that if less than the lower limit value to maintain the switch off to stop the backup power supply to said second memory.

  According to the present invention, with the above configuration, the battery can be reduced as much as possible while reducing the cost, size, and environmental load while satisfying the conventional data retention period. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is the schematic block diagram which showed the basic composition of the communication control board based on the Example of the control board of this invention. It is a figure which shows the hardware sequence which concerns on a device when the system state in the communication control board shown in FIG. 1 changes from the time of operation to the time of backup electric power feeding. FIG. 2 is a schematic block diagram showing a basic configuration of a communication control board according to an example in which a part of the configuration of the communication control board shown in FIG. 1 is modified. It is a figure which shows the hardware sequence which concerns on a device when the system state in the communication control board shown in FIG. 3 changes from the time of operation to the time of backup electric power feeding. FIG. 4 is a schematic block diagram showing a basic configuration of a communication control board according to another example in which a part of the configuration of the communication control board shown in FIG. 3 is modified. It is a figure which shows the hardware sequence which concerns on a device when the system state in the communication control board shown in FIG. 5 changes from the time of operation | movement to the time of backup electric power feeding. FIG. 4 is a schematic block diagram showing a basic configuration of a communication control board according to another example in which a part of the configuration of the communication control board shown in FIG. 3 is modified. It is a figure which shows the hardware sequence which concerns on a device when the system state in the communication control board shown in FIG. 7 changes from the time of operation to the time of backup electric power feeding.

  Hereinafter, examples of the control board, the control board backup power supply method, and the control board backup power supply program of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic block diagram showing a basic configuration of a communication control board 10A according to an embodiment of the control board of the present invention.

  Referring to FIG. 1, the communication control board 10 </ b> A may be applied to FAX communication of the image forming apparatus as a mounting destination. The device is mounted and power is supplied at a predetermined voltage. The communication control board 10A is equipped with a line control device 12 for connecting to the public line 11 and a communication control CPU 14 as a control unit responsible for overall control related to communication processing. The line control device 12 performs analog / digital (A / D) conversion and digital / analog (D / A) conversion. Further, a modem (MODEM) 13 that is disposed between the line control device 12 and the communication control CPU 14 and modulates transmission data and demodulates reception data is mounted on the communication control board 10A.

  Furthermore, a reset IC 15 is mounted on the communication control board 10A to monitor the power supply voltage supplied to the communication control CPU 14 and determine whether or not to perform a hard reset according to the voltage value. The reset IC 15 transmits a reset signal to the communication control CPU 14 when a hard reset is applied. In addition, various memories are mounted on the communication control board 10A. The memory includes a ROM 16 which is a non-volatile memory storing a program (software) related to the control of the communication control CPU 14 and a volatile memory for storing various data. Incidentally, the case where power is supplied at a voltage of 3.3 V can also be exemplified for the communication control board 10A here.

  The volatile memory stores the SRAM 17 as the first volatile memory storing data that needs to be stored over the warranty period of the image forming apparatus, and data transmitted or received for information processing communication. And a DRAM 18 as a second volatile memory. The SRAM 17 also stores user setting data and management data of the image forming apparatus. The DRAM 18 also stores work data as a result of control processing by the communication control CPU 14 and page data for primary file management of image processing.

  In addition, the communication control board 10A includes a storage battery (secondary battery) 19 that supplies backup power by discharging the data stored in the SRAM 17 and the DRAM 18 while the power supply is stopped, and a voltage for monitoring the voltage of the storage battery 19 The monitoring circuit 20 is mounted. Further, a booster circuit 22 for charging the storage battery 19 and a switch (SW) 21 for switching on / off of backup power supply from the storage battery 19 to the DRAM 18 are mounted on the communication control board 10A. That is, the communication control board 10 </ b> A according to the embodiment is characterized in that backup power is supplied to the SRAM 17 and the DRAM 18 using only the storage battery 19.

  When performing backup power supply while the power supply is stopped due to the discharge of the storage battery 19, the voltage monitoring circuit 20 monitors the battery voltage of the storage battery 19 and turns on / off the switch 21 (hereinafter referred to as SW control signal). ) Is output. Then, if the battery voltage exceeds 3.0 V, which is the lower limit value of the recommended operating voltage of the SRAM 17 and the DRAM 18, an SW control signal for keeping the switch 21 on is output. Thereby, the backup power supply to the SRAM 17 and the DRAM 18 is continuously performed. The voltage monitoring circuit 20 stops the backup power supply to the DRAM 18 by outputting a SW control signal for keeping the switch 21 OFF when the lower limit value is 3.0 V or less.

  FIG. 2 is a diagram illustrating a hardware sequence related to a device when the system state of the communication control board 10A described above transitions from an operation time to a backup power supply time.

  Referring to FIG. 2, if the system state of the image forming apparatus is in operation, the power supply voltage supplied to the communication control board 10 </ b> A is 3.3 V, and the output voltage of the booster circuit 22 can charge the storage battery 19. It is 3.4V. Further, the battery voltage of the storage battery 19 at that time is 3.3 V, and the SW control signal from the voltage monitoring circuit 20 is in a high state in which the switch 21 is kept on. Furthermore, the power supply voltages of the DRAM 18 and the SRAM 17 are both 3.3V.

  When the system state changes from the time of operation to the time of backup power supply, the DRAM 18 and the SRAM 17 are disconnected from the power supply for operation and switched from the power supply voltage of 3.3 V to the backup power supply by discharging the storage battery 19. In this state, the SW control signal from the voltage monitoring circuit 20 is maintained in a high state in which the switch 21 is kept on. Thereafter, when the storage battery 19 is consumed and the battery voltage starts to drop and falls below 3.0 V, the SW control signal from the voltage monitoring circuit 20 is in a low state that keeps the switch 21 off. As a result, the backup power supply to the DRAM 18 is cut off, and the backup power supply to only the SRAM 17 is performed.

  Incidentally, the power supply voltage required to hold data in the DRAM 18 is 3.0V, but the power supply voltage required to hold data in the SRAM 17 is 2.0V. The storage battery 19 used for the backup power supply of the SRAM 17 and the DRAM 18 depends on the type of the battery, but even if it is a 100 mAh type, the battery voltage can generally be maintained at 3.0 V for 200 hours or more with 200 uA discharge. . That is, since the battery voltage can be maintained at 3.0 V until 40 mAh or more is discharged, the data held in the DRAM 18 can be continuously held for 6 hours or more. The basis for the calculation here is that, in the case of a button battery of about 600 mAh, the current consumption for data retention is only about 100 hours. / 6 = according to the calculation result of about 6.7 hours. Since the data held in the DRAM 18 may be protected for about one hour, sufficient protection is achieved.

  Further, the storage battery 19 continuously performs backup power supply only to the SRAM 17 until the warranty period is reached. Here, the battery remaining amount of the storage battery 19 after stopping the backup power supply to the DRAM 18 is 60 mAh, but the power consumption of the SRAM 17 is 1 uA. For this reason, backup power supply for five years or more is possible for the SRAM 17, and the warranty period can be sufficiently satisfied.

  As described above, according to the communication control board 10A, while satisfying the conventional data retention period, the above-described cost, size, and environment are reduced by reducing the battery as much as possible without requiring a primary battery. The load can be reduced. In short, the communication control board 10A is characterized in that it has a function of making the backup power supply time to the DRAM 18 as long as possible and lengthening the time until the data transmitted or received for information processing disappears.

  FIG. 3 is a schematic block diagram showing a basic configuration of a communication control board 10B according to an example in which a part of the configuration of the communication control board 10A described above is modified.

  Referring to FIG. 3, the communication control board 10B is compared with the communication control board 10A, as a device, a microcomputer (microcomputer) 23 for inputting a reset signal from the reset IC 15, a logical product circuit (AND circuit) 24, Is implemented separately. The microcomputer 23 has a counting function of counting the backup power supply backup time by the storage battery 19 and the 3.3 V power supply stop period. Further, the microcomputer 23 detects the timing at which the count value of the power supply stop period reaches the count value of the backup time corresponding to the time required for storing data in the DRAM 18 by the count function. Then, at the time of detection, the SW control signal 3 is outputted to stop backup power feeding to the DRAM 18.

  The AND circuit 24 inputs the SW control signal 3 output from the microcomputer 23 and the SW control signal 2 output from the voltage monitoring circuit 20, and turns on or off the switch 21 when any of them is input. The SW control signal 1 to be output is output. The switch 21 is turned off when the arrival of the count value is detected or when the battery voltage of the storage battery 19 becomes equal to or lower than the lower limit value 3.0V of the recommended operating voltage of the SRAM 17 and the DRAM 18 by the voltage monitoring circuit 20.

  In the communication control board 10B, when the microcomputer 23 detects a state in which the power supply voltage of 3.3V is turned off by a reset signal from the reset IC 15, the microcomputer 23 starts counting the off time. The count threshold value defines the data protection period of the DRAM 18 as 1 hour here. In this case, when the count of the off time reaches 1 hour, the microcomputer 23 outputs the SW control signal 3 to the AND circuit 24 in order to stop the backup power supply to the DRAM 18. As a result, the AND circuit 24 outputs the SW control signal 1 for keeping the switch 21 OFF, and the backup power supply to the DRAM 18 is stopped. Here, for example, the SRAM 17 is energized longer than when the voltage monitoring circuit 20 simply outputs the SW control signal 2 to the AND circuit 24 to stop the backup power supply to the DRAM 18 and continue the backup power supply to the SRAM 17. Can do. As a result, the SRAM 17 data can be stored and maintained beyond the guarantee period.

  FIG. 4 is a diagram illustrating a hardware sequence related to the device when the system state in the communication control board 10B changes from the operation time to the backup power supply time.

  Referring to FIG. 4 again, if the system state of the image forming apparatus is in operation, the power supply voltage supplied to the communication control board 10B is 3.3V, and the output voltage of the booster circuit 22 charges the storage battery 19. It is possible 3.4V. Further, the battery voltage of the storage battery 19 at that time is 3.3 V, and the SW control signal 2 from the voltage monitoring circuit 20 and the SW control signal 3 from the microcomputer 23 are in a high state for keeping the switch 21 on. . As a result, the SW control signal 1 output from the AND circuit 24 is in the High state at the same timing as the SW control signal 3. Furthermore, the power supply voltages of the DRAM 18 and the SRAM 17 are both 3.3V.

  When the system state changes from the time of operation to the time of backup power supply, the DRAM 18 and the SRAM 17 are disconnected from the power supply for operation and switched from the power supply voltage of 3.3 V to the backup power supply by discharging the storage battery 19. At this time, the microcomputer 23 starts counting the backup power backup time by the storage battery 19 and the 3.3 V power supply voltage cut-off time by the counting function. In this state, the SW control signal 2 from the voltage monitoring circuit 20 is maintained in a High state in which the switch 21 is kept on.

  Thereafter, when the storage battery 19 is consumed and the battery voltage starts to drop and falls below 3.0 V, the SW control signal 2 from the voltage monitoring circuit 20 is in a low state that keeps the switch 21 off. However, here, prior to that, it is assumed that the microcomputer 23 detects the timing at which the count value of the power supply stop period reaches the count value of the backup time corresponding to the time required for storing data in the DRAM 18. . In such a case, the microcomputer 23 outputs the SW control signal 3 in the Low state that keeps the switch 21 off when the count threshold is reached. In response to this, the AND circuit 24 outputs the SW control signal 1 in the Low state that keeps the switch 21 off. For this reason, the switch 21 is turned off, the backup power supply to the DRAM 18 is cut off, and the backup power supply to only the SRAM 17 is performed.

  As a result, in the communication control board 10B, the timing at which the backup power supply to the DRAM 18 is cut off is earlier than in the case of the communication control board 10A, and accordingly, the backup power supply can be performed from the storage battery 19 to the SRAM 17 longer. . Further, the storage battery 19 continuously performs backup power supply only to the SRAM 17 until the warranty period is reached.

  By the way, according to the communication control board 10B, the backup power supply to the SRAM 17 can be continued until the warranty period is exceeded. This is limited to the case where the microcomputer 23 is operated with the same power supply voltage as that of the SRAM 17. However, the microcomputer 23 generally has a power of about 1 uA in the halt mode for stopping the execution of the function-equipped instruction. Therefore, when the power supply voltage supplied to the communication control board 10B is off, the microcomputer 23 may be backed up and operated by discharging from the storage battery 19. In such a case, since the data storage time of the SRAM 17 or DRAM 18 is hardly affected, it is possible to adopt such a configuration.

  In any case, in the communication control board 10B, while satisfying the conventional data retention period, the battery is reduced as much as possible without the need for a primary battery, thereby reducing the above-mentioned cost, size, and environmental load. Can be made. In short, the communication control board 10B is characterized in that the backup power supply time to the DRAM 18 is shortened as much as possible, and the backup power supply time to the SRAM 17 is increased accordingly.

  FIG. 5 is a schematic block diagram showing a basic configuration of a communication control board 10C according to another example in which a part of the configuration of the communication control board 10B described above is modified.

  Referring to FIG. 5, the communication control board 10 </ b> C is a device between the ROM 25 storing the warranty period and the first booster circuit 22 a similar to the booster circuit 22 and the switch 21, as compared with the communication control board 10 </ b> B. An intervening second booster circuit 22b is separately mounted. However, the ROM 25 here may be regarded as being built in the microcomputer 23. Further, the second booster circuit 22b plays a role of boosting the backup power supply by the storage battery 19 and maintaining the SRAM 17 and the DRAM 18 at the recommended operating voltage until the remaining charge of the storage battery 19 becomes zero.

  Further, the microcomputer 23 here counts the operating time indicating the time from when the image forming apparatus starts energizing for the first time to the present by the counting function. In addition, the microcomputer 23 has a calculation function for calculating the required time of data to be stored in the SRAM 17 based on the difference time obtained by subtracting the operation time from the total time corresponding to the guarantee period. Therefore, the microcomputer 23 detects the timing at which the count value by the count function reaches the stop period as a result of calculating the time for stopping the backup power supply to the DRAM 18 based on the required time by the calculation function. Then, the microcomputer 23 stops the backup power supply to the DRAM 18 at the detection time.

  That is, the microcomputer 23 calculates the remaining necessary time that must be guaranteed based on the difference time obtained by subtracting the operation time from the total time corresponding to the warranty period. Further, a stop period for keeping the switch 21 off, which is a time for stopping the backup power supply to the DRAM 18, is determined from the necessary time and the consumption current of the SRAM 17. The switch 21 is turned off during the determined stop period or when the battery voltage of the storage battery 19 becomes equal to or lower than the lower limit value 3.0 V of the recommended operating voltage of the SRAM 17 and DRAM 18 by the voltage monitoring circuit 20.

  FIG. 6 is a diagram illustrating a hardware sequence related to the device when the system state in the communication control board 10C changes from the operation time to the backup power supply time.

  Referring to FIG. 6 again, if the system state of the image forming apparatus is in operation, the power supply voltage supplied to the communication control board 10C is 3.3V, and the output voltage of the first booster circuit 22a is the storage battery. It is 3.4V that can charge 19. The output voltage of the second booster circuit 22b is also 3.4 V that can maintain the voltage drop caused by the discharge of the storage battery 19 in a boosted manner. Further, the battery voltage of the storage battery 19 at that time is 3.3 V, and the SW control signal 2 from the voltage monitoring circuit 20 and the SW control signal 3 from the microcomputer 23 are in a high state for keeping the switch 21 on. . As a result, the SW control signal 1 output from the AND circuit 24 is in the High state at the same timing as the SW control signal 3. Furthermore, the power supply voltages of the DRAM 18 and the SRAM 17 are both 3.3V.

  When the system state changes from the time of operation to the time of backup power supply, the DRAM 18 and the SRAM 17 are disconnected from the operation power supply and switched from the power supply voltage of 3.3 V to the backup power supply by the storage battery 19. At this time, the microcomputer 23 starts counting the operation time, the backup power supply backup time by the storage battery 19, and the 3.3V power supply voltage cut-off time by the count function. In this state, the SW control signal 2 from the voltage monitoring circuit 20 is maintained in a High state in which the switch 21 is kept on.

  On the other hand, the output voltage of the second booster circuit 22b is maintained at 3.3V by receiving backup power supply by discharging from the storage battery 19. For this reason, the power supply voltages of the DRAM 18 and the SRAM 17 are different from the waveform in the case of the communication control board 10B shown in FIG. That is, the second booster circuit 22b boosts the SRAM 17 and the DRAM 18 with respect to the battery voltage output of the storage battery 19 so as to be within the recommended operating voltage range. As a result, the battery voltage can be maintained within the recommended operating voltage range until the remaining charge of the storage battery 19 becomes zero.

  Thereafter, when the storage battery 19 is consumed and the battery voltage starts to drop and falls below 3.0 V, the SW control signal 2 from the voltage monitoring circuit 20 is in a low state that keeps the switch 21 off. However, here, prior to that, the microcomputer 23 calculates the required time of data to be stored in the SRAM 17 based on the difference time obtained by subtracting the operation time from the total time corresponding to the guarantee period by the calculation function. Then, it is assumed that the microcomputer 23 detects the timing at which the count value by the count function reaches the stop period as a result of calculating the time for stopping the backup power supply to the DRAM 18 based on the required time. In such a case, the microcomputer 23 outputs the SW control signal 3 in the low state that keeps the switch 21 off. In response to this, the AND circuit 24 outputs the SW control signal 1 in the Low state that keeps the switch 21 off. For this reason, the switch 21 is turned off, the backup power supply to the DRAM 18 is cut off, and the backup power supply to only the SRAM 17 is performed. Here, as compared with the case of the communication control board 10B, the power supply voltage of the DRAM 18 is not lowered and the power supply is stopped in a state of being maintained at 3.3V.

  Further, the storage battery 19 continuously performs backup power supply only to the SRAM 17 until the warranty period is reached. Again, the backup power supply from the storage battery 19 is boosted by the second booster circuit 22b. For this reason, the power supply voltage of the SRAM 17 is maintained at 3.3V without being lowered, and at the time when the guarantee period is reached, it begins to drop with the output voltage of the second booster circuit 22b and eventually becomes 0V.

  As a result, also in the communication control board 10C, the timing at which the backup power supply to the DRAM 18 is cut off is earlier than in the case of the communication control board 10A. However, although this timing is illustrated as being similar to that in the case of the communication control board 10B, it can be delayed. Further, backup power can be supplied from the storage battery 19 to the SRAM 17 with a more stable power supply voltage until the guarantee period is reached than in the case of the communication control board 10B. As a result, even in the communication control board 10C, while satisfying the conventional data retention period, the battery is reduced as much as possible without the need for a primary battery, thereby reducing the above-mentioned cost, size, and environmental load. be able to.

  FIG. 7 is a schematic block diagram showing a basic configuration of a communication control board 10D according to another example in which a part of the configuration of the communication control board 10B described above is modified.

  Referring to FIG. 7, the communication control board 10 </ b> D has an A / D (analog / digital) converter as a microcomputer instead of mounting the voltage monitoring circuit 20 and the AND circuit 24 as a device, compared to the communication control board 10 </ b> B. 23. This A / D converter has a function equivalent to that of the voltage monitoring circuit 20, monitors the battery voltage of the storage battery 19, and switches the switch 21 when the battery voltage is detected to be below the lower limit value of the recommended operating voltage of the SRAM 17 and DRAM 18. The SW control signal 3 that is kept off is output.

  FIG. 8 is a diagram illustrating a hardware sequence related to a device when the system state of the communication control board 10D described above transitions from an operation time to a backup power supply time.

  Referring to FIG. 8, if the system state of the image forming apparatus is in operation, the power supply voltage supplied to the communication control board 10D is 3.3V, and the output voltage of the booster circuit 22 can charge the storage battery 19. It is 3.4V. Further, the battery voltage of the storage battery 19 at that time is 3.3 V, and the SW control signal 3 from the voltage monitoring circuit 20 is in a High state in which the switch 21 is kept on. Furthermore, the power supply voltages of the DRAM 18 and the SRAM 17 are both 3.3V.

  When the system state changes from the time of operation to the time of backup power supply, the DRAM 18 and the SRAM 17 are disconnected from the power supply for operation and switched from the power supply voltage of 3.3 V to the backup power supply by discharging the storage battery 19. In this state, the SW control signal 3 from the voltage monitoring circuit 20 is maintained in the High state in which the switch 21 is kept on, but the output voltage of the booster circuit 22 decreases with the power supply voltage of 3.3V and eventually becomes 0V. become. After that, when the storage battery 19 is consumed and the battery voltage starts to drop and falls below 3.0V, the SW control signal 3 from the voltage monitoring circuit 20 is in a low state that keeps the switch 21 off. As a result, the backup power supply to the DRAM 18 is cut off, and the backup power supply to only the SRAM 17 is performed. Further, the storage battery 19 continuously performs backup power supply only to the SRAM 17 until the warranty period is reached. That is, the hardware sequence of the communication control board 10D shown in FIG. 8 has the same form as the hardware sequence of the communication control board 10A shown in FIG.

  Even in this communication control board 10D, it is possible to reduce the cost, size, and environmental load described above by reducing the battery as much as possible without requiring a primary battery while satisfying the conventional data retention period. it can.

  By the way, also in the communication control board 10D, it is possible to give the microcomputer 23 the same function as the communication control board 10B and the communication control board 10C. In the former, the timing at which the count value of the power supply stop period reaches the count value of the backup time corresponding to the time required for storing data in the DRAM 18 may be detected by the count function. At this detection time, the SW control signal 3 for stopping the backup power supply to the DRAM 18 is output. Thereby, the backup power supply to the DRAM 18 is stopped.

  The latter is based on the premise that the microcomputer 23 further includes a storage unit for storing the warranty period of the image forming apparatus. On this basis, the operation time is counted by the count function, and a calculation function for calculating the required time of the data to be stored in the SRAM 17 based on the difference time obtained by subtracting the operation time from the total time corresponding to the guarantee period may be provided. . Therefore, the microcomputer 23 outputs the SW control signal 3 for stopping the backup power supply to the DRAM 18 when the A / D converter detects that the battery voltage of the storage battery 19 is below the lower limit value of the recommended operating voltage of the SRAM 17 and the DRAM 18. . Alternatively, the microcomputer 23 detects the timing at which the count value by the count function reaches the stop period as a result of calculating the time for stopping the backup power supply to the DRAM 18 based on the required time by the calculation function. At this detection time, the SW control signal 3 for stopping the backup power supply to the DRAM 18 is output. Thereby, the backup power supply to the DRAM 18 is stopped.

  By the way, the technology related to the communication control board 10A described above can be restated as a backup power supply method for the control board. In this control board backup power supply method, it is assumed that the communication control CPU 14, SRAM 17, DRAM 18, storage battery 19, voltage monitoring circuit 20, and switch 21 are mounted on the communication control board 10A. Therefore, a backup power supply step executed by the voltage monitoring circuit 20 is provided. In the backup power supply step, the switch 21 is kept on by the voltage monitoring circuit 20 when the battery voltage of the storage battery 19 exceeds the lower limit value of the recommended operating voltage of the SRAM 17 and DRAM 18 during the backup power supply while the power supply is stopped. As a result, the backup power supply to the DRAM 18 together with the SRAM 17 is continued. In the backup power supply step, the voltage monitoring circuit 20 keeps the switch 21 off and stops the backup power supply to the DRAM 18 if it is below the lower limit value of the recommended operating voltage. Incidentally, this backup power supply step can be constructed as a control board backup power supply program to be executed by a computer.

  It should be noted that the present invention is not limited to the gist described in the embodiments in the embodiment described above, and various modifications are possible without departing from the technical spirit thereof, and the technical ideas described in the claims are included. All the technical matters involved are the subject of the present invention. The above-described embodiments show preferred examples, but those skilled in the art can realize various modifications from the disclosed contents, and these are described in the appended claims. Included in the technical scope.

10A, 10B, 10C, 10D Communication control board 11 Public line 12 Line control device 13 Modem (MODEM)
14 CPU for communication control
15 Reset IC
16 ROM
17 SRAM
18 DRAM
19 Storage battery (secondary battery)
20 Voltage monitoring circuit 21 Switch (SW)
22, 22a, 22b Booster circuit 23 Microcomputer
24 AND circuit (AND circuit)

JP 2006-166044 A

Claims (9)

A control board,
A control unit responsible for overall control of the control board, a first memory storing data that needs to be stored over the warranty period of the device on which the control board is mounted, and transmitted or received for communication A second memory in which data is stored, a storage battery that supplies backup power to the data stored in the first memory and the second memory while power supply to the control board is stopped, and A voltage monitoring circuit for monitoring the voltage of the storage battery, and a switch for switching on / off of backup power supply from the storage battery to the second memory,
The voltage monitoring circuit turns on the switch if the battery voltage of the storage battery exceeds the lower limit value of the recommended operating voltage of the first memory and the second memory during backup power supply when the power supply is stopped. The backup power supply to the second memory together with the first memory is continued, and if it is equal to or lower than the lower limit value, the switch is kept off and the backup power supply to the second memory is stopped. A control board characterized by that. The control board according to claim 1,
A microcomputer having a count function for counting the backup power backup time and the power supply stop period,
The microcomputer detects a timing at which the count value of the power supply stop period reaches a count value of the backup time corresponding to a time necessary for storing the data in the second memory by the count function. And stopping the backup power supply to the second memory. The control board according to claim 2,
A storage unit for storing a warranty period of the device;
The microcomputer counts an operating time indicating a time from when the device starts energizing for the first time to the present by the counting function, and based on a difference time obtained by subtracting the operating time from the total time corresponding to the guarantee period. And having a calculation function for calculating the time required for the data to be stored in the first memory,
Further, the microcomputer detects the timing at which the count value by the count function reaches the stop period as a result of calculating the time to stop the backup power supply to the second memory based on the required time by the calculation function. A control board characterized by stopping backup power feeding to the second memory at the time of being performed. The control board according to claim 3,
A control board comprising a booster circuit that boosts backup power supply by the storage battery and maintains the first memory and the second memory at a recommended operating voltage until a remaining charge of the storage battery becomes zero. The control board according to claim 2,
The control board according to claim 1, wherein the voltage monitoring circuit is an A / D converter having an analog / digital conversion function built in the microcomputer. The control board according to claim 5,
In the microcomputer, the battery voltage of the storage battery is detected by the A / D converter as being lower than or equal to a lower limit value of the recommended operating voltage of the first memory and the second memory, or the power supply is performed by the counting function. The backup power supply to the second memory is stopped when it is detected that the count value of the stop period reaches the backup time count value corresponding to the time required to store the data in the second memory. A control board. The control board according to claim 6,
A storage unit for storing a warranty period of the device;
The microcomputer counts an operation time indicating a time from when the device starts energization for the first time to the present by the count function, and subtracts the operation time from a total time corresponding to the warranty period. A calculation function for calculating a time required for the data to be stored in the first memory;
Further, the microcomputer detects that the voltage of the storage battery is below the lower limit value of the recommended operating voltage of the first memory and the second memory by the A / D converter, or that the calculation function requires the microcomputer. The backup power supply to the second memory is detected when the timing at which the count value by the count function reaches the stop period as a result of calculating the time to stop the backup power supply to the second memory based on the time. A control board characterized by stopping. A backup power supply method for a control board,
A control unit responsible for overall control of the control board, a first memory storing data that needs to be stored over the warranty period of the device on which the control board is mounted, and data transmitted or received for communication A storage battery that supplies backup power to the data stored in the first memory and the second memory while power supply to the control board is stopped; and Under the condition that a voltage monitoring circuit for monitoring the voltage of the storage battery and a switch for switching on / off backup power feeding from the storage battery to the second memory are mounted on the control board,
When the backup voltage is supplied by the voltage monitoring circuit while the power supply is stopped, the switch is turned on if the battery voltage of the storage battery exceeds the lower limit value of the recommended operating voltage of the first memory and the second memory. The backup power supply to the second memory is continued together with the first memory, and the switch is turned off and the backup power supply to the second memory is stopped if the lower limit value is not reached. A backup power supply method for a control board, comprising a backup power supply step. A backup power supply program for a control board,
A control unit responsible for overall control of the control board, a first memory storing data that needs to be stored over the warranty period of the device on which the control board is mounted, and data transmitted or received for communication A storage battery that supplies backup power to the data stored in the first memory and the second memory while power supply to the control board is stopped; and Under the condition that a voltage monitoring circuit for monitoring the voltage of the storage battery and a switch for switching on / off backup power feeding from the storage battery to the second memory are mounted on the control board,
During backup power supply while the power supply is stopped, if the battery voltage of the storage battery exceeds the lower limit value of the recommended operating voltage of the first memory and the second memory, the switch is kept on and the second power supply is stopped. A backup power supply step for continuing backup power supply to the second memory together with the memory of 1 and keeping the switch off and stopping the backup power supply to the second memory if it is below the lower limit value is performed on the computer Backup power supply program for control board to be executed.