JP2019040030A - Optical logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-bit optical logic circuit capable of realizing high-speed logic operation. An 8-bit input AND circuit is a three-input, one-output optical logic element 1-1 to 1-7 connected in cascade. The optical logic elements 1-1 to 1-4 of the first stage input two signal lights of amplitude bits and bias light in which values of 0 and 1 are assigned to different amplitudes. The optical logic elements 1-5 to 1-7 other than the first stage input the output light and the bias light of the two immediately preceding optical logic elements. The output light obtained by merging with one optical logic element 1-7 in the final stage is used as the calculation result. [Selection diagram] Fig. 1

Description

  The present invention relates to an optical logic circuit that performs logical operations in an optical circuit.

  An optical logic element is one of important devices for realizing high-speed optical computation without RC delay, and has been studied for many years by many institutions. Many of them use the nonlinear optical effect (see Non-Patent Document 1). The non-linear optical effect is indispensable for securing the binary contrast of the output bit signal (ratio of the absolute intensity at the time of “0” output and the absolute intensity at the time of “1” output). However, the use of the nonlinear optical effect has the following problems.

(I) A large input intensity (or intensity density) of the signal is required.
(II) Large insertion loss.
(III) The performance changes depending on the input intensity.
(IV) The structure is complex and not easy to manufacture.

  Although the problem (I) can be compensated to some extent by the device structure, it is difficult to fundamentally solve any problem. Therefore, even in the present situation, the application of nonlinear optical logic elements is remarkably limited from the viewpoint of cascadability (the number of optical logic elements that can be connected in cascade) and power consumption. Even if the restrictions on cascadeability and power consumption are satisfied, it is difficult to obtain a binary contrast exceeding 10 dB and a low insertion loss at the same time.

  On the other hand, linear optical logic elements based on linear optics have also been proposed in order to avoid the problem of optical logic elements using the above-described nonlinear optical effect. The advantage of linear optics is that the power consumption can be greatly reduced because the performance does not depend on the input intensity and can be operated at a low input intensity (level of several photons if possible). As an operation principle, one based on linear interference using the phase of propagating light has been proposed.

  When an optical logic element sensitive to the above phase change is incorporated in a free space optical system or fiber optical system, the relative phase between each optical signal is temporally affected by the spatial vibration or twist of each optical element or fiber. Therefore, it cannot basically operate without a feedback control mechanism.

However, in recent years, the progress of nanophotonics technology has made it possible to some extent allow on-chip integration of laser light sources, photodetectors, phase shifters and 1 × 1 switches or 2 × 2 switches that can be electrically controlled. By such on-chip integration of devices, the relative position of each device is fixed, so that the problem of phase fluctuation seen in the free space optical system is almost solved.
However, since the on-chip linear optical logic device itself is under development, the implementation of a specific function and a specific circuit configuration using a combination of the optical logic device and another optical device have not been sufficiently studied.

  As an application example of an optical AND (logical sum) element, there is a match search (pattern match) circuit that determines whether an input bit string matches a specific arrangement. In the case of this application, it is necessary to perform matching determination of a plurality of bits as fast as possible (low delay). As an application destination of the pattern match circuit, for example, there is a switch router.

P. Singh et al., “All-Optical Logic Gates: Designs, Classification, and Comparison”, Advances in Optical Technologies, Volume 2014, Article ID 275083, 2014

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a multi-bit optical logic circuit capable of realizing a high-speed logic operation.

The optical logic circuit of the present invention includes a plurality of three-input one-output optical logic elements that receive two signal lights and a bias light, and a two-input one-output plurality of optical logic elements that receive two signal lights as inputs. And at least one kind of optical logic elements of a plurality of two-input one-output optical logic elements that receive one signal light and a bias light as input, and are joined to one final optical logic element. The obtained output light is used as a calculation result.
In the optical logic circuit of the present invention, a plurality of optical logic elements with three inputs and one output are connected in cascade, and the first-stage optical logic element has a signal light 2 of amplitude bits in which values of 0 and 1 are assigned to different amplitudes. The optical logic elements other than the first stage are obtained by inputting the output light of the immediately preceding two optical logic elements and the bias light and merging with one of the last optical logic elements. The output light thus obtained is used as a calculation result.

Further, the optical logic circuit of the present invention includes a plurality of first input / output three-input optical logic elements arranged at the first stage, and a second input / output second arranged at positions excluding the first stage and the final stage. A phase bit in which an optical logic element and a third optical logic element with three inputs and one output arranged at the last stage are connected in cascade, and the values of 0 and 1 are assigned to different phases. The signal light and the bias light are input, and the second optical logic element inputs the output light of the immediately preceding two first optical logic elements or the output light of the immediately preceding two second optical logic elements. The third optical logic element receives the output light of the immediately preceding two second optical logic elements and the bias light, and combines the output light obtained by combining with the third optical logic element. The result is an operation result.
The optical logic circuit of the present invention includes a plurality of first optical logic elements having two inputs and one output arranged in the first stage, and a second optical logic element having two inputs and one output arranged in the second stage. Cascade connection of the third optical logic element with two inputs and one output arranged in the place excluding the first stage, the second stage and the final stage, and the fourth optical logic element with three inputs and one output arranged in the final stage The first optical logic element receives two phase-bit signal lights with values of 0 and 1 assigned to different phases, and the second optical logic element is the first optical logic element of the first optical logic element. One output light and bias light are input, and the third optical logic element receives the output light of the two preceding second optical logic elements or the output light of the two immediately preceding third optical logic elements. The fourth optical logic element receives the output light of the immediately preceding two third optical logic elements and the bias light as inputs, and the fourth optical theory. It is characterized in that the output light obtained by merging the device and the operation result.

In addition, one configuration example of the optical logic circuit of the present invention includes a first phase shifter capable of adjusting the phase of one of two signal lights input to each optical logic element, and input to each optical logic element. And a second phase shifter capable of adjusting the phase of the bias light, and an intensity modulator capable of adjusting the intensity of the bias light input to each optical logic element.
Also, one configuration example of the optical logic circuit of the present invention includes a first intensity modulator capable of adjusting the intensity of two signal lights input to the first optical logic element, and the second and third A first phase shifter capable of adjusting the phase of one of the two signal lights input to the optical logic element, and an intensity of the bias light input to the first and third optical logic elements can be adjusted. The apparatus further comprises a second intensity modulator and a second phase shifter capable of adjusting the phase of the bias light input to the third optical logic element.
Also, in one configuration example of the optical logic circuit of the present invention, a photodetector for photoelectrically converting the output light of the optical logic element arranged at the final stage, and an analog electric signal output from the photodetector are thresholded. It further comprises a threshold value processor for performing value processing and converting it into a digital electric signal.
In addition, one configuration example of the optical logic circuit of the present invention is characterized by further including a light source capable of individually setting a plurality of the intensity of the bias light.

  According to the present invention, a plurality of three-input one-output optical logic elements that receive two signal lights and a bias light, a two-input one-output plurality of optical logic elements that receive two signal lights, It is obtained by cascading at least one type of optical logic elements among a plurality of two-input one-output optical logic elements that receive one signal light and a bias light, and join to one optical logic element at the final stage. By using the output light as an operation result, it is possible to realize a high speed logic operation.

FIG. 1 is a block diagram showing a configuration example of an 8-bit input AND circuit according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration example of an 8-bit input AND circuit according to the second embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of an 8-bit input AND circuit according to the third embodiment of the present invention. FIG. 4 is a block diagram showing a configuration example of an 8-bit input AND circuit according to the fourth exemplary embodiment of the present invention. FIG. 5 is a block diagram showing a configuration example of an 8-bit input AND circuit according to the fifth exemplary embodiment of the present invention. FIG. 6 is a perspective view showing the configuration of an optical logic element according to the sixth embodiment of the present invention. FIG. 7 is a plan view showing the configuration of an optical logic element according to the sixth embodiment of the present invention. FIG. 8 is a perspective view showing the configuration of an optical logic element according to the seventh embodiment of the present invention. FIG. 9 is a plan view showing the configuration of an optical logic element according to the seventh embodiment of the present invention. FIG. 10 is a perspective view showing the configuration of an optical logic element according to the eighth embodiment of the present invention. FIG. 11 is a plan view showing the configuration of an optical logic element according to the eighth embodiment of the present invention.

[First embodiment]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an 8-bit input AND circuit (optical logic circuit) according to the first embodiment of the present invention. The 8-bit input AND circuit is a three-input one-output optical logic element 1-1 to 1-7 that performs an AND operation on two signal lights with two signal lights and one bias light as inputs, and for generating signal lights. A light source 2 that outputs a continuous light and a bias light, and an intensity modulator 3-1 that generates signal light by intensity-modulating the continuous light for signal light generation according to each bit of the 8-bit input digital electrical signal. 3-8, a photodetector 4 that photoelectrically converts the output light of the optical logic element 1-7, a comparator that performs threshold processing on the analog electrical signal output from the photodetector 4 and converts it into a digital electrical signal, It comprises a threshold processing unit 5 such as a sense amplifier and optical waveguides 7-1 to 7-8, 8-1 to 8-7, 9-1 to 9-6. This 8-bit input AND circuit is integrated on a substrate made of a dielectric material.

  In FIG. 1, 6A and 6B are signal light input ports of the optical logic elements 1-1 to 1-7, 6C is an optical output port of the optical logic elements 1-1 to 1-7, and 6D is an optical logic element 1-1 to 1-7. 1-7 is a bias light input port.

  In the 8-bit input AND circuit of this embodiment, optical logic elements 1-1 to 1-7 that input signal lights having values of “0” and “1” assigned to different amplitudes are cascaded hierarchically. Is. Specifically, the optical outputs of the optical logic elements 1-1 and 1-2 are input to the optical logic element 1-5, and the optical outputs of the optical logic elements 1-3 and 1-4 are input to the optical logic element 1-6. The optical outputs of the optical logic elements 1-5 and 1-6 are input to the optical logic element 1-7. The number of stages is N = 3.

  The optical waveguides 7-1 and 7-2 are connected to the signal light input ports 6A and 6B of the optical logic element 1-1, and the optical waveguides 7-3 and 7-4 are the signal light input ports 6A of the optical logic element 1-2. , 6B. The optical waveguides 7-5 and 7-6 are connected to the signal light input ports 6A and 6B of the optical logic element 1-3, and the optical waveguides 7-7 and 7-8 are the signal light input ports 6A of the optical logic element 1-4. , 6B. The optical waveguides 8-1, 8-3, 8-5, and 8-7 are connected to the bias light input ports 6D of the optical logic elements 1-1 to 1-4.

  The optical output port 6C of the optical logic element 1-1 and the signal light input port 6A of the optical logic element 1-5 are connected by an optical waveguide 9-1, and the optical output port 6C of the optical logic element 1-2 and the light are connected. The signal light input port 6B of the logic element 1-5 is connected by an optical waveguide 9-2. The optical output port 6C of the optical logic element 1-3 and the signal light input port 6A of the optical logic element 1-6 are connected by an optical waveguide 9-3, and the optical output port 6C of the optical logic element 1-4. And the signal light input port 6B of the optical logic element 1-6 are connected by an optical waveguide 9-4. The optical waveguides 8-2 and 8-6 are connected to the bias light input ports 6D of the optical logic elements 1-5 and 1-6.

  Further, the optical output port 6C of the optical logic element 1-5 and the signal light input port 6A of the optical logic element 1-7 are connected by an optical waveguide 9-5, and the optical output port 6C of the optical logic element 1-6. And the signal light input port 6B of the optical logic element 1-7 are connected by an optical waveguide 9-6. The optical waveguide 8-4 is connected to the bias light input port 6D of the optical logic element 1-7.

  The light source 2 inputs continuous light having an intensity corresponding to the value “1” to the optical waveguides 7-1 to 7-8. At this time, the light source 2 inputs in-phase continuous light to all the optical waveguides 7-1 to 7-8. The optical waveguides 7-1 to 7-8 are provided with intensity modulators 3-1 to 3-8 that receive respective bits of an 8-bit input digital electric signal. In this manner, eight signal lights having amplitudes corresponding to the corresponding bits of the input digital electrical signal can be generated. Hereinafter, the signal light generated by the intensity modulators 3-1 to 3-8 and having an intensity of 0 or 1 and having a fixed phase is referred to as an amplitude bit.

  The amplitude bits generated by the intensity modulators 3-1 and 3-2 are input to the signal light input ports 6A and 6B of the optical logic element 1-1, and the amplitude generated by the intensity modulators 3-3 and 3-4. The bits are input to the signal light input ports 6A and 6B of the optical logic element 1-2. The amplitude bits generated by the intensity modulators 3-5 and 3-6 are input to the signal light input ports 6A and 6B of the optical logic element 1-3, and the amplitude generated by the intensity modulators 3-7 and 3-8. The bits are input to the signal light input ports 6A and 6B of the optical logic element 1-4.

  The light source 2 uses the continuous light having the same intensity and the same wavelength as the continuous light for signal light generation input to the optical waveguides 7-1 to 7-8 as bias light, and the optical waveguides 8-1, 8-3, 8- 5 and 8-7, continuous light having the same wavelength and 1/3 intensity as the continuous light for signal light generation is input as bias light to the optical waveguides 8-2 and 8-6, and is used for signal light generation. Continuous light having the same wavelength as that of continuous light and having an intensity of 1/9 is input as bias light to the optical waveguide 8-4. At this time, the light source 2 sets the phase of these bias lights to the opposite phase to the continuous light for signal light.

  The bias light propagated through the optical waveguides 8-1, 8-3, 8-5, and 8-7 is input to the bias light input ports 6D of the optical logic elements 1-1 to 1-4. The bias light propagated through the optical waveguides 8-2 and 8-6 is input to the bias light input port 6D of the optical logic elements 1-5 and 1-6. The bias light propagated through the optical waveguide 8-4 is input to the bias light input port 6D of the optical logic element 1-7.

  Each of the optical logic elements 1-1 to 1-7 performs an AND operation on the amplitude bits. That is, each of the optical logic elements 1-1 to 1-7 outputs the amplitude bit “1” to the optical output port 6 C when both the signal light input ports 6 A and 6 B have the amplitude bit “1”, and the signal light When at least one of the inputs of the input ports 6A and 6B is the amplitude bit “0”, the amplitude bit “0” is output to the optical output port 6C.

In each of the optical logic elements 1-1 to 1-7, the confluence ratio of the phase bit of the signal light input port 6A, the bias light of the bias light input port 6D, and the phase bit of the signal light input port 6B is 1: 1: 1. In this case, the relative light intensity P _bias ^— _n of the bias light input to the bias light input port 6D of the n-th stage (n = 1 to N) optical logic element is optimally 3 ^{− (n−1)} . Therefore, in the above example, the relative light intensity of the bias light input to the first stage optical logic elements 1-1 to 1-4 is input to the first and second stage optical logic elements 1-5 and 1-6. The relative light intensity of the bias light is 1/3, and the relative light intensity of the bias light input to the third-stage optical logic element 1-7 is 1/9. In other words, by adjusting the relative light intensity of the bias light, the merge ratio of each of the optical logic elements 1-1 to 1-7 can be set.

The optical logic elements 1-1 to 1-7 can operate if the merge ratio is 1: α: 1 (α> 0). If all the optical logic elements have the same merge ratio, the relative light intensity P _{bias — n} of the _bias light can be easily formulated. The detailed configuration of the optical logic elements 1-1 to 1-7 will be described later.

The operation flow of the 8-bit input AND circuit of this embodiment is as follows.
(1) A continuous laser beam is input from the light source 2 to each of the optical waveguides 7-1 to 7-8 and 8-1 to 8-7 with the above-described intensity (constantly input during calculation).
(2) 8-bit input Each bit of the digital electrical signal is input in parallel to the intensity modulators 3-1 to 3-8.
(3) An optical analog operation (in this embodiment, an AND operation of amplitude bits) is performed in each of the optical logic elements 1-1 to 1-7.
(4) The output signal light of the optical logic element 1-7 is photoelectrically converted by the photodetector 4.
(5) The analog electrical signal output from the photodetector 4 is threshold-processed by the threshold processor 5 and converted into a digital electrical signal.

  Each of the intensity modulators 3-1 to 3-8 blocks input light when the corresponding bit of the input digital electric signal is “0” (intensity 0), and input light when the corresponding bit is “1”. Is transmitted (strength 1). Therefore, when all the bits of the input digital electric signal are “1”, the analog electric signal after photoelectric conversion obtained by the photodetector 4 has a maximum value.

  In addition, when bias light having an appropriate intensity is input to each of the optical logic elements 1-1 to 1-7 as shown in FIG. 1, when at least one bit of the input digital electric signal is “0”, The analog electric signal has a value lower than the maximum value. Therefore, by calculating and designing these values of the analog electric signal after photoelectric conversion in advance, only when all the bits of the input digital electric signal are “1”, the threshold value processor 5 sets “1”. The threshold value of the threshold processor 5 can be set so as to be output. That is, it is possible to realize an optoelectronic operation circuit that photoelectrically converts the result of the optical analog operation and realizes a multi-bit logical operation by electrical discrimination.

The calculation delay caused in the present embodiment is determined by the total delay of the following (A) to (D).
(A) Electric / optical signal conversion (EO conversion) delay in the intensity modulators 3-1 to 3-8.
(B) Optical path delay determined by the optical path length from the intensity modulators 3-1 to 3-8 to the photodetector 4 and the equivalent refractive index of the propagation mode.
(C) Optical / electrical signal conversion (OE conversion) delay in the photodetector 4.
(D) Delay in the threshold processor 5.

  Note that there is a possibility that the delays (C) and (D) can be combined into one depending on the circuit configuration. In this embodiment, an additional delay of EO conversion and OE conversion is added as compared with the case where calculation is performed only with an electric signal, but the optical path delay of (B) is sufficiently speeded up by using many optical logic elements. Because it can, from the CMOS circuit (literature “A. Agarwal et al.,“ A 128x128b High-Speed Wide-AND Match-Line Content Addressable Memory in 32 nm CMOS ”, Proceedings of the ESSCIRC, pp. 83-86, 2011”) A circuit with low delay can be expected. For example, in the case of a CMOS circuit, a 128-bit AND operation is estimated to require 145 picoseconds even if the configuration is optimized. On the other hand, in the present embodiment, there is a possibility that it can be realized with about one-tenth of that. Furthermore, if the throughput is determined by the operating frequency of the intensity modulators 3-1 to 3-8 (EO modulator), 10 GHz or more can be expected.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a configuration example of an 8-bit input AND circuit (optical logic circuit) according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. Since the light source 2 is the same as that of the first embodiment, the description of the light source 2 is omitted in FIG.

  The 8-bit input AND circuit of this embodiment includes optical logic elements 1-1 to 1-7, a light source 2, intensity modulators 3-1 to 3-8, a photodetector 4, and a threshold value processor. 5, optical waveguides 7-1 to 7-8, 8-1 to 8-7, 9-1 to 9-6, and optical waveguides 7-1, 8-1, 7-3, 8-3, 7- 5, 8-5, 7-7, 8-7, 9-1, 9-3, 8-2, 8-6, 9-5, 8-4. 10-14 and calibration intensity modulators 11-1 to 11-7 provided in the optical waveguides 8-1, 8-3, 8-5, 8-7, 8-2, 8-6, and 8-4. It consists of. This 8-bit input AND circuit is integrated on a substrate made of a dielectric material.

In this embodiment, calibration phase shifters 10-1 to 10-14 and calibration intensity modulators 11-1 to 11-7 are added to the 8-bit input AND circuit of the first embodiment.
In the first embodiment, the optical path length and the merging ratio of each of the optical logic elements 1-1 to 1-7 may deviate from the desired values or vary due to an optical waveguide manufacturing error.

  Therefore, in order to calibrate the variation in the performance of the optical logic element 1-1, continuous light of intensity 1 is input from the light source 2 to the optical waveguides 7-1 and 7-2, and from the intensity modulators 3-1 and 3-2. The optical waveguide 7-1 for the light propagating through the optical waveguide 7-2 is set so that the output light from the optical output port 6C of the optical logic element 1-1 is maximized in the state where the amplitude bit of intensity 1 is output. The relative phase of the propagating light may be adjusted by the calibration phase shifter 10-1. Further, continuous light having an intensity of 1 is input from the light source 2 to the optical waveguide 7-1, an amplitude bit of intensity 1 is output from the intensity modulator 3-1, and a bias of intensity 1 is applied from the light source 2 to the optical waveguide 8-1. The phase of the bias light is adjusted by the calibration phase shifter 10-2 so that the output light of the optical output port 6C of the optical logic element 1-1 is minimized in a state where the light is input, and the intensity of the bias light is adjusted. Adjustment may be performed by the calibration intensity modulator 11-1.

  Further, in order to calibrate the variation in the performance of the optical logic element 1-2, continuous light having an intensity of 1 is input from the light source 2 to the optical waveguides 7-3 and 7-4, and from the intensity modulators 3-3 and 3-4. In the state where the amplitude bit of intensity 1 is output, the optical waveguide 7-3 with respect to the light propagating through the optical waveguide 7-4 is set so that the output light of the optical output port 6C of the optical logic element 1-2 is maximized. The relative phase of the propagating light may be adjusted by the calibration phase shifter 10-3. Further, continuous light of intensity 1 is input from the light source 2 to the optical waveguide 7-3, and an amplitude bit of intensity 1 is output from the intensity modulator 3-3, and a bias of intensity 1 is applied from the light source 2 to the optical waveguide 8-3. The phase of the bias light is adjusted by the calibration phase shifter 10-4 so that the output light of the optical output port 6C of the optical logic element 1-2 is minimized while the light is input, and the intensity of the bias light is adjusted. Adjustment may be performed by the calibration intensity modulator 11-2.

  Calibration method of optical logic element 1-3 using calibration phase shifters 10-5 and 10-6 and calibration intensity modulator 11-3, calibration phase shifters 10-7 and 10-8, and calibration intensity The calibration method of the optical logic element 1-4 using the modulator 11-4 is the same as the calibration method of the optical logic elements 1-1 and 1-2.

  Next, after calibration of the optical logic elements 1-1 to 1-4 is completed, in order to calibrate the variation in performance of the optical logic element 1-5, the intensity of 1 is continuously applied from the light source 2 to the optical waveguides 7-1 to 7-4. In the state where the light is input, the amplitude bit of intensity 1 is output from the intensity modulators 3-1 to 3-4, and the bias light of intensity 1 is input from the light source 2 to the optical waveguides 8-1, 8-3. The relative phase shift of the light propagating through the optical waveguide 9-1 with respect to the light propagating through the optical waveguide 9-2 so that the output light from the optical output port 6C of the optical logic element 1-5 is maximized. It may be adjusted by 10-9. Further, continuous light of intensity 1 is input from the light source 2 to the optical waveguides 7-1 and 7-2, amplitude bits of intensity 1 are output from the intensity modulators 3-1 and 3-2, and the optical waveguide from the light source 2 is output. In the state where the bias light having the intensity of 1/3 of the continuous light for signal light generation is input to 8-2, the output of the bias light is minimized so that the output light of the optical output port 6C of the optical logic element 1-5 is minimized. The phase may be adjusted by the calibration phase shifter 10-10, and the intensity of the bias light may be adjusted by the calibration intensity modulator 11-5.

  Further, in order to calibrate the variation in performance of the optical logic element 1-6, continuous light having an intensity of 1 is input from the light source 2 to the optical waveguides 7-5 to 7-8, and from the intensity modulators 3-5 to 3-8. In the state where the amplitude bit of intensity 1 is output and the bias light of intensity 1 is input from the light source 2 to the optical waveguides 8-5 and 8-7, the output light of the optical output port 6C of the optical logic element 1-6 is maximum. The relative phase of the light propagating through the optical waveguide 9-3 with respect to the light propagating through the optical waveguide 9-4 may be adjusted by the calibration phase shifter 10-11. Further, continuous light of intensity 1 is input from the light source 2 to the optical waveguides 7-5 and 7-6, amplitude bits of intensity 1 are output from the intensity modulators 3-5 and 3-6, and the optical waveguide from the light source 2 is output. In the state where the bias light having the intensity of 1/3 of the continuous light for signal light generation is input to 8-6, the output light of the optical output port 6C of the optical logic element 1-6 is minimized. The phase may be adjusted by the calibration phase shifter 10-12, and the intensity of the bias light may be adjusted by the calibration intensity modulator 11-6.

  Next, after the calibration of the optical logic elements 1-5 and 1-6, in order to calibrate the variation in performance of the optical logic element 1-7, the intensity 1 is continuously applied from the light source 2 to the optical waveguides 7-1 to 7-8. The light is input and the intensity modulator 3-1 to 3-8 outputs an amplitude bit of intensity 1, and the light source 2 has an intensity of 1 to the optical waveguides 8-1, 8-3, 8-5, and 8-7. The bias light is input, and the bias light having the intensity of 1/3 of the continuous light for signal light generation is input to the optical waveguides 8-2 and 8-6, and the optical output port 6C of the optical logic element 1-7 is connected. The relative phase of the light propagating through the optical waveguide 9-5 with respect to the light propagating through the optical waveguide 9-6 may be adjusted by the calibration phase shifter 10-13 so that the output light becomes maximum. Further, continuous light of intensity 1 is input from the light source 2 to the optical waveguides 7-1 to 7-4, and amplitude bits of intensity 1 are output from the intensity modulators 3-1 to 3-4. 8-1, 8-3, 8-5, and 8-7 are input with a bias light having an intensity of 1, and the optical waveguides 8-2 and 8-6 have a bias that is 1/3 the intensity of continuous light for signal light generation. When light is input and bias light having 1/9 the intensity of continuous light for signal light generation is input to the optical waveguide 8-4, the output light from the optical output port 6C of the optical logic element 1-7 is minimum. Thus, the phase of the bias light may be adjusted by the calibration phase shifter 10-14, and the intensity of the bias light may be adjusted by the calibration intensity modulator 11-7.

  As described above, according to the present embodiment, the optical path lengths of the respective optical waveguides due to manufacturing errors can be obtained by introducing the calibration phase shifters 10-1 to 10-14 and the calibration intensity modulators 11-1 to 11-7. And deviations and variations in the merge ratio of the optical logic elements 1-1 to 1-7 can be compensated.

The calibration phase shifters 10-1 to 10-14 and the calibration intensity modulators 11-1 to 11-7 may be thermo-optical low-speed ones. Since the thermo-optic calibration phase shifters 10-1 to 10-14 can be made sufficiently short (-10 μm), the optical path delay hardly increases. However, it is necessary to add 14 (= 2 ^{N + 1} −2) calibration phase shifters and 7 (= 2 ^N −1) calibration intensity modulators for 8 (= 2 ^N ) bits. is there.

In the first and second embodiments, an 8-bit input AND circuit is described as an example. However, the present invention is not limited to this, and the number of first-stage optical logic elements according to the number of input bits (2 Needless to say, if only ^N / 2) is provided and the number of stages N is increased, a multi-bit AND circuit can be realized.

[Third embodiment]
Next, a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration example of an 8-bit input AND circuit (optical logic circuit) according to the third embodiment of the present invention. The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. It is. The 8-bit input AND circuit of the present embodiment has a light source 2a, a photodetector 4, a threshold value processor 5, and a continuous light for signal light generation in phase according to each bit of the 8-bit input digital electrical signal. Phase shifters 12-1 to 12-8 that generate signal light by modulation, and a three-input one-output optical logic element that performs an AND operation on two signal lights with two signal lights and one bias light as inputs 13-1 to 13-4, two-input one-output optical logic elements 14-1 and 14-2 that combine and output the output lights of the two preceding optical logic elements 13-1 to 13-4, and the immediately preceding The three-input one-output optical logic element 15 that performs an AND operation on two signal lights with the output light and the bias light of the two optical logic elements 14-1 and 14-2 as inputs, and optical waveguides 16-1 to 16-16 -8, 17-1 to 17-5, 18-1 to 18-6. This 8-bit input AND circuit is integrated on a substrate made of a dielectric material.

  The 8-bit input AND circuit of this embodiment includes optical logic elements 13-1 to 13-4 that receive signal lights assigned values of "0" and "1" to different phases, and an optical logic element 13-1. ˜13-4 input optical logic elements 14-1, 14-2 and optical logic elements 15 input optical logic elements 14-1, 14-2 as inputs are cascaded hierarchically. It is a thing. The number of stages is N = 3.

  The optical waveguides 16-1 and 16-2 are connected to the signal light input ports 6A and 6B of the optical logic element 13-1, and the optical waveguides 16-3 and 16-4 are the signal light input port 6A of the optical logic element 13-2. , 6B. The optical waveguides 16-5 and 16-6 are connected to the signal light input ports 6A and 6B of the optical logic element 13-3, and the optical waveguides 16-7 and 16-8 are the signal light input port 6A of the optical logic element 13-4. , 6B. The optical waveguides 17-1, 17-2, 17-4, and 17-5 are connected to the bias light input port 6D of the optical logic elements 13-1 to 13-4.

  The optical output port 6C of the optical logic element 13-1 and the signal light input port 6A of the optical logic element 14-1 are connected by an optical waveguide 18-1, and the optical output port 6C of the optical logic element 13-2 and the light are connected. The signal light input port 6B of the logic element 14-1 is connected by an optical waveguide 18-2. Further, the optical output port 6C of the optical logic element 13-3 and the signal light input port 6A of the optical logic element 14-2 are connected by an optical waveguide 18-3, and the optical output port 6C of the optical logic element 13-4. And the signal light input port 6B of the optical logic element 14-2 are connected by an optical waveguide 18-4.

  Further, the optical output port 6C of the optical logic element 14-1 and the signal light input port 6A of the optical logic element 15 are connected by an optical waveguide 18-5, and the optical output port 6C of the optical logic element 14-2 is connected to the optical signal. The signal light input port 6B of the logic element 15 is connected by an optical waveguide 18-6. The optical waveguide 17-3 is connected to the bias light input port 6D of the optical logic element 15.

  The light source 2a inputs continuous light with intensity 1 to the optical waveguides 16-1 to 16-8. At this time, the light source 2a inputs in-phase continuous light to all the optical waveguides 16-1 to 16-8. The optical waveguides 16-1 to 16-8 are provided with phase shifters 12-1 to 12-8 that receive respective bits of an 8-bit input digital electric signal. In this manner, eight signal lights having phases corresponding to the corresponding bits of the input digital electrical signal can be generated.

  The operating points of the phase shifters 12-1 to 12-8 need to be determined in advance with bias light as a phase reference. Each of the phase shifters 12-1 to 12-8 sets the phase of the input light to the same phase (0) as that of the bias light when the corresponding bit of the input digital electric signal is “0”, and the corresponding bit of “1”. In this case, the phase of the input light is set to the opposite phase (π) from the bias light. Hereinafter, signal light generated by the phase shifters 12-1 to 12-8 and having a fixed intensity of 1 and having the same phase (0) or opposite phase (π) as the bias light is referred to as a phase bit.

  The phase bits generated by the phase shifters 12-1 and 12-2 are input to the signal light input ports 6A and 6B of the optical logic element 13-1, and the phases generated by the phase shifters 12-3 and 12-4. The bits are input to the signal light input ports 6A and 6B of the optical logic element 13-2. The phase bits generated by the phase shifters 12-5 and 12-6 are input to the signal light input ports 6A and 6B of the optical logic element 13-3, and the phases generated by the phase shifters 12-7 and 12-8. The bits are input to the signal light input ports 6A and 6B of the optical logic element 13-4.

  The light source 2a uses the continuous light having the same intensity and the same wavelength as the continuous light for signal light generation input to the optical waveguides 16-1 to 16-8 as bias light, and the optical waveguides 17-1, 17-2, 17-. 4 and 17-5, continuous light having the same wavelength as that of the continuous light for generating signal light and three times the intensity is input to the optical waveguide 17-3 as bias light.

  The bias light propagated through the optical waveguides 17-1, 17-2, 17-4, and 17-5 is input to the bias light input port 6D of the optical logic elements 13-1 to 13-4. The bias light propagated through the optical waveguide 17-3 is input to the bias light input port 6D of the optical logic element 15.

The operation flow of the 8-bit input AND circuit of this embodiment is as follows.
(1) A continuous laser beam is input from the light source 2a to each of the optical waveguides 16-1 to 16-8, 17-1 to 17-5 with the above-described intensity (constantly input during calculation).
(2) 8-bit input Each bit of the digital electric signal is input in parallel to the phase shifters 12-1 to 12-8.
(3) An optical analog operation is performed by each of the optical logic elements 13-1 to 13-4, 14-1, 14-2, and 15.
(4) The output signal light of the optical logic element 15 is photoelectrically converted by the photodetector 4.
(5) The analog electrical signal output from the photodetector 4 is threshold-processed by the threshold processor 5 and converted into a digital electrical signal.

  In this embodiment, unlike the first embodiment, each of the optical logic elements 13-1 to 13-4 performs an AND operation on the phase bits. That is, each of the optical logic elements 13-1 to 13-4 outputs the phase bit “π” to the optical output port 6C when both of the input of the signal light input ports 6A and 6B are the phase bit “π”, and the signal light When at least one of the inputs of the input ports 6A and 6B is the phase bit “0”, the phase bit “0” is output to the optical output port 6C.

The optical logic elements 14-1 and 14-2 join the phase bits input to the signal light input ports 6A and 6B, respectively, and output them to the optical output port 6C.
The optical logic element 15 performs an AND operation using the light output from the optical logic elements 14-1 and 14-2 and input to the signal light input ports 6A and 6B as amplitude bits.

  The configuration of the optical logic elements 13-1 to 13-4, 15 is the same as that of the optical logic elements 1-1 to 1-7 of the first embodiment. The optical logic elements 14-1 and 14-2 correspond to those obtained by removing the bias light input port 6D from the optical logic elements 13-1 to 13-4 and 15.

This embodiment has the following features compared to the first embodiment.
(A) Phase shifters 12-1 to 12-8 are used instead of the intensity modulators 3-1 to 3-8 of the first embodiment.
(B) At the first stage of optical analog computation (N = 1), the confluence ratio of the phase bit of the signal light input port 6A, the bias light of the bias light input port 6D, and the phase bit of the signal light input port 6B is 1: 1: One optical logic element 13-1 to 13-4 is used.
(C) At the final stage of optical analog calculation (N = 3), the merge ratio of the amplitude bit of the signal light input port 6A, the bias light of the bias light input port 6D, and the amplitude bit of the signal light input port 6B is 2: 1. : The optical logic element 15 of 2 is used.
(D) For the operation excluding the first and last stages of the optical analog operation, the optical logic element 14-1 having a confluence ratio of the phase bit of the signal light input port 6A and the phase bit of the signal light input port 6B of 1: 1. 14-2.

  The circuit can be simplified by the above (a), (b), and (d), the loss due to the optical calculation can be reduced by (b) and (d), and the first implementation is performed by (c). It is possible to obtain the same signal discrimination (signal contrast) as in the configuration of the example.

Similar to the first embodiment, the merging ratio of the optical logic elements 13-1 to 13-4, 15 can be set by adjusting the relative light intensity of the bias light. In the case of the present embodiment, when the confluence ratio of the optical logic elements 13-1 to 13-4 is 1: 1: 1 and the confluence ratio of the optical logic element 15 is 2: 1: 2, the loss due to optical calculation is minimized. Can be In this embodiment, the ratio of the signal light intensity and the bias light intensity of the first-stage optical logic elements 13-1 to 13-4 is 1: 1. When an AND circuit of 8 (= 2 ^N ) bits is configured, when the intensity of continuous light is 1, the relative light intensity P _{bias — N} of the bias light input to the bias light input port 6D of the optical logic element at the final stage. Is (2 ^N-1 -1) ² / (3 × 2 ^N-3 ). Therefore, in the above example, the relative light intensity of the bias light input to the optical logic element 15 is set to 3.

  The optical path delay in this embodiment is almost the same as that of the first embodiment. Thus, in this embodiment, the configuration of the AND circuit of the first embodiment can be simplified.

[Fourth embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 4 is a block diagram showing a configuration example of an 8-bit input AND circuit (optical logic circuit) according to the fourth embodiment of the present invention. The same components as those in FIGS. It is. Since the light source 2a is the same as that in the third embodiment, the light source 2a is not shown in FIG.

  The 8-bit input AND circuit of this embodiment includes a light source 2a, a photodetector 4, a threshold value processor 5, phase shifters 12-1 to 12-8, and optical logic elements 13-1 to 13-. 4, 14-1, 14-2, 15, optical waveguides 16-1 to 16-8, 17-1 to 17-5, 18-1 to 18-6, optical waveguides 16-1, 17-1, Intensities for calibration provided in 16-2, 16-3, 17-2, 16-4, 16-5, 17-4, 16-6, 16-7, 17-5, 16-8, 17-3 It comprises modulators 19-1 to 19-13 and calibration phase shifters 20-1 to 20-4 provided in the optical waveguides 18-1, 18-3, 18-5, and 17-3. This 8-bit input AND circuit is integrated on a substrate made of a dielectric material.

In this embodiment, calibration intensity modulators 19-1 to 19-13 and calibration phase shifters 20-1 to 20-4 are added to the 8-bit input AND circuit of the third embodiment.
Similar to the first embodiment, in the third embodiment, the optical path length and the merging ratio of each of the optical logic elements 13-1 to 13-4, 14-1, 14-2, and 15 are caused by an optical waveguide manufacturing error. It may deviate from the desired value or may vary.

  Therefore, in order to calibrate the variation in the performance of the optical logic element 13-1, continuous light having an intensity of 1 is input from the light source 2a to the optical waveguides 16-1 and 16-2, and then from the phase shifters 12-1 and 12-2. In a state where the phase bit “π” is output, the optical waveguides 16-1 and 16− are arranged so that the phase of the output light from the optical output port 6C of the optical logic element 13-1 is opposite to the bias light (π). The intensity of the light propagating through 2 may be adjusted by the calibration intensity modulators 19-1 and 19-3. Further, continuous light having an intensity of 1 is input from the light source 2a to the optical waveguide 16-1, a phase bit "π" is output from the phase shifter 12-1, and a bias of intensity 1 is applied from the light source 2a to the optical waveguide 17-1. With the light input, the intensity of the bias light is adjusted by the calibration intensity modulator 19-2 so that the phase of the output light of the optical output port 6C of the optical logic element 13-1 is in phase (0) with the bias light. Adjust it.

  Further, in order to calibrate the variation in performance of the optical logic element 13-2, continuous light having an intensity of 1 is input from the light source 2a to the optical waveguides 16-3 and 16-4, and from the phase shifters 12-3 and 12-4. In a state where the phase bit “π” is output, the optical waveguides 16-3 and 16− are set so that the phase of the output light from the optical output port 6C of the optical logic element 13-2 is opposite to the bias light (π). 4 may be adjusted by calibration intensity modulators 19-4 and 19-6. Further, continuous light having an intensity of 1 is input from the light source 2a to the optical waveguide 16-3, a phase bit “π” is output from the phase shifter 12-3, and a bias of intensity 1 is applied from the light source 2a to the optical waveguide 17-2. With the light input, the intensity of the bias light is adjusted by the calibration intensity modulator 19-5 so that the phase of the output light of the optical output port 6C of the optical logic element 13-2 is in phase (0) with the bias light. Adjust it.

  A calibration method for the optical logic element 13-3 using the calibration intensity modulators 19-7 to 19-9 and a calibration method for the optical logic element 13-4 using the calibration intensity modulators 19-10 to 19-12 are also available. This is the same as the calibration method for the optical logic elements 13-1 and 13-2.

  Next, after the calibration of the optical logic elements 13-1 to 13-4 is completed, in order to calibrate the variation in performance of the optical logic element 14-1, a continuous intensity of 1 from the light source 2a to the optical waveguides 16-1 to 16-4. While inputting light and outputting phase bits “π” from the phase shifters 12-1 to 12-4, while bias light having intensity 1 is input from the light source 2 a to the optical waveguides 17-1 and 17-2, The relative phase shift of the light propagating through the optical waveguide 18-1 with respect to the light propagating through the optical waveguide 18-2 so that the output light from the optical output port 6C of the optical logic element 14-1 is maximized. 20-1 may be adjusted.

  Further, in order to calibrate the variation in the performance of the optical logic element 14-2, continuous light having an intensity of 1 is input from the light source 2a to the optical waveguides 16-5 to 16-8, and from the phase shifters 12-5 to 12-8. In the state where the phase bit “π” is output and the bias light having the intensity 1 is input from the light source 2a to the optical waveguides 17-4 and 17-5, the output light of the optical output port 6C of the optical logic element 14-2 is the maximum. The relative phase of the light propagating through the optical waveguide 18-3 with respect to the light propagating through the optical waveguide 18-4 may be adjusted by the calibration phase shifter 20-2.

  Next, after calibrating the optical logic elements 14-1 and 14-2, in order to calibrate the variation in performance of the optical logic element 15, continuous light of intensity 1 is applied from the light source 2a to the optical waveguides 16-1 to 16-8. The phase shifter 12-1 to 12-8 outputs the phase bit “π”, and the light source 2a supplies the optical waveguides 17-1, 17-2, 17-4, 17-5 with a bias light of intensity 1. Is input, the relative phase of the light propagating through the optical waveguide 18-5 is calibrated with respect to the light propagating through the optical waveguide 18-6 so that the output light of the optical output port 6C of the optical logic element 15 becomes maximum. What is necessary is just to adjust with the phase shifter 20-3. Further, continuous light of intensity 1 is input from the light source 2a to the optical waveguides 16-1 to 16-8, and phase bits “π” are output from the phase shifters 12-1 to 12-8, and the optical waveguide from the light source 2a. 17-1, 17-2, 17-4, and 17-5 are input with a bias light having an intensity of 1, and the optical waveguide 17-3 is input with a bias light having an intensity three times that of continuous light for signal light generation. Thus, the phase of the bias light is adjusted by the calibration phase shifter 20-4 so that the output light of the optical output port 6C of the optical logic element 15 is minimized, and the intensity of the bias light is adjusted by the calibration intensity modulator 19-. 13 may be adjusted.

  As described above, according to the present embodiment, the optical path lengths of the respective optical waveguides due to manufacturing errors are obtained by introducing the calibration intensity modulators 19-1 to 19-13 and the calibration phase shifters 20-1 to 20-4. And deviations and variations in the merge ratio of the optical logic elements 13-1 to 13-4, 14-1, 14-2, and 15 can be compensated.

Similarly to the second embodiment, the calibration intensity modulators 19-1 to 19-13 and the calibration phase shifters 20-1 to 20-4 may be thermo-optical low-speed ones. However, it is necessary to add 4 (= 2 ^N-1 ) calibration phase shifters and 13 (= 3 × 2 ^N +1) calibration intensity modulators for 8 (= 2 ^N ) bits. .

In the third and fourth embodiments, an 8-bit input AND circuit is described as an example. However, the present invention is not limited to this, and the number of first-stage optical logic elements according to the number of input bits (2 It is needless to say that a multi-bit AND circuit can be realized by providing only ^N / 2) and increasing the number of stages N (increasing the number of stages of the optical logic elements 14-1 and 14-2). In this case, the 2-stage 1-output optical logic element in the middle stage receives the output light of the immediately preceding 3-input 1-output optical logic element and the output light of the immediately preceding 2-input 1-output optical logic element. There is a case.

[Fifth embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration example of an 8-bit input AND circuit (optical logic circuit) according to the fifth embodiment of the present invention. The same components as those in FIGS. It is. The 8-bit input AND circuit of this embodiment combines the light source 2b, the photodetector 4, the threshold value processor 5, the phase shifters 12-1 to 12-8, and the two signal lights for output. 2-input 1-output optical logic elements 21-1 to 21-6 and the output light and bias light of the immediately preceding one optical logic elements 21-1 to 21-4 are combined and output. 3-input 1-output that performs an AND operation of two signal lights with the output light and bias light of the optical logic elements 22-1 to 22-4 and the immediately preceding two optical logic elements 21-5 and 21-6 as inputs. The optical logic device 23 includes optical waveguides 24-1 to 24-8 and 25-1 to 25-5, 26-1 to 26-4, and 27-1 to 27-6. This 8-bit input AND circuit is integrated on a substrate made of a dielectric material.

  The 8-bit input AND circuit of the present embodiment is an optical logic element 21-1 to 21-4 having a phase bit as an input, and an output having the outputs of the optical logic elements 21-1 to 21-4 and bias light as inputs. Of the logic elements 22-1 to 22-4, the optical logic elements 21-5 and 21-6 that receive the outputs of the optical logic elements 22-1 to 22-4, and the optical logic elements 21-5 and 21-6. The optical logic elements 23 having outputs as inputs are cascaded in a hierarchical manner, and the first-stage optical logic elements 13-1 to 13-4 of the third and fourth embodiments are connected to the optical logic element 21-. 1 to 21-4 and optical logic elements 22-1 to 22-4 are replaced with a cascade connection. In this embodiment, the loss due to optical calculation is slightly increased as compared with the third and fourth embodiments, but the signal contrast is the same as in the third and fourth embodiments.

  The optical waveguides 24-1 and 24-2 are connected to the signal light input ports 6A and 6B of the optical logic element 21-1, and the optical waveguides 24-3 and 24-4 are the signal light input ports 6A of the optical logic element 21-2. , 6B. The optical waveguides 24-5 and 24-6 are connected to the signal light input ports 6A and 6B of the optical logic element 21-3, and the optical waveguides 24-7 and 24-8 are the signal light input port 6A of the optical logic element 21-4. , 6B.

  The optical output port 6C of the optical logic element 21-1 and the signal light input port 6A of the optical logic element 22-1 are connected by an optical waveguide 26-1, and the optical output port 6C of the optical logic element 21-2 and the light are connected. The signal light input port 6A of the logic element 22-2 is connected by an optical waveguide 26-2. The optical output port 6C of the optical logic element 21-3 and the signal light input port 6A of the optical logic element 22-3 are connected by an optical waveguide 26-3, and the optical output port 6C of the optical logic element 21-4 and the light are connected. The signal light input port 6A of the logic element 22-4 is connected by an optical waveguide 26-4. The optical waveguides 25-1 and 25-2 are connected to the signal light input ports 6B of the optical logic elements 22-1 and 22-2. The optical waveguides 25-4 and 25-5 are connected to the signal light input ports 6B of the optical logic elements 22-3 and 22-4.

  The optical output port 6C of the optical logic element 22-1 and the signal light input port 6A of the optical logic element 21-5 are connected by an optical waveguide 27-1, and the optical output port 6C of the optical logic element 22-2 is connected to the light. The signal light input port 6B of the logic element 21-5 is connected by an optical waveguide 27-2. The optical output port 6C of the optical logic element 22-3 and the signal light input port 6A of the optical logic element 21-6 are connected by an optical waveguide 27-3, and the optical output port 6C of the optical logic element 22-4 and the light are connected. The signal light input port 6B of the logic element 21-6 is connected by an optical waveguide 27-4.

  Further, the optical output port 6C of the optical logic element 21-5 and the signal light input port 6A of the optical logic element 23 are connected by the optical waveguide 27-5, and the optical output port 6C of the optical logic element 21-6 and the optical signal are connected. The signal light input port 6B of the logic element 23 is connected by an optical waveguide 27-6. The optical waveguide 25-3 is connected to the bias light input port 6D of the optical logic element 23.

  The light source 2b inputs continuous light with intensity 1 to the optical waveguides 24-1 to 24-8. At this time, the light source 2b inputs in-phase continuous light to all the optical waveguides 24-1 to 24-8. The optical waveguides 24-1 to 24-8 are provided with phase shifters 12-1 to 12-8 that receive respective bits of an 8-bit input digital electric signal. In this way, phase bits can be generated as in the third and fourth embodiments.

  The light source 2b uses the continuous light having the same wavelength and half the intensity as the continuous light for signal light generation input to the optical waveguides 24-1 to 24-8 as bias light, and the optical waveguides 25-1 and 25-2. , 25-4, 25-5, and continuous light having the same wavelength and 9/4 intensity as the continuous light for signal light generation is input as bias light to the optical waveguide 25-3.

The operation flow of the 8-bit input AND circuit of this embodiment is as follows.
(1) A continuous laser beam is input from the light source 2b to each of the optical waveguides 24-1 to 24-8 and 25-1 to 25-5 with the above-described intensity (constant input during calculation).
(2) 8-bit input Each bit of the digital electric signal is input in parallel to the phase shifters 12-1 to 12-8.
(3) An optical analog operation is performed by each of the optical logic elements 21-1 to 21-6, 22-1 to 22-4, and 23.
(4) The output signal light of the optical logic element 23 is photoelectrically converted by the photodetector 4.
(5) The analog electrical signal output from the photodetector 4 is threshold-processed by the threshold processor 5 and converted into a digital electrical signal.

The optical logic elements 21-1 to 21-4 join the phase bits input to the signal light input ports 6A and 6B, respectively, and output them to the optical output port 6C.
The optical logic elements 22-1 to 22-4 respectively output the light output from the optical logic elements 21-1 to 21-4 and input to the signal light input port 6A and the bias light input to the signal light input port 6B. Merge and output to the optical output port 6C.

The optical logic element 21-5 combines the lights output from the optical logic elements 22-1 and 22-2 and input to the signal light input ports 6A and 6B, and outputs the combined light to the optical output port 6C. The optical logic element 21-6 combines the lights output from the optical logic elements 22-3 and 22-4 and input to the signal light input ports 6A and 6B, and outputs the combined light to the optical output port 6C.
The optical logic element 23 performs an AND operation using the light output from the optical logic elements 21-5 and 21-6 and input to the signal light input ports 6A and 6B as amplitude bits.

  In the case of the present embodiment, the merge ratio of the phase bit of the signal light input port 6A and the phase bit of the signal light input port 6B of the optical logic elements 21-1 to 21-4, and the optical logic elements 22-1 to 22-4 The merge ratio between the phase bit of the signal light input port 6A and the bias light of the signal light input port 6B, and the phase bit of the signal light input port 6A of the optical logic elements 21-5 and 21-6 and the phase of the signal light input port 6B The merge ratios with the bits are all 1: 1. The ratio of the signal light intensity to the bias light intensity of the optical logic elements 21-1 to 21-4 and 22-1 to 22-4 is optimally 2: 1.

Similar to the third and fourth embodiments, the merge ratio of the amplitude bit of the signal light input port 6A, the bias light of the bias light input port 6D, and the amplitude bit of the signal light input port 6B of the optical logic element 23 at the final stage. Is 2: 1: 2, loss due to optical computation can be minimized. When an AND circuit of 8 (= 2 ^N ) bits is configured, when the intensity of continuous light is 1, the relative light intensity P _{bias — N} of the bias light input to the bias light input port 6D of the optical logic element at the final stage. becomes ^{(2 N-1 -1) 2} /2 N-1. Therefore, in the above example, the relative light intensity of the bias light input to the optical logic element 23 is 9/4.

In this embodiment, an 8-bit input AND circuit has been described as an example. However, the present invention is not limited to this, and only the number (2 ^N / 2) of first-stage optical logic elements corresponding to the number of input bits is used. Needless to say, if the number of stages N is increased (the number of stages of the optical logic elements 21-5 and 21-6 is increased), a multi-bit AND circuit can be realized.

[Sixth embodiment]
Next, a sixth embodiment of the present invention will be described. In this embodiment, the optical logic elements 1-1 to 1-7, 13-1 to 13-4, 14-1, 14-2, 15, 21-1 to 21 used in the first to fifth embodiments are used. A specific configuration of −6, 22-1 to 22-4, and 23 will be described. FIG. 6 is a perspective view showing the configuration of the optical logic element of this embodiment, and FIG. 7 is a plan view showing the configuration of the optical logic element of this embodiment.

  As shown in FIG. 6, the optical logic element 100 is formed on a substrate 101 made of a first dielectric material and one surface 101a of the substrate 101, and has a higher refractive index than that of the first dielectric material. An optical waveguide 102 made of a second dielectric material, an optical waveguide 103, an optical waveguide 104, and an optical waveguide 105 (bias light input port 6D) are provided.

Examples of the first dielectric that forms the substrate 101 include silica (SiO ₂ ) such as quartz.
The second dielectric that constitutes the optical waveguides 102 to 105 is, for example, silicon (Si). The refractive index of silica is 1.4 in the communication wavelength band (for example, wavelength 1.5 μm), whereas the refractive index of silicon (Si) is 3.5. Therefore, when the optical waveguides 102 to 105 are made of silicon, the substrate and air act as a cladding, and light is confined in the optical waveguides 102 to 105.
Further, by forming the optical waveguides 102 to 105 on one surface 101a of the substrate 101, the optical logic element 100 is configured on the planar optical waveguide.

As shown in FIGS. 6 and 7, in the optical logic device 100 according to the present embodiment, the optical waveguide 102, the optical waveguide 103, and the optical waveguide 104 are connected to each other to form a Y-branch optical waveguide. doing. The optical waveguide 102 and the optical waveguide 103 are optical waveguides for inputting signal light, and function as a set of signal light input ports (signal light input ports 6A and 6B in the first to fifth embodiments). The optical waveguide 104 is an optical waveguide for signal light output, and acts as an optical output port (the optical output port 6C of the first to fifth embodiments).
In this embodiment, the optical waveguide 102 and the optical waveguide 103 serving as the signal light input port are disposed symmetrically with respect to the extension line of the optical waveguide 104 serving as the light output port.

On the other hand, the optical waveguide 105 is an optical waveguide for bias light input, and acts as a bias light input port (bias light input port 6D of the first to fifth embodiments).
The optical waveguide 105 serving as a bias light input port is disposed between the optical waveguide 102 and the optical waveguide 103. More specifically, the optical waveguide 105 is disposed on an extension line of the optical waveguide 104.

  One end of the optical waveguide 105 closer to the Y-branch optical waveguide is formed in a tapered shape in plan view. One end of the tapered optical waveguide 105 is referred to as a “tapered portion 105a”. The tapered portion 105a is disposed adjacent to the optical waveguide 102 and the optical waveguide 103 of the Y-branch optical waveguide with a gap therebetween. As a result, the optical waveguide 102 and the optical waveguide 103 and the optical waveguide 105 are optically coupled to each other.

  In such an optical logic device 100, the input signal light that has propagated through the optical waveguide 102 and the optical waveguide 103, which are signal light input ports, interferes with the bias light that has propagated through the optical waveguide 105, resulting in an optical output port. Output light is output from the optical waveguide 104.

As shown in FIGS. 6 and 7, the structure of the optical logic device 100 according to this embodiment is as follows. The width (waveguide width) W of each waveguide, the height h _{H of} the waveguide, and the optical waveguide for bias light input. 105 taper part 105a length (taper length) L _taper , gap width (gap width between taper waveguides) g between Y branch optical waveguide and taper part, angle formed by optical waveguide 102 and optical waveguide 103 (Y (Branch angle) α.

For example, W = 0.1 to 2.0 μm, h _H = 0.1 to 2.0 μm, L _taper = 0.1 to 20 μm, g = 0 to 1.0 μm, α = 5-60 degrees is assumed. The value of the structural parameter may be appropriately selected according to the material constituting the optical waveguide. For example, there may be a combination of parameters such that the tapered portion 105a of the optical waveguide 105 and the optical waveguide 102 and the optical waveguide 103 constituting the Y-branch optical waveguide contact each other (overlap).

The above-described optical logic element can be manufactured by the following process. That is, a substrate made of silica or the like is prepared, and a silicon (Si) layer is grown on the surface. A method such as CVD may be used for the growth of the silicon layer.
Next, after the photosensitive material applied to the surface of the silicon layer is patterned into a predetermined pattern as shown in FIG. 7, for example, by etching the silicon layer, an optical waveguide as shown in FIG. Can be obtained.

When the optical logic element 100 of this embodiment is used for a logical operation, the phase of one set of input signal lights is in phase with each other. That is, the phase of the pair of input signal lights input to the two optical input ports is adjusted so as to enhance the output light from the optical output port.
The phase of the bias light is opposite to that of the signal light. That is, the phase of the bias light is adjusted with respect to the two input signal lights input to each signal light input port so as to weaken the output light from the light output port.

  If the length of the optical waveguide 102 and the length of the optical waveguide 103 are equal to each other, the input signal light input to the two signal light input ports is a connection point between the optical waveguide 102 and the optical waveguide 103, that is, the Y branch optical waveguide. It is in phase at the branch point.

In this embodiment, in order to obtain a high binary contrast of output light, the following conditions must be satisfied.
(1) The signal light input ports (that is, the optical waveguide 102 and the optical waveguide 103) of signal light such as Y branch are introduced symmetrically with respect to the direction of the optical output port (optical waveguide 104).
(2) There is a bias light input port.
(3) The bias light intensity P _bias can be adjusted.

As described in the first to fifth embodiments, the merge ratio of the optical logic element 100 can be set by adjusting the intensity P _{bias of the} bias light.
As described above, according to this embodiment, the optical logic element 100 is replaced with the optical logic elements 1-1 to 1-7, 13-1 to 13-4, 15 described in the first to fifth embodiments. 23 can be used. Further, a Y-branch optical waveguide having a structure composed of the substrate 101 and the optical waveguides 102 to 104 is used as the optical logic elements 14-1, 14-2, 21-1 to 21-6, 22-1 to 22-4. Can do.

  According to this embodiment, in order to avoid problems in nonlinear optics, it is possible to realize a high binary contrast in a wide wavelength band by using a linear optical element. In addition, since the operation is based only on linear optics, a large input intensity is not required, and the performance is independent of the input intensity, so that significant power saving can be expected at the photon level.

  Furthermore, a decrease in signal strength due to optical logic operation, that is, insertion loss is suppressed to a minimum, and in some cases, a gain of about 0.2 to 0.3 dB is maintained with binary contrast maintained, and one or more outputs Strength comes out. That is, since the input signal light can be amplified, compensation processing by nonlinear optics at the subsequent stage necessary for signal discrimination can be minimized. Further, higher performance can be expected by combining a linear optical logic operation with amplification and a slight nonlinear optical effect.

  Further, in the same element, the logical operation function can be changed by optical adjustment, specifically, adjusting the intensity of the bias light. As a result, the circuit configuration can be changed flexibly and at high speed with an adjustment mechanism that has been previously introduced into the circuit even after the optical circuit is manufactured.

  Further, according to the optical logic device 100 according to the present embodiment, the device length of the region where the optical interference actually occurs is about 2 μm, so that the optical signal path time is as extremely short as about 0.02 ps. This is at least 1/100 or more shorter than that of a conventional optical switch, so that the path time of the entire optical path element circuit can be greatly shortened, and it can contribute to the realization of an optical operation with a very low delay. .

  Further, in this embodiment, since a wide band operation is possible, a wavelength division multiplexing operation by a single element is possible. Further, since it can be configured only with a dielectric material, additional loss can be suppressed and fabrication can be facilitated. Further, the element can be made on-chip and further shortened. These are important for optical computation applications with low computation delay.

  Furthermore, a CMOS foundry that can be integrated with a phase shifter and an intensity modulator can be used as long as the phase shifter and the intensity modulator are configured with only a dielectric material and can be easily manufactured and in an optical communication wavelength band.

  Further, on-chip integration is possible, and a plurality of elements can be connected with a sufficiently short optical waveguide. As a result, various functionalities can be created while maintaining the low arithmetic delay.

[Seventh embodiment]
Next, a seventh embodiment of the present invention will be described. This embodiment will explain another specific example of the optical logic element. FIG. 8 is a perspective view showing the configuration of the optical logic element of this embodiment, and FIG. 9 is a plan view showing the configuration of the optical logic element of this embodiment.

As shown in FIG. 8, the optical logic element 200 according to the present embodiment is formed on a substrate 201 made of a first dielectric material such as silica (SiO ₂ ) and one surface 201a of the substrate 201, An optical waveguide 202, an optical waveguide 203, an optical waveguide 204, and an optical waveguide 205 made of a second dielectric material having a higher refractive index than the first dielectric material, such as silicon (Si), are provided. Here, the optical waveguide 202 and the optical waveguide 203 act as signal light input ports (the signal light input ports 6A and 6B in the first to fifth embodiments), and the optical waveguide 204 serves as the light output ports (first to fifth). And the optical waveguide 205 acts as a bias light input port (bias light input port 6D of the first to fifth embodiments).

As shown in FIGS. 8 and 9, in the optical logic device 200 according to the present embodiment, an optical waveguide that acts as a bias light input port between an optical waveguide 202 that acts as a signal light input port and the optical waveguide 203. 205 is arranged. In the present embodiment, the optical waveguide 202 and the optical waveguide 203 are arranged so as to be symmetric with respect to the optical waveguide 205 in plan view.
The optical waveguide 205 and the optical waveguide 204 acting as an optical output port are connected to each other at one end.

The optical waveguide 202 and the optical waveguide 203 that are signal light input ports have coupling portions 202a and 203a that are coupled to the optical waveguide 205 that is a bias light input port, respectively. That is, the coupling portions 202a and 203a are portions corresponding to the length L _{DC in the} vicinity of the tip portions of the optical waveguide 202 and the optical waveguide 203, which are arranged in parallel with the optical waveguide 204 with a gap g _DC therebetween. As described above, the optical waveguide 202 and the optical waveguide 203 are provided with the coupling portions 202a and 203a, respectively, so that the optical waveguide 202 and the optical waveguide 203 and the optical waveguide 205 are separated so as to be coupled to each other and are directionally coupled. A vessel is formed. The length L _DC of the coupling portions 202a and 203a is preferably about 90% of the 3 dB coupling length.

  Thus, according to this embodiment, the optical logic element 200 is used as the optical logic elements 1-1 to 1-7, 13-1 to 13-4, 15, 23 described in the first to fifth embodiments. be able to.

[Eighth embodiment]
Next, an eighth embodiment of the present invention will be described. This embodiment will explain another specific example of the optical logic element. FIG. 10 is a perspective view showing the configuration of the optical logic element of this embodiment, and FIG. 11 is a plan view showing the configuration of the optical logic element of this embodiment.

As shown in FIG. 10, the optical logic device 300 according to the present embodiment is formed on a substrate 301 made of a first dielectric material such as silica (SiO ₂ ) and one surface 301a of the substrate 301, An optical waveguide 302, an optical waveguide 303, an optical waveguide 304, and an optical waveguide 305 made of a second dielectric material having a higher refractive index than the first dielectric material, such as silicon (Si), are provided. Here, the optical waveguide 302 and the optical waveguide 303 act as a pair of signal light input ports (the signal light input ports 6A and 6B in the first to fifth embodiments), and the optical waveguide 304 serves as an optical output port (first 1 to 5 as the optical output port 6C of the fifth embodiment. The optical waveguide 305 functions as a bias light input port (the bias light input port 6D in the first to fifth embodiments).

  In the optical logic device 300 according to the present embodiment, the optical waveguide 302 and the optical waveguide 303 that function as signal light input ports, and the optical waveguide 304 that functions as an optical output port are the optical logic device 100 according to the sixth embodiment. In the same manner as described above, one end of each is connected to each other to form a Y-branch optical waveguide. An angle (Y branch angle) formed by the optical waveguide 302 and the optical waveguide 303 is represented by β.

As shown in FIGS. 10 and 11, in the optical logic device 300 according to the present embodiment, the optical waveguide 305 that is a bias light input port has a coupling portion 305 a that couples with the optical waveguide 304 constituting the Y-branch optical waveguide. . That is, the coupling portion 305a is a portion corresponding to the length L _{DC in the} vicinity of the distal end portion of the optical waveguide 305, which is arranged in parallel with the optical waveguide 304 with a gap g _DC therebetween. Since the optical waveguide 305 includes the coupling portion 305a as described above, the optical waveguide 304 and the optical waveguide 305 are separated to an extent that can be coupled to each other to form a directional coupler. In this embodiment, the signal light is caused to interfere with the Y branch, and then the directional coupler is caused to interfere with the bias light. That is, three-wave interference is divided into two times.

  Thus, according to this embodiment, the optical logic device 300 is used as the optical logic devices 1-1 to 1-7, 13-1 to 13-4, 15, 23 described in the first to fifth embodiments. be able to.

  The present invention can be applied to an optical logic circuit.

  1-1 to 1-7, 13-1 to 13-4, 14-1, 14-2, 15, 21-1 to 21-6, 22-1 to 22-4, 23, 100, 200, 300 ... Optical logic elements, 2, 2a, 2b ... light source, 3-1 to 3-8 ... intensity modulator, 4 ... photodetector, 5 ... threshold value processor, 6A, 6B ... signal light input port, 6C ... light Output port, 6D: bias light input port, 7-1 to 7-8, 8-1 to 8-7, 9-1 to 9-6, 16-1 to 16-8, 17-1 to 17-5 18-1 to 18-6, 24-1 to 24-8, 25-1 to 25-5, 26-1 to 26-4, 27-1 to 27-6, 102 to 105, 202 to 205, 302 to 305: optical waveguide, 10-1 to 10-14, 20-1 to 20-4 ... phase shifter for calibration, 11-1 to 11-7, 19-1 to 19-13 ... intensity change for calibration Vessel, 12-1 to 12-8 ... phase shifter, 101, 201, 301 ... substrate.

Claims (8)

A plurality of three-input one-output optical logic elements that receive two signal lights and bias light, a plurality of two-input one-output optical logic elements that receive two signal lights, one signal light and a bias Cascade connection of at least one kind of optical logic elements among a plurality of two-input / one-output optical logic elements that receive light as input,
An optical logic circuit characterized in that an output light obtained by merging with one optical logic element at the final stage is used as a calculation result. Cascading multiple optical logic elements with 3 inputs and 1 output,
The optical logic element of the first stage receives two signal lights with amplitude bits assigned values of 0 and 1 to different amplitudes and bias light, and
The optical logic elements other than the first stage have the output light of the immediately preceding two optical logic elements and the bias light as inputs,
An optical logic circuit characterized in that an output light obtained by merging with one optical logic element at a final stage is used as a calculation result. A plurality of first optical logic elements with three inputs and one output arranged at the first stage, a second optical logic element with two inputs and one output arranged at a place other than the first stage and the last stage, and arranged at the last stage Cascaded with a third optical logic element with three inputs and one output,
The first optical logic element receives two phase-bit signal lights each assigned a value of 0, 1 to different phases and a bias light,
The second optical logic element receives, as input, output lights of the immediately preceding two first optical logic elements or output lights of the immediately preceding two second optical logic elements,
The third optical logic element has the output light of the immediately preceding two second optical logic elements and the bias light as inputs,
An optical logic circuit characterized in that an output light obtained by merging with the third optical logic element is used as a calculation result. A plurality of first optical logic elements having two inputs and one output arranged in the first stage, a second optical logic element having two inputs and one output arranged in the second stage, an initial stage, a second stage, and a final stage. Cascade connection of a third optical logic element with two inputs and one output arranged at a place other than a fourth optical logic element with three inputs and one output arranged at the final stage;
The first optical logic element receives two phase-bit signal lights in which values of 0 and 1 are assigned to different phases;
The second optical logic element has one output light of the first optical logic element and a bias light as inputs,
The third optical logic element receives, as inputs, output lights of the immediately preceding two second optical logic elements or output lights of the immediately preceding two third optical logic elements,
The fourth optical logic element receives the output light of the immediately preceding two third optical logic elements and the bias light, and
An optical logic circuit characterized in that an output light obtained by joining the fourth optical logic element is used as a calculation result. The optical logic circuit according to claim 2, wherein
A first phase shifter capable of adjusting the phase of one of the two signal lights input to each optical logic element;
A second phase shifter capable of adjusting the phase of the bias light input to each optical logic element;
An optical logic circuit further comprising: an intensity modulator capable of adjusting the intensity of bias light input to each optical logic element. The optical logic circuit according to claim 3, wherein
A first intensity modulator capable of adjusting the intensity of two signal lights input to the first optical logic element;
A first phase shifter capable of adjusting the phase of one of the two signal lights input to the second and third optical logic elements;
A second intensity modulator capable of adjusting the intensity of the bias light input to the first and third optical logic elements;
An optical logic circuit, further comprising: a second phase shifter capable of adjusting a phase of bias light input to the third optical logic element. The optical logic circuit according to any one of claims 1 to 6,
A photodetector for photoelectrically converting the output light of the optical logic element disposed in the final stage;
An optical logic circuit, further comprising: a threshold processing unit that performs threshold processing on the analog electrical signal output from the photodetector and converts the analog electrical signal into a digital electrical signal. The optical logic circuit according to any one of claims 1 to 7,
An optical logic circuit further comprising a light source capable of individually setting the intensity of the plurality of bias lights.