JP2008135692A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower wiring resistance and parasitic inductance while preventing cracking of a pad and a lower layer wiring as well as breakage of a semiconductor element, and shortening the effective length of wiring, with no addition of a manufacturing process. <P>SOLUTION: A top wiring combined with electrode layer 58 is arranged just above a cell part where an LDMOS10 which is to be a power element is formed. A top wiring layer that is electrically connected to the element in the cell part and the electrode layer constituting a part of the pad structure are shared by the top wiring combined with electrode layer 58. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which wire bonding is performed on an upper portion of a cell portion in which a semiconductor element is formed.

  Conventionally, as a technique for enabling wire bonding at an upper portion of a cell portion in which a semiconductor element is formed, for example, there are those shown in Patent Document 1 and Patent Document 2. In Patent Document 1, the film thickness of the insulating film or the metal film is set to 1 to 2 μm in the pad portion where wire bonding is performed, and in Patent Document 2, the wiring is multilayered in the pad portion where wire bonding is performed. Wire bonding can be performed by suppressing the occurrence of cracks and the destruction of semiconductor elements.

  Patent Document 3 also proposes a technique in which a via hole is formed around a portion where wire bonding is performed, and a via hole is not formed immediately below the portion where wire bonding is performed.

Furthermore, in patent document 4, while arrange | positioning Cu electrode so that it may protrude from an insulating film or a passivation film, and coat | covering with the Al film | membrane of the surface of this Cu electrode, the impact absorption at the time of bonding and corrosion resistance of Cu electrode are carried out. A structure capable of achieving the above has been proposed.
Special table 2003-518739 gazette JP-A-8-236706 Japanese Patent No. 3432284 JP 2006-5325 A

  However, in the case of the structures shown in Patent Document 1 and Patent Document 2, it has been confirmed that the structure is easily influenced by the underlying pattern, and it is not always possible to prevent the occurrence of cracks and the destruction of the semiconductor element.

  In the case of the structure of Patent Document 3, since the via hole is formed only around the portion where wire bonding is performed, the drain wiring and the source wiring of the power element have to be routed so far. Since the effective length of the wiring becomes long, the wiring resistance and the parasitic inductance cannot be reduced. In particular, since the drain wiring and the source wiring are routed in the lower layer position, each wiring is thinned and the wiring resistance is likely to be increased.

  On the other hand, if it is the structure of patent document 4, although each said problem can be solved, the exclusive process for forming a thick Cu electrode must be added, and the increase in a manufacturing process and the accompanying high cost are problems. Become. In addition, since the Cu electrode has a convex shape, the upper end of the Cu electrode also swings left and right due to vibration during bonding, resulting in a decrease in adhesion to the base metal at the lower end of the Cu electrode and cracks in the interlayer insulating film. The problem is that the corrosion resistance of the Cu electrode and the Al film for shock absorption during bonding move from the upper end of the Cu electrode to the side surface due to plastic deformation, resulting in the thinning of the Al film, so that the targeted function can be performed stably. The problem of disappearing arises.

  In view of the above points, the present invention, when performing electrical bonding between a bonding metal material such as a bonding wire and the pad portion directly above the cell portion, without adding a manufacturing process, cracks in the pad portion and lower layer wiring, An object of the present invention is to provide a semiconductor device having a structure that can prevent breakdown of a semiconductor element and reduce wiring resistance and parasitic inductance by shortening the effective length of the wiring. In addition, by preventing the electrode from swinging during bonding, the adhesion with the base metal is reduced, the crack in the interlayer insulating film is suppressed, and the decrease in the coverage due to the thin metal film covering the electrode is suppressed. An object of the present invention is to provide a semiconductor device having a structure capable of achieving the above.

  In order to achieve the above object, in the present invention, the uppermost wiring layer (58) constitutes the uppermost wiring and electrode layer that also serves as the electrode layer disposed in the lower layer of the pad portion (62). The uppermost wiring / electrode layer is made of a material having a Young's modulus larger than that of the pad portion, and a portion corresponding to the electrode layer of the uppermost wiring / electrode layer is disposed immediately above the semiconductor element. The pad structure is constituted by a multilayer structure including two layers of an electrode layer of the layers and a pad portion made of a material having a Young's modulus smaller than that of the electrode layer, and the uppermost wiring and electrode layer is It is characterized by being surrounded by an insulating film (60) configured to cover the side wall surface of the uppermost wiring and electrode layer.

  In this way, by adding the uppermost wiring layer and the electrode layer together in the uppermost wiring and electrode layer, an additional manufacturing process is added when electrical bonding between the bonding metal material and the pad portion is performed directly above the cell portion. In addition, a semiconductor device having a structure that can prevent cracks in the pad portion and lower layer wiring, breakage of the semiconductor element, and reduce the wiring resistance and parasitic inductance by shortening the effective length of the wiring.

  Furthermore, since the uppermost wiring / electrode layer is not convex and is surrounded by an insulating film so as to cover the side wall surface of the uppermost wiring / electrode layer, it is possible to prevent the electrode from swinging during bonding. For this reason, it becomes possible to provide a semiconductor device having a structure capable of suppressing a decrease in adhesion to the base metal and a crack in the interlayer insulating film, and a decrease in the coverage due to the thinning of the pad portion covering the electrode. .

  In this case, the material of the uppermost wiring and electrode layer is the metal that constitutes the bonding metal material and the metal that constitutes the pad portion due to the mutual diffusion coefficient between the metal constituting the uppermost wiring and electrode layer and the metal constituting the joining metal material. It is preferable that it is configured to be smaller than the mutual diffusion coefficient. In this way, if the material has a small interdiffusion coefficient, the metal constituting the bonding metal material can be made difficult to diffuse into the lower layer wiring, and the formation of a compound between different metals can be suppressed, cracking due to volume expansion, etc. Can be suppressed.

  For example, the pad portion can be made of Al or an Al alloy, the bonding metal material can be made of Au, and the uppermost wiring and electrode layer can be made of Cu or a Cu alloy.

  Further, when the bonding metal material is a bonding wire (70), the film thickness of the pad portion is such that when the bonding wire is bonded to the pad portion, the pad portion is interposed between the bonding wire and the uppermost wiring and electrode layer. It is preferable that the wire is set to a thickness that is separated from the uppermost wiring and electrode layer. If the thickness is set to such a value, an impact absorbing effect during bonding by the pad portion can be obtained. For example, the effect appears when the film thickness of the pad portion is 0.5 μm or more, preferably 1 μm or more.

  Further, it is preferable that the outer edge of the uppermost wiring and electrode layer protrudes by 1 μm or more from the outer edge of the contact surface between the bonding wire and the pad portion. Preferably it is 5 micrometers or more. As described above, when the outer edge (end surface) of the uppermost wiring and electrode layer protrudes from the outer edge of the bonding wire by 1 μm or more, the shear stress can be made smaller than the crack generation stress.

  Furthermore, in order to connect the wiring layer (55) located below the uppermost wiring / electrode layer and the uppermost wiring / electrode layer, directly below the electrode layer of the uppermost wiring / electrode layer, and the uppermost wiring / electrode layer. A structure in which a contact portion (59) for filling a through hole formed in the interlayer insulating film can be formed. In this case, if the contact part is made of a material having a Young's modulus larger than that of the pad part and the outer edge (end face) of the contact part protrudes from the outer edge of the contact surface between the bonding wire and the pad part by 1 μm or more, the bonding impact A strong structure can be obtained.

  When the contact portion is formed of such a material, the effect is exhibited when the total film thickness of the uppermost wiring / electrode layer and the contact portion is 0.3 μm or more. It is possible to sufficiently obtain a deformation preventing effect at the time of bonding by the electrode layer, and it is possible to prevent the occurrence of cracks in the underlying interlayer insulating film and elements. Of course, the effect can be obtained if the thickness of the uppermost wiring and electrode layer is 0.3 μm or more independently.

  Further, it is preferable that the surface of the uppermost wiring / electrode layer is covered with a passivation film (61), and an opening is formed in the passivation film only at a portion where the uppermost wiring / electrode layer is joined to the pad portion. In this way, it is possible to suppress the formation of the reaction layer (80) by covering the surface of the uppermost wiring and electrode layer with the passivation film (61). In addition, the effect of suppressing oxidation of the surface of the uppermost wiring and electrode layer and factory contamination can be obtained.

  On the other hand, the surface of the uppermost wiring and electrode layer and the outer edge of the pad portion may be covered with a passivation film (61). As described above, by enclosing the outer edge of the pad portion with the passivation film, it is possible to prevent the pad portion from being laterally moved due to an impact during bonding.

  Note that such a passivation film is formed of, for example, a CVD film.

  Further, it is preferable that the surface of the uppermost wiring and electrode layer is quasi-flat with respect to the surface of the insulating film surrounding the uppermost wiring and electrode layer. If a step remains on the surface of the uppermost wiring and electrode layer, the corner (58c) of the step is torn and the metal constituting the bonding metal material and the metal interdiffusing layer constituting the pad portion enter and enter the lower wiring layer. Propagated. Therefore, the barrier property of the uppermost wiring / electrode layer can be ensured, and the mutual diffusion layer can be prevented from being blocked by the uppermost wiring / electrode layer and propagated to the lower layer wiring.

  In the case where the semiconductor element includes a power element and a logic circuit, the uppermost wiring / electrode layer can function as a wiring for both the power element and the logic circuit. In such a case, if the uppermost wiring and electrode layer is made of Cu or Cu alloy, it can be miniaturized by a technique such as Cu damascene. Therefore, the uppermost wiring and electrode layer that functions as both the power element and the logic circuit wiring is provided. Can be easily formed.

  The present invention uses a SOI substrate (2) in which an oxide film (4) is buried between an active layer (5) and a support substrate (3) as a semiconductor substrate, and a trench in which a semiconductor element is formed in the active layer. This is suitable when the elements are separated by (8) and the insulating film (9). That is, the heat dissipation effect can be increased by combining the uppermost wiring layer and the electrode layer in the uppermost wiring / electrode layer. When an SOI substrate is used, heat transfer is deteriorated in an insulating layer composed of an insulating film, a buried oxide film, or the like, so that an increase in heat dissipation effect by using the uppermost wiring and electrode layer is effective.

  Further, when there is a surplus space (90) in the layer where the uppermost wiring / electrode layer is formed, it is preferable to form a dummy pattern (91) made of a material constituting the uppermost wiring / electrode layer. Thus, by forming the dummy pattern of the uppermost wiring and electrode layer in the remaining space, it is possible to increase the heat capacity and the heat dissipation area, and to further increase the heat dissipation effect.

  Further, in this case, it is preferable that the pad portion is bonded to the dummy pattern, and the bonding metal material (70) is connected through the pad portion. As described above, by connecting the bonding metal material to the dummy pattern, the heat dissipation effect can be further enhanced by using the bonding metal material as a heat dissipation path.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 shows a cross-sectional structure of a semiconductor device 1 to which the first embodiment of the present invention is applied. The semiconductor device 1 includes an integrated circuit in which an LDMOS 10, a CMOS 20, and a bipolar transistor (hereinafter referred to as a Bip) 30 are integrally formed in a cell portion. The semiconductor device 1 is formed using an SOI substrate 2.

The SOI substrate 2 has a silicon layer 5 as an active layer disposed on the surface of a silicon substrate 3 as a support substrate via an insulating film 4 such as a silicon oxide film. The silicon layer 5 has an N ⁺ type layer 6 and an N ⁻ type layer 7 formed on the surface layer portion of the N ⁺ type layer 6, and is provided for each region where the LDMOS 10, the CMOS 20, and the Bip 30 are arranged. The elements are isolated by the trench 8 and the insulating layer 9 disposed in the trench 8. For this reason, the LDMOS 10, the CMOS 20, and the Bip 30 are electrically isolated from each other.

The LDMOS 10 is composed of an N-type drain region 11, a P-type channel region 12, and an N ⁺ -type source region 13 that are located on the surface layer of the N ⁻ -type layer 7 in the silicon layer 5. An N ⁺ -type contact layer 14 is formed on the surface layer of the N-type drain region 11, and a P-type contact layer 15 is formed on the surface layer of the P-type channel region 12. The N-type drain region 11 and the P-type channel region 12 are insulated and separated by a so-called LOCOS oxide film 16. A gate electrode 18 is disposed on the P-type channel region 12 via a gate insulating film 17.

The CMOS 20 includes an N-type well layer 21 in the N ⁻ -type layer 7 in the silicon layer 5, a P-type layer 22 on the surface of the N-type well layer 21, an N ⁺ -type source region 23 and an N-type source region 23 on the surface of the P-type layer 22. ^{And a +} -type drain region 24. In addition, a gate electrode 26 is disposed on the region of the P-type layer 22 between the N ⁺ -type source region 23 and the N ⁺ -type drain region 24 via a gate insulating film 25. Although only an N-channel MOSFET is shown here, a P-channel MOSFET is also arranged.

Bip30 is formed in the silicon layer 5, N ^- and N ⁺ -type collector region 31 through the type layer 7 in the vertical and is connected to the N ⁺ -type layer 6, N in the silicon layer 5 ^- the surface of the mold layer 7 P-type base region 32, and N ⁺ -type emitter layer 33 and P ⁺ -type contact layer 34 on the surface layer of P-type base region 32.

  And the wiring structure part 50 is comprised on the surface of the SOI substrate 2 in which each element comprised in this way was formed.

  The wiring structure portion 50 includes a BPSG film 51 formed in order on the silicon layer 5, a first wiring layer 52, a first contact portion 53 embedded in a contact hole of the BPSG film 51, and a first insulating film 54, the 2nd wiring layer 55, the second contact portion 56 buried in the via hole of the first insulating film 54, the second insulating film 57, the uppermost wiring and electrode layer 58, and the via hole of the second insulating film 57. The third contact portion 59, the third insulating film 60, the P-SiN film 61 as a passivation film, and the uppermost wiring and electrode layer 58 are electrically connected to each other through the opening formed in the P-SiN film 61. The pad portion 62 is connected to the. A bonding wire 70 is electrically connected to the pad portion 62 in the wiring structure portion 50.

  The 1st wiring layer 52 and the 2nd wiring layer 55 are wirings for electrically connecting power supply lines, ground lines, or elements for elements such as the LDMOS 10, CMOS 20, Bip 30, and the like, and correspond to the wiring layers of the present invention.

  The first contact portion 53 includes a barrier metal 53a made of a laminated film of Ti / TiN or Ta / TaN, and a W plug 53b disposed on the barrier metal 53a. The first contact part 53 is electrically connected to each part of the LDMOS 10, the CMOS 20, and the Bip 30 through contact holes formed in the BPSG film 51.

  Both the 1st wiring layer 52 and the 2nd wiring layer 55 are constituted by barrier metals 52a and 55a made of a laminated film of Ti / TiN or Ta / TaN, and Cu layers 52b and 55b arranged on the barrier metals 52a and 55a. Has been. The first wiring layer 52 is embedded in a wiring pattern groove formed in the first TEOS film 54 a in the first insulating film 54. A silicon nitride film 54b and a second TEOS film 54c in the first insulating film 54 are formed so as to cover the entire surface of the first wiring layer 52. Openings are formed at desired positions of the silicon nitride film 54b and the second TEOS film 54c, and the second contact portion 56 is electrically connected to the desired position of the first wiring layer 52 through the openings.

  The second contact portion 56 is configured by a barrier metal 56a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 56b disposed on the barrier metal 56a.

  The 2nd wiring layer 55 is embedded in a wiring pattern groove formed in the first TEOS film 57 a in the second insulating film 57. A silicon nitride film 57b and a second TEOS film 57c in the second insulating film 57 are formed so as to cover the entire surface of the 2nd wiring layer 55. Openings are formed at desired positions of the silicon nitride film 57b and the second TEOS film 57c, and the third contact portion 59 is electrically connected to the desired position of the 2nd wiring layer 55 through the openings.

  The third contact portion 59 includes a barrier metal 59a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 59b disposed on the barrier metal 59a.

  The uppermost wiring / electrode layer 58 includes a barrier metal 58a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 58b disposed on the barrier metal 58a. The uppermost wiring / electrode layer 58 serves as both the uppermost wiring layer and the electrode layer (pad) of each element. The uppermost wiring / electrode layer 58 is embedded in the third insulating film 60, that is, all the side walls are the third insulating film. The surface of the uppermost wiring and electrode layer 58 and the surface of the insulating film 60 are quasi-flat. Then, by being surrounded by the third insulating film 60 in this way, the uppermost wiring / electrode layer 58 is formed thicker than the first wiring layer 52 and the second wiring layer 55.

  In this way, the uppermost wiring and electrode layer 58 is used as both the uppermost wiring layer and the electrode layer, so that the uppermost wiring layer and the electrode layer are compared with the case where the uppermost wiring layer and the electrode layer are configured separately. The layer can be made thicker, the wiring resistance can be reduced, and the electrode layer does not need to be formed alone, and a separate manufacturing process is not required for forming only the electrode layer.

In addition, regarding the portion functioning as an electrode layer electrically connected to a portion where a large current flows in the element in the uppermost wiring and electrode layer 58, the area (volume) when viewed from the upper surface is the other electrode layer. It has been enlarged compared to the part that functions as. Here, in the uppermost wiring and electrode layer 58, the portion electrically connected to the N-type drain region 11 and the N ⁺ -type source region 13 in the LDMOS 10 has a larger area than the other portions.

The uppermost wiring and electrode layer 58 also serves as a lower electrode layer located under the pad portion 62, and is therefore made of a material having a large Young's modulus. Here, the Cu layer 58b is used as a base material. However, any material having a Young's modulus of 1.0 × 10 ⁴ kg / m ² or more may be used. For example, Cu alloy, Ti, W, Ni, Cr, Pd, Pt, Mn, Zn, doped Si, doped Poly-Si or the like can be used. However, since the uppermost wiring and electrode layer 58 also serves as the uppermost wiring layer, the mutual diffusion coefficient with Au in the bonding wire 70 to be described later is considered in consideration of workability, electrical conductivity, and thermal conductivity. In consideration of the fact that Au is difficult to propagate to the lower layer wiring when the material is small, Cu or Cu alloy is effective. In particular, in the case of normal Al wiring, fine processing cannot be performed if it is attempted to secure a film thickness in order to reduce the wiring resistance of a power element such as an LDMOS 10, but wiring resistance can be reduced by using a technique such as Cu damascene. It is possible to achieve both reduction of the size and fine processing.

  Furthermore, the reason why such a material having a high Young's modulus is embedded in the third insulating film 60 is to prevent deformation when subjected to an impact during bonding. That is, since the impact during bonding includes a longitudinal impact and a lateral impact, it is possible to effectively suppress deformation of the uppermost wiring and electrode layer 58 as a base by embedding and fixing a hard material. Become. Then, Au wire (material: 4N_Au or 1% Pd_Au, wire diameter: 30 μm to 38 μmφ), load: 25 g to 125 g, US (ultrasonic) power: 75 to 255 range, temperature: 230 ° C., general bonding conditions Below, the film thickness of the uppermost wiring / electrode layer 58 is set to 0.3 μm or more, preferably 0.7 μm or more so that the deformation preventing effect at the time of bonding by the uppermost wiring / electrode layer 58 can be obtained. .

  The third insulating film 60 is composed of a TEOS film, and is disposed on the second insulating film 57 and the third contact portion 59. The third insulating film 60 has the same thickness as that of the uppermost wiring / electrode layer 58, and has a structure in which the uppermost wiring / electrode layer 58 is embedded in a groove formed in the third insulating film 60. Yes.

  The P-SiN film 61 corresponds to a passivation film, and is formed of, for example, a CVD film so as to cover the third insulating film 60 and the uppermost wiring and electrode layer 58, and a pad portion 62 is disposed. It is set as the structure where the opening part was formed only in the site | part. Here, although the passivation film is composed of the P-SiN film 61, it may be a moisture-resistant and insulating film.

  The pad portion 62 is electrically connected to the uppermost wiring and electrode layer 58 through an opening formed in the P-SiN film 61. By bonding to the pad portion 62, each portion of elements such as the LDMOS 10, the CMOS 20, and the Bip 30 formed in the semiconductor device 1 can be electrically connected to the outside.

The pad part 62 is made of a material having a small Young's modulus and plastically deformed by an impact during bonding, that is, a material having a Young's modulus smaller than that of the uppermost wiring / electrode layer 58. Here, the pad portion 62 is made of Al, but may be any material having a Young's modulus of 8.0 × 10 ³ kg / m ² or less. For example, Au, Ag, Pb, Sn or the like is used. Can do. In this way, the pad portion 62 is plastically deformed to absorb an impact during bonding. In order to obtain an impact absorbing effect during bonding by the pad portion 62 as described above, the pad portion 62 is interposed between the bonding wire 70 and the uppermost wiring and electrode layer 58 when the bonding wire 70 is bonded. The film thickness of the pad portion 62 is set so that the bonding wire 70 does not reach the uppermost wiring / electrode layer 58 through the pad portion 62, for example, an Au wire (material: 4N_Au or 1% Pd_Au, wire diameter: 30 μmφ to 38 μmφ) Load: 25 g to 125 g, US (ultrasonic) power: 75 to 255 range, temperature: 230 ° C., under general bonding conditions, effect from 0.5 μm or more It appears that a sufficient effect can be obtained at 1 μm or more.

  In the present embodiment, a pad structure is constituted by the portion corresponding to the electrode layer in the uppermost wiring and electrode layer 58 and the pad portion 62. When these uppermost wiring / electrode layer 58 and pad portion 62 are made of only a material having a large Young's modulus, an impact at the time of bonding is transmitted as it is to the base, so that an interlayer insulating film crack and element destruction occur. This occurs because there is almost no shock absorption effect by the material constituting the interlayer insulating film or the wiring layer. On the contrary, when the uppermost wiring / electrode layer 58 and the pad 62 are made of only a material having a small Young's modulus, the base also plastically deforms simultaneously with the plastic deformation due to the impact during bonding, and the interlayer insulating film cracks. And device destruction occurs. Therefore, the upper pad portion 62 is made of a material having a small Young's modulus, and the uppermost wiring and electrode layer 58 being a lower layer is made of a material having a large Young's modulus.

  The uppermost wiring and electrode layer 58 and the pad portion 62 are formed immediately above the cell portion where the elements such as the LDMOS 10, the CMOS 20, and the Bip 30 are formed (upper portion of the cell portion), and the contact portions 53, 56 and 57 and the wiring layers 52 and 55 are not routed, and each element and the uppermost wiring and electrode layer 58, and thus the pad portion 62 are electrically connected. For this reason, wiring resistance and parasitic inductance can be reduced.

  The bonding wire 70 is composed of an Au wire or the like, and one or a plurality of bonding wires are electrically connected to each pad portion 62 by bonding using ultrasonic vibration or the like. FIG. 2 shows the relationship between each bonding portion, that is, the contact surface 71 between the bonding ball at the tip of the bonding wire 70 and the pad portion 62, the uppermost wiring and electrode layer 58, and FIG. FIG. 2B is a diagram showing the relationship in the cross section of FIG. 1, and is a layout diagram showing the relationship when viewed from above the semiconductor device 1.

  As shown in FIG. 2A, in the present embodiment, the outer edge (specifically, Cu) of the portion corresponding to the electrode layer in the uppermost wiring and electrode layer 58 immediately under the bonding ball at the tip of each bonding wire 70. The wiring width of the uppermost wiring and electrode layer 58 is determined so that the distances L1 and L2 that the outer edge of the layer 58b protrudes from the contact surface 71 are 1 μm or more. Preferably, distances L3 and L4 at which the outer edge of the third contact portion 59 (specifically, the outer edge of the Cu layer 59b) protrudes from the contact surface 71 are set to 1 μm or more.

  The effect obtained by the semiconductor device 1 of the present embodiment having the above configuration will be described.

  In the semiconductor device 1 of the present embodiment, the uppermost wiring and electrode layer 58 is disposed immediately above the cell portion where the LDMOS 10 serving as the power element is formed, and the uppermost wiring layer is electrically connected to the element in the cell portion. The electrode layer constituting a part of the pad structure is also used as the uppermost wiring / electrode layer 58.

  Thus, by using the uppermost wiring layer and the electrode layer in the uppermost wiring / electrode layer 58, the wiring resistance of the power element can be reduced, and the portion corresponding to the wiring layer in the uppermost wiring / electrode layer 58 can be reduced. The heat dissipation effect can be increased by expanding the volume, and further, it is possible to prevent the occurrence of cracks and element damage due to propagation of damage during bonding to the lower wiring layer. In addition, since the uppermost wiring layer and the electrode layer are used together, the manufacturing process can be simplified as compared with the case where the electrode layer is formed alone. Further, when the semiconductor device 1 is used at a high temperature, an interdiffusion layer (reaction layer) of Au in the bonding wire 70 and Al in the pad portion 62 is easily propagated to the lower wiring layer. It becomes possible to prevent it at 58.

  Therefore, when electrical bonding between the bonding metal material and the pad portion is performed directly above the cell portion, it is possible to prevent cracks in the pad portion, lower layer wiring, and the like, and destruction of the semiconductor element without adding a manufacturing process. By shortening the effective length of the semiconductor device, a semiconductor device having a structure in which wiring resistance and parasitic inductance can be reduced can be obtained.

  In the present embodiment, the surface of the uppermost wiring and electrode layer 58 and the surface of the insulating film 60 are quasi-flat. When the uppermost wiring / electrode layer 58 is formed by patterning, for example, a step as shown in FIG. 3 remains in the uppermost wiring / electrode layer 58, and when the pad portion 62 and the bonding wire 70 are disposed thereon, the step The grain boundary of the corner portion 58c is torn by stress, and the interdiffusion layer (reaction layer) of Au in the bonding wire 70 and Al in the pad portion 62 enters the torn corner portion 58c and propagates to the lower wiring layer. There is a fear. However, since the surface of the uppermost wiring / electrode layer 58 and the surface of the insulating film 60 are quasi-flat as in the present embodiment, the barrier property of the uppermost wiring / electrode layer 58 can be secured, and Au and Al This interdiffusion layer is blocked by the uppermost wiring and electrode layer 58 and can be prevented from being propagated to the lower wiring.

  Further, since the uppermost wiring / electrode layer 58 is not convex and is surrounded by the insulating film 60 so as to cover the side wall surface of the uppermost wiring / electrode layer 58, the uppermost wiring / electrode layer 58 is not shaken during bonding. It can be prevented from moving. For this reason, a semiconductor device having a structure capable of reducing adhesion with the underlying metal, suppressing cracks in the interlayer insulating film 57, and suppressing deterioration in coverage due to thinning of the pad portion 62 covering the uppermost wiring and electrode layer 58. It becomes possible.

  FIG. 4 shows the case where the uppermost wiring and electrode layer 58 is made of Al (case 1), and the uppermost wiring with a step left by simply patterning Cu with a thickness of 2 μm by sputtering. When the cum electrode layer 58 is configured (case 2), and after the Cu film having a thickness of 2 μm is formed by plating, the surface of the uppermost wiring and electrode layer 58 is quasi-flat as in the present embodiment. (Case 3) In each case, the crack occurrence rate when left at 250 ° C. for 1870 min from the initial stage of manufacture was examined. As shown in this figure, by making the surface of the uppermost wiring / electrode layer 58 quasi-flat, the crack generation rate can be suppressed, and the barrier property of the uppermost wiring / electrode layer 58 can be secured even at high temperatures. I understand.

  In the present embodiment, the P-SiN film 61 serving as a passivation film covers the uppermost wiring and electrode layer 58 other than the portion where the pad portion 62 is disposed. For this reason, the following effects are acquired. This will be described with reference to FIG.

  FIG. 5 is a schematic diagram showing a state in which a wiring composed of Cu is exposed to water. When the semiconductor device 1 is used in a high-temperature and high-humidity environment, Cu in the uppermost wiring and electrode layer 58 is ionized and water can be electrolyzed. For this reason, Cu serves as the anode, adjacent wiring with different potentials serves as the cathode, the reaction layer (dendrites) 80 extends from the anode side to the cathode side, and the uppermost wiring / electrode layer 58 is short-circuited with the adjacent wiring. End up. On the other hand, since the P-SiN film 61 covers the portion other than the portion where the pad portion 62 is arranged in the uppermost wiring and electrode layer 58 as in the present embodiment, the reaction layer 80 is formed. It becomes possible to suppress. In addition, the effect of suppressing oxidation of the surface of the uppermost wiring and electrode layer 58 and factory contamination can be obtained.

  FIG. 6 shows a case where the P-SiN film 61 serving as a passivation film covers the portion other than the portion where the pad portion 62 is arranged in the uppermost wiring and electrode layer 58 (solid line) and not covered (broken line). 3 is a graph showing the relationship between the service voltage V and service temperature T of the semiconductor device 1 and the lifetime. The life mentioned here means that the uppermost wiring and electrode layer 58 is short-circuited with the adjacent wiring by the reaction layer 80, and the product does not function as a product.

  As shown in this figure, if the use voltage V of the semiconductor device 1 is low, the required life can be obtained even if the use temperature T is high. However, as the use voltage V of the semiconductor device 1 becomes high, the use temperature T is increased. Even if it is lowered, the service life is shortened and the required service life cannot be obtained. For this reason, it is possible to improve the life of the semiconductor device 1 by covering the portion other than the portion where the pad portion 62 is disposed in the uppermost wiring and electrode layer 58 with the P-SiN film 61 serving as a passivation film. Become.

  Further, the uppermost wiring / electrode layer 58 is made of a material having a large Young's modulus, the pad portion 62 is made of a material having a small Young's modulus, and the film thicknesses of the uppermost wiring / electrode layer 58 and the pad portion 62 are set to the above values. I have to. These reasons will be described.

  First, the film thickness of the uppermost wiring and electrode layer 58 is set to 0.7 μm or more, preferably 1 μm or more. This is based on the experimental results shown below. FIG. 7 shows the case where the film thickness of the uppermost wiring / electrode layer 58 and the third insulating film 60 is variously changed while the film thickness of the third contact part 59 is fixed at 1 μm and the film thickness of the pad part 62 is fixed at 1 μm. It is the graph which showed the result of having investigated the crack generation rate. As shown in this figure, when the uppermost wiring / electrode layer 58 and the third insulating film 60 are thin, the effect of suppressing deformation cannot be sufficiently obtained, but the effect is gradually obtained as the film thickness increases. When 0.3 μm, the effect is obtained until the crack occurrence rate becomes 5% or less, and when 0.7 μm or more, more surely 1 μm, the effect is obtained until the crack occurrence rate becomes 0%. Was confirmed. For this reason, the film thicknesses of the uppermost wiring and electrode layer 58 and the third insulating film 60 are set to 0.7 μm or more, preferably 1 μm or more.

  The upper limit of the film thickness of the uppermost wiring / electrode layer 58 is considered to be determined by factors such as the film formation time of the uppermost wiring / electrode layer 58, but there is no particular limitation in the sense that the above effect can be obtained. According to experiments, it has been confirmed that there is no problem until the uppermost wiring and electrode layer 58 has a thickness of 5 μm. Further, if the third contact portion 59 located under the uppermost wiring and electrode layer 58 is made of Cu or Cu alloy having a high Young's modulus like the Cu layer 59b shown in the present embodiment, the third contact portion 59 is provided. Since the total film thickness with the contact portion 59 may be 0.7 μm or more, the film thickness can be reduced as compared with the case where only the uppermost wiring and electrode layer 58 is made of a material having a high Young's modulus.

  The film thickness of the pad portion 62 is 0.5 μm or more, preferably 1 μm or more. This is based on the experimental results shown below. FIG. 8 shows the crack generation rate when the thickness of the pad portion 62 is changed variously while the thickness of the uppermost wiring and electrode layer 58 is fixed at 2 μm and the thickness of the third contact portion 59 is fixed at 1 μm. It is the graph which showed the result. As shown in this figure, if the pad portion 62 is thin, the impact absorbing effect cannot be obtained sufficiently, but as the film thickness increases, the effect is gradually obtained. It was confirmed that the effect was obtained to the extent that the occurrence rate was 5% or less, and that the effect was obtained until the crack occurrence rate was 0% when it was 1 μm. For this reason, the film thickness of the pad part 62 is 0.5 μm or more, preferably 1 μm or more.

  The upper limit of the film thickness of the pad part 62 is considered to be determined by factors such as the film formation time of the pad part 62 and whether or not the patterning of the pad part 62 can be accurately performed, but the above effect can be obtained. There is no limit in meaning. According to experiments, it has been confirmed that there is no problem with the pad portion 62 having a thickness of 3 μm.

  In the present embodiment, the outer edge of the portion corresponding to the electrode layer of the uppermost wiring and electrode layer 58 is the contact surface between the bonding portion and the pad portion 62 immediately below the bonding portion, that is, the bonding ball at the tip of the bonding wire 70. However, the wiring width of the uppermost wiring and electrode layer 58 is determined so as to protrude beyond 1 μm. This will be described with reference to FIG. FIG. 9A shows a simulation analysis result of the shear stress depending on the positional relationship between the bonding portion and the uppermost wiring / electrode layer 58, and FIG. 9B is a cross-sectional view showing a simulation model of the stress analysis. is there.

  As shown in FIG. 9B, in the stress analysis, a pad portion 62 made of Al is disposed on the uppermost wiring and electrode layer 58 made of Cu, and bonding made of Au is further formed on the pad portion 62. The wire 70 is arranged, the outer edge (end face) of the uppermost wiring and electrode layer 58 is shifted from the outer edge of the bonding wire 70, and the shear stress at the outer edge (end face) of the bonding wire 70 is analyzed with respect to the shift amount. However, the shift to the direction where the outer edge of the uppermost wiring / electrode layer 58 protrudes from the outer edge of the bonding wire 70 is the plus side, and the shift to the direction where the outer edge of the uppermost wiring / electrode layer 58 enters the inner side of the outer edge of the bonding wire 70. Is on the minus side.

As shown in FIG. 9A, the shear stress is greatest when the deviation amount is 0, and the shear stress decreases as the deviation amount increases either plus or minus. In the case of plus, the shear stress decreases as the value increases. In the case of minus, the shear stress does not decrease from the value at which the shear stress increases. If the shear stress is 4.8 × 10 ⁵ (N / μm ² ), for example, the crack generation stress is plus 1 μm or more, that is, the outer edge of the uppermost wiring and electrode layer 58 is separated from the outer edge of the bonding wire 70. When protruding beyond 1 μm, the shear stress becomes smaller than the crack generation stress. Therefore, the outer edge of the portion corresponding to the electrode layer in the uppermost wiring and electrode layer 58 protrudes from the contact surface 71 between the bonding portion and the pad portion 62 by 1 μm or more.

  The size of the third contact portion 59 is not particularly limited. However, the second contact layer 55 serving as a lower layer wiring to be connected to the third contact portion 59 and the uppermost wiring and electrode layer 58 serving as an upper layer wiring are not limited. When the intersecting portion is viewed from above the semiconductor device 1, it is preferable that the outer edge of the third contact portion 59 is located inside the outer edge of the intersecting portion. As for the relationship between the outer edge (end surface) of the third contact portion 59 and the contact surface between the bonding portion and the pad portion 62, the same result as in FIG. It is preferable that the outer edge of 59 protrudes 1 μm or more with respect to the contact surface between the bonding portion and the pad portion 62.

  Then, the manufacturing method of the semiconductor device 1 of this embodiment is demonstrated. However, the formation process of the LDMOS 10, the CMOS 20, the Bip 30, etc. with respect to the SOI substrate 2, the BPSG film 51, the first contact part 53, the first wiring layer 52, the first insulating film 54, the second contact in the wiring structure part 50. Since the formation process of the part 56 and the like is the same as the conventional process, only the subsequent processes will be described.

  First, after forming to the 2nd contact part 56, the 1st TEOS film | membrane 57a in the 2nd insulating film 57 is formed into a film. At this time, the thickness of the first TEOS film 57a is set to about the thickness of the 2nd wiring layer 55 to be formed later. Then, a groove is formed in the first TEOS film 57a at a position where the 2nd wiring layer 55 is to be formed by a photo-etching process. Then, after the barrier metal 55a and the Cu layer 55b are formed, the 2nd wiring layer 55 is disposed in the groove of the first TEOS film 57a by performing CMP polishing or the like using the first TEOS film 57a as a stopper. Thereafter, a silicon nitride film 57b is formed so as to cover the surfaces of the first TEOS film 57a and the 2nd wiring layer 55.

  Subsequently, a second TEOS film 57c is formed. At this time, the thickness of the second TEOS film 57c is set to be about the thickness of the third contact portion 59 to be formed later, for example, about 1 μm. Then, a groove is formed in the second TEOS film 57c and the silicon nitride film 57b at a position where the third contact portion 59 is to be formed by a photo-etching process. Then, after the barrier metal 59a and the Cu layer 59b are formed, CMP polishing or the like using the second TEOS film 57c as a stopper is performed, so that the third contact portion 59 is formed in the groove of the second TEOS film 57c and the silicon nitride film 57b. Deploy.

  Thereafter, a third insulating film 60 is formed. At this time, the film thickness of the third TEOS film 59 is about the film thickness of the uppermost wiring and electrode layer 58 to be formed later, that is, 0.5 μm or more, preferably 1 μm or more. Then, a groove is formed in the third TEOS film 59 at a position where the uppermost wiring and electrode layer 58 is to be formed by a photo-etching process. Then, after forming the barrier metal 58a and the Cu layer 58b having a large Young's modulus, CMP polishing or the like using the third insulating film 60 as a stopper is performed, so that the uppermost wiring / electrode layer is formed in the groove of the third insulating film 60. 58 is arranged. As a result, the uppermost wiring and electrode layer 58 surrounded by the third insulating film 60 has a thick film thickness and is quasi-flat with respect to the surface of the third insulating film 60.

  Thereafter, after the P-SiN film 61 is formed, an opening is provided in the P-SiN film 61 at a position where the pad portion 62 is to be formed, and then a metal material having a small Young's modulus for constituting the pad portion 62 is formed. After the film formation, the pad portion 62 is formed by patterning the film. Thereafter, the bonding wire 70 is bonded and bonded. Thereby, the semiconductor device 1 of this embodiment is completed.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, in the layer where the uppermost wiring and electrode layer 58 is formed, the region where the LDMOS 10 is formed, the logic circuit region where the CMOS 20 and the Bip 30 are formed, and the pads for electrically connecting to each part of the logic circuit region A case will be described in which there is a remaining space other than the place where the part is placed, and it is not necessary to place anything.

  FIG. 10 is a diagram schematically showing the layout of the uppermost wiring and electrode layer 58 of the semiconductor device 1. There is a remaining space 90 in addition to the region where the LDMOS 10 is formed, the logic circuit region where the CMOS 20 and the Bip 30 are formed, and the place where the pad portion 62 for electrical connection is disposed. A dummy pattern 91 of the uppermost wiring / electrode layer 58 is formed in the remaining space 90, and a pad portion 62 is provided on the uppermost wiring / electrode layer 58 so that the bonding wire 70 is connected. However, as long as the number of PINs of the package in which the semiconductor device 1 is accommodated is allowed, the PIN and the dummy pattern are connected via the bonding wire 70.

  In this way, by forming the dummy pattern of the uppermost wiring and electrode layer 58 in the remaining space 90, it is possible to increase the heat capacity and the heat dissipation area, thereby further increasing the heat dissipation effect. In addition, by connecting the bonding wire 70 to this dummy pattern, the heat dissipation effect can be further enhanced by using the bonding wire 70 as a heat dissipation path.

  Further, by forming a dummy pattern of the uppermost wiring / electrode layer 58 in the remaining space 90, it is possible to improve the processing uniformity when the uppermost wiring / electrode layer 58 is flattened.

(Other embodiments)
(1) In the embodiment described above, the case where the semiconductor device 1 is manufactured using the SOI substrate 2 has been described. However, other substrates, for example, a single silicon substrate may be used. However, in the case of the SOI substrate 2, heat transfer is deteriorated in the insulating layer 9 composed of the insulating film 4, the buried oxide film, and the like, so that the increase in the heat dissipation effect by using the uppermost wiring and electrode layer 58 is effective. It becomes.

  (2) In the above-described embodiment, the semiconductor device 1 having the LDMOS 10, the CMOS 20, and the Bip 30 as elements has been described as an example. However, the present invention is not limited to this, and other semiconductors that require a large driving current (for example, 10 amperes or more). The present invention can also be applied to a semiconductor device 1 including devices and other power devices.

  (3) In the above-described embodiment, the case where an element formed in a semiconductor substrate such as LDMOS 10, CMOS 20, Bip 30 is used as an example has been described. However, the element is not limited to the element formed in the semiconductor substrate. The present invention can also be applied to the semiconductor device 1 using an element formed on the surface of the semiconductor substrate, such as a passive element.

  (4) In the above embodiment, the case where the third contact portion 59 located below the uppermost wiring and electrode layer 58 is also made of Cu having a large Young's modulus has been described. Here, the material of the pad portion 62 is made of Thus, it may be configured with a small Young's modulus. Furthermore, in the above embodiment, the case where the uppermost wiring / electrode layer 58 is basically made of Cu having a high Young's modulus has been described. However, a portion located on the side wall of the uppermost wiring / electrode layer 58 like the barrier metal 58a. May be made of a material having a small Young's modulus.

  (5) In the above-described embodiment, the case where electrical connection to the pad portion 62 is performed by the bonding wire 70 has been described, but metal bumps may be used. In this case, the outer edge of the uppermost wiring / electrode layer 58 and the outer edge of the third contact portion 59 may protrude from the outer edge of the contact surface between the metal bump and the pad portion 62 as a reference.

  (6) In the first and second embodiments, the uppermost wiring and electrode layer 58 is quasi-flat with the insulating film 60. In other words, it is a concept including a state in which the uppermost wiring / electrode layer 58 has irregularities. For example, FIGS. 11A and 11B are cross-sectional views when the uppermost wiring and electrode layer 58 slightly protrudes from the insulating film 60 and when it is recessed. As shown in this figure, the outer edge of the uppermost wiring / electrode layer 58 is basically aligned with the insulating film 60, but the uppermost wiring / electrode layer 58 protrudes or dents from the surface of the insulating film 60. The above effect can be obtained even if there is a portion.

  (7) Further, in the first and second embodiments, the pad portion 62 is formed after the passivation film 61, and the pad portion 62 is partially disposed above the passivation film 61. On the other hand, the passivation film 61 may be formed after the pad portion 62. FIG. 12 is a cross-sectional view showing an example of the case where the passivation film 61 is formed after the pad portion 62. When the passivation film 61 is formed after the pad portion 62, the outer edge (side wall) of the pad portion 62 can be surrounded by the passivation film 61 as shown in FIG. As described above, the pad portion 62 is made of a material having a small Young's modulus and plastically deformed by an impact at the time of bonding. By surrounding the outer edge of such a soft material with the passivation film 61, the pad portion 62 is formed. It is possible to prevent the pad portion 62 from being laterally moved due to the impact.

It is a figure showing the section composition of semiconductor device 1 in a 1st embodiment of the present invention. FIG. 2A is a layout view in the vicinity of the bonding portion when viewed from above the semiconductor device 1, and FIG. 2B is a partially enlarged view in the vicinity of the bonding portion in FIG. 1. It is an expanded sectional view of a bonding part vicinity when the uppermost wiring and electrode layer 58 is formed by patterning. It is a graph which shows the result of having investigated the crack generation rate when changing the manufacturing method of the top wiring and electrode layer 58, and leaving it to stand under high temperature from the initial stage of manufacture. It is a schematic diagram which shows a mode when the wiring comprised with Cu is exposed to water. It is the graph which investigated the relationship between the service voltage V and service temperature T of the semiconductor device 1 according to the presence or absence of the passivation film, and the lifetime. It is the graph which showed the result of having investigated the crack generation rate when the film thickness of the uppermost wiring and electrode layer 58 and the 3rd insulating film 60 was changed variously. It is the graph which showed the result of having investigated the crack generation rate when changing the film thickness of the pad part 62 variously. (A) is the graph which showed the SIM analysis result of the shear stress by the positional relationship of a bonding part and the uppermost wiring and electrode layer 58, (b) is sectional drawing which shows the simulation model of SIM analysis. It is the figure which showed typically the layout of the uppermost wiring and electrode layer 58 of the semiconductor device 1 in 2nd Embodiment of this invention. (A), (b) is sectional drawing when the uppermost wiring and electrode layer 58 protrudes with respect to the insulating film 60 slightly and when it is recessed. 5 is a cross-sectional view showing an example in the case where a passivation film 61 is formed after the pad portion 62. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 1, 2 ... SOI substrate, 50 ... Wiring structure part, 51 ... BPSG film | membrane, 52 ... 1st wiring layer, 53 ... 1st contact part, 54 ... 1st insulating film, 55 ... 2nd wiring layer, 56 ... Second contact portion, 57 ... second insulating film, 58 ... electrode layer, 59 ... third contact portion, 60 ... third insulating film, 61 ... P-SiN film, 62 ... pad portion, 70 ... bonding wire, 71 ... Contact surface, 80 ... reaction layer, 90 ... remaining space, 91 ... dummy pattern.

Claims (19)

A semiconductor substrate (2) on which semiconductor elements (10, 20, 30) are formed;
Interlayer insulating films (51, 54, 57) formed on the semiconductor substrate;
A plurality of wiring layers (52, 55, 58) electrically connected to the semiconductor element via the interlayer insulating film;
A pad portion that is electrically connected to the uppermost wiring layer (58) of the plurality of wiring layers and to which a bonding metal material (70) for electrically connecting the semiconductor element to the outside is bonded. (62), a semiconductor device comprising:
The uppermost wiring layer (58) constitutes an uppermost wiring and electrode layer that also serves as an electrode layer disposed below the pad portion (62), and the uppermost wiring and electrode layer is the pad portion. And a portion corresponding to the electrode layer of the uppermost wiring and electrode layer is disposed immediately above the semiconductor element,
A pad structure is constituted by a multilayer structure including two layers of the electrode layer of the uppermost wiring and electrode layer and the pad portion that is a material having a Young's modulus smaller than that of the electrode layer,
The uppermost wiring / electrode layer is surrounded by an insulating film (60) configured to cover a side wall surface of the uppermost wiring / electrode layer. In the material of the uppermost wiring and electrode layer, the mutual diffusion coefficient between the metal constituting the uppermost wiring and electrode layer and the metal constituting the bonding metal material constitutes the bonding metal material and the metal constituting the pad portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be smaller than a metal interdiffusion coefficient. 3. The semiconductor device according to claim 1, wherein the pad portion is Al or an Al alloy, the bonding metal material is Au, and the uppermost wiring and electrode layer is Cu or a Cu alloy. The bonding metal material is a bonding wire (70), and the film thickness of the pad portion is such that when the bonding wire is bonded to the pad portion, the pad portion is between the bonding wire and the uppermost wiring and electrode layer. 4. The semiconductor device according to claim 1, wherein the semiconductor device is interposed and has a thickness that separates the bonding wire from the uppermost wiring and electrode layer. 5. 5. The semiconductor device according to claim 4, wherein an outer edge of the uppermost wiring / electrode layer protrudes by 1 μm or more from an outer edge of a contact surface between the bonding wire and the pad portion. A wiring layer (55) positioned below the uppermost wiring / electrode layer of the plurality of wiring layers and the uppermost wiring / electrode layer are connected directly below the electrode layer of the uppermost wiring / electrode layer. 6. The semiconductor device according to claim 4, wherein a contact portion (59) for filling a through hole formed in the interlayer insulating film is formed. The contact portion is made of a material having a Young's modulus larger than that of the pad portion, and the outer edge of the contact portion protrudes from the outer edge of the contact surface between the bonding wire and the pad portion by 1 μm or more. The semiconductor device according to claim 6. 7. The contact portion is made of a material having a Young's modulus larger than that of the pad portion, and the total film thickness of the uppermost wiring / electrode layer and the contact portion is 0.3 μm or more. Or the semiconductor device according to 7; The semiconductor device according to claim 8, wherein a total film thickness of the uppermost wiring and electrode layer and the contact portion is 0.7 μm or more. 9. The semiconductor device according to claim 1, wherein a film thickness of the uppermost wiring / electrode layer is 0.5 μm or more. The semiconductor device according to claim 10, wherein a film thickness of the uppermost wiring and electrode layer is 1.0 μm or more. The surface of the uppermost wiring and electrode layer is covered with a passivation film (61), and an opening is formed in the passivation film only at a portion where the uppermost wiring and electrode layer and the pad portion are joined. 12. The semiconductor device according to claim 1, wherein the semiconductor device is formed. The semiconductor device according to claim 1, wherein a surface of the uppermost wiring and electrode layer and an outer edge of the pad portion are covered with a passivation film (61). The semiconductor device according to claim 12, wherein the passivation film is a CVD film. 15. The surface of the uppermost wiring / electrode layer is quasi-flat with respect to the surface of the insulating film surrounding the uppermost wiring / electrode layer, according to any one of claims 1 to 14. Semiconductor device. The semiconductor element includes a power element and a logic circuit,
16. The semiconductor device according to claim 1, wherein the uppermost wiring / electrode layer functions as wiring for both the power element and the logic circuit. The semiconductor substrate is an SOI substrate (2) in which an oxide film (4) is embedded between an active layer (5) and a support substrate (3),
17. The semiconductor device according to claim 1, wherein the semiconductor element is isolated by a trench (8) and an insulating film (9) formed in the active layer. In the surplus space (90) existing in the layer where the uppermost wiring / electrode layer is formed, a dummy pattern (91) made of a material constituting the uppermost wiring / electrode layer is formed. A semiconductor device according to any one of claims 1 to 17. 19. The semiconductor device according to claim 18, wherein the pad portion is also bonded to the dummy pattern, and the bonding metal material (70) is connected through the pad portion.

Images