JP2008004579A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device using a packaging substrate in a double-layer structure assuring the stabilization and low signal noise of a power supply system for mounting a memory device and a data processing device. <P>SOLUTION: The memory device 4 and the data processing device 3 capable of accessing and controlling the memory device 4 are packaged on the first surface of the packaging substrate. The packaging substrate has a double-layer conductive pattern structure, has signal wiring patterns and power supply wiring patterns 300-307 for connecting the memory device to the data processing device on the first surface, and has a ground pattern on a second surface. On the first surface of the packagin substrate, the power supply wiring patterns compose a plurality of separated paths from the memory device to the data processing device, and the power supply wiring patterns and the signal wiring patterns are arranged without crossing each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a memory device and a data processing device are mounted using a mounting substrate having a two-layer conductive pattern. For example, a double data rate synchronous dynamic random access memory (DDR-) is used as a memory device. The present invention relates to a technique effectively applied when a two-layer conductive pattern structure is adopted for a mounting board on which an SDRAM is mounted.

  The DDR-SDRAM inputs a differential clock signal (CK, / CK) from the outside and performs a memory operation in synchronism with this. In particular, the data input / output from the data input / output buffer is the same as the differential clock signal. It is synchronized with the rising and falling edges of the frequency data strobe signal, and doubles the single data rate (SDR) for inputting and outputting data in units of the data strobe signal period. Therefore, attention should be paid to capacitive coupling of signal lines, reduction of parasitic inductance components, reduction of noise in the power supply system, and the like on the mounting substrate on which the DDR-SDRAM is mounted, compared to the case of mounting the SDR-SDRAM. It will be necessary. For example, according to Non-Patent Document 1, in order to terminate the receiving end in the DDR interface, it is standard to use Vtt (half the power supply voltage for the external input / output interface in the DDR-SDRAM) as the termination potential. . Non-Patent Document 2 describes guidelines for a DDR system memory as a design guide for a chip set such as 865G, and shows a four-layer structure of a conductive pattern as a typical mounting board of a DDR-SDRAM. It is shown that a top signal layer, a power supply layer, a ground layer, and a bottom signal layer are stacked.

JEDEC STANDARD, “stab Series Terminated Logic for 2.5V (SSLT_2)” JESD-9a (Revision for JESD-9), December 2000 Intel (R) 865G / 865GV / 865PE / 865P Chipset Platform Guide, Document Number 252518-005, March 2004, PP.99-121, searched June 6, 2006, Internet URL: http://www.intel .com / design / chipsets / designex / 25251805.pdf

  If the mounting substrate having the four-layer structure is used, two conductive layers can be used to form the power plane and the ground plane, and two conductive layers can be used for the signal wiring layer. Is easy, but there is a limit to cost reduction. In addition, in order to use Vtt as the termination potential, many components such as a regulator for generating a termination power source, an inductor, and a capacitor must be added to the mounting substrate, leading to an increase in cost. When using a two-layer mounting board to reduce costs, it becomes difficult to have separate power and ground planes, and fewer wiring layers can be used for signal wiring. Needs to be considered in order to prevent instability and signal noise from becoming large.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost semiconductor device using a two-layer mounting board that guarantees stabilization of a power supply system and low signal noise for mounting a memory device and a data processing device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] << Mounting board with two-layer structure of conductive pattern >>
In the semiconductor device according to the present invention, a memory device and a data processing device capable of controlling access to the memory device are mounted on the first surface of the mounting substrate. The mounting substrate has a two-layer conductive pattern structure in which conductive patterns are formed on the first surface and the second surface on the back side. The memory device has a plurality of first power supply terminals, first ground terminals, first data terminals, first address terminals, and first control terminals as external connection terminals on two opposite sides of the package. The data processing device has, as external connection terminals, the first power terminal, the first ground terminal, the first data terminal, the first address terminal, and the second control terminal corresponding to the first control terminal, the second ground terminal, A second data terminal; a second address terminal; and a second control terminal. The mounting board includes a power wiring pattern connecting the first power terminal and the second power terminal, a data wiring pattern connecting the first data terminal and the second data terminal, the first address terminal and the second address terminal. An address wiring pattern to be connected and a control wiring pattern to connect the first control terminal and the second control terminal are provided. The mounting substrate has a ground plane formed with a conductive pattern on the second surface. The first ground terminal and the second ground terminal are connected to the ground plane. On the first surface of the mounting substrate, the power supply wiring pattern forms a plurality of spaced paths from the memory device to the data processing device, and the power supply wiring pattern, the data wiring pattern, the address wiring pattern, and the control wiring pattern Are arranged in a non-intersecting state.

  According to the above-described means, the power supply wiring pattern, the data wiring pattern, the address wiring pattern, and the control wiring pattern are arranged in a non-intersecting state, so that the power supply wiring pattern and the signal wiring are exclusively used by using the first surface of the mounting board. A pattern can be formed, and the second surface can be used exclusively as a ground plane to stabilize the ground, which is a reference for the power supply. Since the data wiring pattern, the address wiring pattern, and the control wiring pattern have a pattern layout arranged in parallel with a plurality of separated power wiring patterns, the signal wiring pattern through which the charging current flows and the power wiring through which the return current flows through the output operation An undesired inductance component formed between the patterns can be reduced. For a signal wiring pattern in which a discharge current flows along with the output operation, the ground plane ensures a return current path.

<< Distribution of memory device control terminals and address terminals into two parts >>
As one specific form of the present invention, the memory device has an arrangement in which the first data terminal is closer to the data processing device than the first address terminal and the first control terminal. The second address terminal and the second control terminal are disposed so as to sandwich the second data terminal. With this terminal layout, even if the first data terminal, the first address terminal, and the first control terminal are distributed and arranged on the two opposite sides of the memory device, the address wiring pattern and the control wiring are formed on the first surface of the mounting substrate. It becomes possible to arrange the patterns so as to sandwich the data wiring pattern, and it becomes easy to arrange the power supply wiring pattern, the data wiring pattern, the address wiring pattern, and the control wiring pattern in a non-intersecting state.

<Alternate address and control wiring pattern alternately>
As one specific form of the present invention, a part of the address wiring pattern and the control wiring pattern is alternately laid out and arranged in a different conductive pattern according to the arrangement order of the first address terminal and the first control terminal. . Therefore, the pattern pitch of the address wiring pattern and the control wiring pattern on each conductive pattern forming surface can be formed at approximately twice the arrangement pitch of the first address terminal and the first control terminal, and the inductance between adjacent wiring patterns or Capacitive coupling is reduced. For example, the first address terminal and the first control terminal are typified by a DDR-SDRAM of × 16 bit configuration of JEDEC (Joint Electron Device Engineering Council) standard sealed in a TSOP (Thin Small Outline Package) type package. In this arrangement, the power supply terminals and the ground terminals are rarely unevenly distributed. Therefore, it is meaningful to alternately form the address and control wiring patterns as described above. In many cases, the power terminals and the ground terminals are unevenly distributed in the arrangement of the first data terminals. In such a case, it is not necessary to alternately separate the wiring patterns as described above.

<Ground shield wiring between address and control wiring pattern>
As a more specific form of the present invention, the mounting substrate has ground shield wiring formed between the address wiring pattern and the control wiring pattern on the first surface thereof, and the ground shield wiring is Connected to the ground plane. The ground shield wiring further reduces the inductance or capacitive coupling between adjacent addresses and control wiring patterns.

<< Overlay of address and control wiring pattern and ground shield on different layers >>
Of the address wiring pattern and the control wiring pattern, the wiring pattern formed by being distributed to the second surface, which is the ground plane forming surface of the mounting substrate, overlaps the ground shield wiring formed on the first surface of the mounting substrate. Have an arrangement. The inductance or capacitive coupling in the front and back direction of the mounting board is also reduced.

<< Uneven distribution of power supply terminals and ground terminals in the first data terminal arrangement >>
As one specific form of the present invention, the first power supply terminal and the first ground terminal are unevenly arranged in the first data terminal array. As a result, the pattern pitch of the data wiring pattern can be made larger than the arrangement pitch of the first data terminals, and it becomes easy to secure an area margin in the space for forming the data wiring pattern. This facilitates bending wiring for equalizing the data wiring pattern. In general, data has a stricter timing margin than address and control signals, so it is meaningful to make the wiring pattern the same length.

<< Power supply to the second power supply terminal of the QFP type data processing device >>
As one specific form of the present invention, when the data processing device has a quad flat package (QFP) type package, the plurality of second data are formed on the second surface of the mounting substrate. A power terminal coupling pattern for coupling some of the power terminals to each other is formed. When a necessary and sufficient power supply wiring pattern cannot be formed due to the restriction that the power supply wiring pattern must be formed together with the signal wiring pattern on the first surface of the mounting substrate, the power supply terminal coupling pattern can compensate for this. When the package of the data processing device is a QFP type, the external terminals represented by the second power supply terminals are arranged in a line along the side of the package, and the number of external terminals is limited due to the nature of QFP, and most of the one side Since all the power supply terminals do not become the second power supply terminal, even if a slit is formed in the ground plane corresponding to the portion where the power supply terminal coupling pattern is provided, the area does not increase so much and the ground potential becomes unstable. There is no fear of becoming.

<< Power supply to second power supply terminal of BGA type data processing device >>
As one specific form of the present invention, when the data processing device has a ball grid array (BGA) type package, the plurality of second data are formed on the first surface of the mounting substrate. A power terminal coupling pattern for coupling some of the power terminals to each other is formed. Similarly to the above, when the necessary and sufficient power wiring pattern cannot be formed due to the restriction that the power wiring pattern must be formed together with the signal wiring on the first surface of the mounting substrate, it can be compensated by the power terminal coupling pattern. In particular, when the package of the data processing device is a BGA type, a large number of external terminals represented by the second power supply terminals are concentrically arranged in a plurality of rows on the package surface, and the second power supply terminals are also arranged on the inner periphery accordingly. Many are arranged. For this reason, if a slit is formed in the ground plane and the power supply terminal coupling pattern is provided, the area of the ground plane divided by the slit becomes large, and the ground potential may become unstable. In this regard, here, the power supply terminal coupling pattern is disposed on the first surface of the mounting substrate, so that there is no concern.

<< Power supply / ground terminal arrangement for core circuit of data processing device >>
As one specific form of the present invention, when the data processing device includes a core circuit and an external interface circuit for performing a signal interface between the core circuit and the outside, the second power supply terminal and the second ground The terminal supplies operating power to the external interface circuit, and the data processing device includes a third power terminal and a third ground terminal that supply operating power to the core circuit. At this time, the second power supply terminal and the second ground terminal are disposed between the third power supply terminal and the third ground terminal.

  For example, when the data processing device outputs a signal that changes from a high level to a low level to the second data terminal, a current passes from the second data terminal (s_DQ) to the second ground terminal (s_Gddr) through the data processing device. Flowing. At this time, since the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore) are sandwiched between the second data terminal (s_DQ) and the second ground terminal (s_Gddr), the signal current flowing into the second data terminal On the other hand, a return current flows through the second ground terminal. When viewed from the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore), the direction of the return current of the adjacent second ground terminal and the direction of the signal current flowing into the second data terminal are reversed. Thereby, the influence of the inductance coupling due to the return current of the second ground terminal on the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore), and the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore). Since the influence of the inductance coupling due to the signal current flowing into the second data terminal has a canceling relationship, it is external compared to a layout in which the third power supply terminal and the third ground terminal are sandwiched between the second power supply terminal and the second ground terminal. The operation power supply noise of the core circuit generated during the output operation of the interface circuit can be reduced. Similarly, when the data processing device outputs a signal that changes from a low level to a high level to the second data terminal, a current passes through the data processing device from the second power supply terminal (Vddr) and passes through the second data terminal (DQ). ). At this time, since the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore) are sandwiched between the second data terminal (s_DQ) and the second power supply terminal (s_Vddr), the signal output from the second data terminal A return current flows into the second power supply terminal with respect to the current. When viewed from the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore), the direction of the return current of the adjacent second power supply terminal is opposite to the direction of the signal current output from the second data terminal. As a result, the influence of inductance coupling due to the return current of the second power supply terminal on the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore), and the third ground terminal (s_Gcore) and the third power supply terminal (s_Vcore). Since the influence of the inductance coupling due to the signal current output from the second data terminal has a canceling relationship, it is compared with a layout in which the third power supply terminal and the third ground terminal are sandwiched between the second power supply terminal and the second ground terminal. The operation power supply noise of the core circuit generated during the output operation of the external interface circuit can be reduced.

  This effect is the same regardless of whether the second power supply terminal and the second ground terminal are adjacent to the third power supply terminal and the third ground terminal in any of the following cases. In the first adjacent form, the third power supply terminal is adjacent to the second power supply terminal in an arrangement in which the second power supply terminal and the second ground terminal are sandwiched between the third power supply terminal and the third ground terminal. The third ground terminal is adjacent to the second ground terminal, the third power supply terminal is adjacent to the second data terminal, and the third ground terminal is adjacent to the second data terminal. In the second adjacent form, the third power supply terminal is adjacent to the second ground terminal in the arrangement in which the second power supply terminal and the second ground terminal are sandwiched between the third power supply terminal and the third ground terminal. The third ground terminal is adjacent to the second power terminal, the third power terminal is adjacent to the second data terminal, and the third ground terminal is adjacent to the second data terminal.

<Bypass capacitor>
As one specific form of the present invention, the data processing device includes a core circuit and an external interface circuit for performing a signal interface between the core circuit and the outside. The second power terminal and the second ground terminal supply operating power to the external interface circuit, and the data processing device includes a third power terminal and a third ground terminal that supply operating power to the core circuit. Further, a bypass capacitor mounted on the second surface of the mounting substrate, and a conductive ground through that penetrates the mounting substrate and connects one capacitor terminal of the bypass capacitor to the second ground terminal or the third ground terminal. And a conductive power supply through hole that penetrates the mounting substrate and connects the other capacitor terminal of the bypass capacitor to the second power supply terminal or the third power supply terminal. The conductive ground through hole is disposed closer to the memory device, and the conductive power supply through hole is disposed closer to the data processing device. According to this, in the ground plane in which the return current path on the ground side between the memory device and the data processing device is formed, between the conductive ground through hole connecting the ground terminal to the ground plane and the memory device, The slit for escaping the conductive power supply through hole is not interposed, and the return current path on the ground side is not narrowed, and an increase in ground noise can be suppressed. Further, under the circumstance that the impedance of the power supply system to the second power supply terminal of the data processing device is much larger than the impedance of the ground plane, the bypass capacitor has the impedance of the power supply noise accompanying the return current in the power supply system. It has the function of absorbing into a small ground plane. At this time, since a large return current path is secured between the bypass capacitor and the memory device as described above, power supply system noise can be efficiently absorbed by the bypass capacitor.

<< Reference potential generator >>
As one specific form of the present invention, the data processing device has a first input terminal for a reference voltage, the memory device has a second input terminal for a reference voltage, and the mounting board has the first input. A first reference voltage generation circuit for supplying a reference voltage to the terminal and a second reference voltage generation circuit for supplying a reference voltage to the second input terminal are separately provided. Compared with the case where the reference potential generated by one reference potential generation circuit is distributed to both the memory device and the data processing device, wiring is reduced. The first reference voltage generation circuit may be disposed in the vicinity of a chip corner portion of the data processing device. In general, effective use of the vicinity of the chip corner portion on the mounting board, which often becomes a dead space, can contribute to size reduction of the mounting board.

  [2] A semiconductor device according to another aspect of the present invention includes a memory device mounted on a first surface of a mounting substrate and a data processing device capable of controlling access to the memory device. The mounting substrate has a two-layer conductive pattern structure in which conductive patterns are formed on the first surface and the second surface on the back side. The memory device has a first power supply terminal, a first ground terminal, a first data terminal, a first address terminal, and a first control terminal as external connection terminals on two opposite sides of the package, and the first data terminal is the first data terminal. It has an arrangement closer to the data processing device than one address terminal and the first control terminal. The data processing device has, as external connection terminals, the first power terminal, the first ground terminal, the first data terminal, the first address terminal, and the second control terminal corresponding to the first control terminal, the second ground terminal, A second data terminal, a second address terminal, and a second control terminal are provided, and the second address terminal and the second control terminal are disposed so as to sandwich the second data terminal. The mounting board is arranged in parallel on the first surface, the power wiring pattern connecting the first power terminal and the second power terminal, the data wiring pattern connecting the first data terminal and the second data terminal, An address wiring pattern for connecting the first address terminal and the second address terminal, and a control wiring pattern for connecting the first control terminal and the second control terminal.

  In the first surface of the mounting substrate, the power supply wiring pattern has at least a path passing through a central portion and a path passing through the outermost part of the parallel path of the data wiring pattern, the address wiring pattern, and the control wiring pattern arranged in parallel.

  [3] A semiconductor device according to still another aspect of the present invention includes a memory device mounted on a first surface of a mounting substrate and a data processing device capable of controlling access to the memory device. The mounting substrate has a two-layer conductive pattern structure, the first surface has a signal wiring pattern and a power wiring pattern for connecting the memory device and the data processing device, and the second surface has a ground plane. Have. On the first surface of the mounting substrate, the power supply wiring pattern forms a plurality of spaced paths from the memory device to the data processing device, and the power supply wiring pattern and the signal wiring pattern are arranged in parallel in a non-intersecting state. The power supply wiring pattern has at least a path passing through a central portion of the parallel path of the signal wiring patterns arranged in parallel and a path passing through the outermost part thereof.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to realize a low-cost semiconductor device using a mounting substrate having a two-layer structure in which a power supply system is stabilized and low signal noise is ensured for mounting a memory device and a data processing device.

"System configuration"
FIG. 1 shows a block diagram of a semiconductor device according to an example of the present invention. The semiconductor device 1 includes, for example, a data processing device 3, a DDR-SDRAM 4, a flash memory (FLSH) 5, and interface connectors (TCNCT, VNCCT, ANCCT, PCNCT) 6 to 9 on the first surface (component surface) of the mounting substrate 2. .

  The data processing device 3 is a custom product configured as an SOC (System On Chip) in which a system for performing video control, audio control, and tuning control for digital TV, for example, is on-chip on one semiconductor chip. Although not limited, the package is of QFP type aiming at low cost, and a large number of lead terminals are arranged in a line around the package.

  The data processing device 3 is roughly divided into a core circuit (CORE) 3A and an external interface circuit (EXIF) 3B. Although not particularly illustrated, the core circuit 3A includes a processor that performs overall control, a memory controller, a tuning control unit, a video control unit, an audio control unit, and other peripheral circuits. The external interface circuit 3B includes various input / output buffers (not shown) corresponding to the memory controller, tuning control unit, video control unit, audio control unit, and other peripheral circuits. (FIFL, TIFL, VIFL, AIFL, PIFL) are coupled to corresponding DDR-SDRAM, FLSH, and interface connectors (TCNCT, VNCCT, ANCCT, PCNCT) 6-9. The operating power supply voltage of the core circuit 3A is, for example, 1V, and the operating power supply voltage of the external interface circuit 3B corresponds to the operating power supply voltage of the external circuit connected thereto, for example, a circuit portion of 2.5V and a circuit of 3.3V It is divided roughly into. Needless to say, level conversion circuits such as a level up shifter and a level down shifter are arranged between the core circuit 3A and the external interface circuit 3B.

  The DDR-SDRAM 4 is a dynamic memory used for a work area or a frame buffer of the data processing device 3 and is operated in synchronization with a clock signal. DDR-SDRAM4 has JEDEC standard functions and terminal layouts in accordance with standards such as JEDEC STANDARD, “stab Series Terminated Logic for 2.5V (SSLT_2)” JESD-9a (Revision for JESD-9), December 2000, etc. The package is also TSOP type aiming at low cost. For example, when the operating power supply voltage of the DDR-SDRAM 4 is 2.5V, the operating power supply of the DDR-SDRAM interface circuit in the external interface circuit 3B connected to the signal wiring DIFL is 2.5V. The DDR-SDRAM 4 is accessed under the control of a memory controller that responds to an access request from the processor, video control unit, or the like.

  The flash memory 5 is used to store an operation program executed by the processor of the data processing device 3 and the control data table. The flash memory 5 is accessed under the control of a memory controller that responds to an access request from the processor, video controller, or the like.

  Although not shown in FIG. 1, a bypass capacitor and a resistance element are mounted on the second surface (solder surface) which is the back surface of the mounting substrate.

  The mounting substrate 2 has a two-layer conductive pattern structure (two-layer structure) in which a conductive pattern is formed on the first surface and the second surface for low cost. The fact that only two conductive patterns can be formed means that it is difficult to have a power plane and a ground plane separately, and there are fewer wiring layers that can be used for signal wiring. Since the influence is particularly related to the high-speed operation performance of the DDR-SDRSAM 4 that is DDR-operated, the signal pattern between the data processing device 3 and the DDR-SDRAM 4 and the wiring pattern configuration for supplying power are Some considerations have been taken to prevent instability and signal noise. Hereinafter, from the viewpoint, the configuration of the mounting board in the area AER1 indicated by the two-dot chain line in FIG. 1 will be described in detail.

《Non-crossing wiring structure》
FIG. 2 illustrates in plan view the configuration of wiring patterns for supplying signals and power between the data processing device 3 and the DDR-SDRAM 4 on the first surface (component surface). FIG. 3 shows a planar layout configuration on the second surface (solder surface) corresponding to FIG. In FIG. 2, for convenience, the data processing device 3 and the DDR-SDRAM 4 are illustrated as transparent bodies except for their outlines and lead terminals. FIG. 4 schematically illustrates the arrangement of external terminals of the data processing device 3 and the DDR-SDRAM 4 connected by a wiring pattern and the connection form thereof.

  As shown in FIG. 3, the second surface of the mounting substrate 2 is exclusively assigned to the formation of the ground plane 100, and the first surface of the mounting substrate 2 has almost a signal wiring pattern and a power supply wiring pattern as shown in FIG. Assigned to form.

  In FIG. 2, reference numeral 200 denotes a core circuit power supply wiring pattern to which the operating power supply voltage of the core circuit 3 </ b> A is applied, and is formed under the data processing device 3. In order to supply an operating power supply voltage to the DDR-SDRAM interface circuit and DDR-SDRAM 4 provided in the external interface circuit 3B, a power pattern 300 having a relatively large area is secured under the DDR-SDRAM 4, and the data processing device 3 The power supply wiring patterns 301 to 305 are extended toward the bottom, and the power supply wiring patterns 306 and 307 are extended from the bottom of the memory device so as to bypass the outer sides of the two opposing sides. Various signal wiring patterns are formed in a non-intersecting state between the power supply wiring patterns 301 to 307.

  The arrangement of the external terminals of the data processing device 3 and the DDR-SDRAM 4 will be described with reference to FIG. d_DQ0 to d_DQ15 are data terminals, d_A0 to d_A12 are address terminals, d_UDQS (upper data strobe), d_LDQS (lower data strobe), d_UDM (upper data mask), d_LDM (lower data mask), d_CKE (clock enable), d_WEN ( Write enable), d_CASN (column address strobe), d_RASN (row address strobe), d_CS0 (chip select), d_CK (non-inverted clock), and d_CKN (inverted clock) are control terminals. d_Vddr is a power supply terminal, and d_Gddr is a ground terminal. The external terminal array of the DDR-SDRAM 4 conforms to the JEDEC standard and is arranged on two opposite sides 40 and 41 along the longitudinal direction of the TSOP type package. Each side 40 and 41 has a data system, a control system, and an address system. Are arranged in that order. A relatively large number of power supply terminals d_Vddr and ground terminals d_Gddr are unevenly arranged in the external terminal row of the data system. In particular, the direction of the DDR-SDRAM 4 with respect to the data processing device 3 is selected so that the data terminals d_DQ0 to d_DQ15 are close to the data processing device 3.

  The data processing device includes power terminals s_Vddr, ground terminals s_Gddr, data terminals s_DQ0 to s_DQ15, address terminals s_A0 to s_A12, and control terminals s_UDQS, s_LDQS, s_UDM, and s_LDM as external terminals corresponding to external terminals of the DDR-SDRAM. s_CKE, s_WEN, s_CASN, s_RASN, s_CS0, s_CK, and s_CKN. These external terminals are arranged on one side 30 facing the DDR-SDRAM 4 and one side 31 adjacent to the DDR-SDRAM 4, and the arrangement thereof does not cross the wiring patterns for connecting the corresponding terminals of the memory device 4 and the data processing device 3. In addition, the relationship with the external terminal arrangement of the memory device 4 is considered.

  The first consideration corresponds to the fact that the data terminals d_DQ0 to d_DQ15 in the DDR-SDRAM 4 are arranged closer to the data processing device 3 than the control terminals represented by d_UDQS and the address terminals d_A0 to d_A12. In the data processing device 3, the control terminals represented by s_UDQS and the address terminals s_A0 to s_A12 are arranged so as to sandwich the data terminals s_DQ0 to s_DQ15. For example, if the direction of the arrangement order of the address terminals and control terminals from d_UDQS to d_A4 arranged along the side 40 of the DDR-SDRAM 4 is the arrow Ad direction, the addresses from s_UDQS to s_A4 of the corresponding data processing device 3 The direction of the arrangement order of the terminals and the control terminals is the arrow As direction. Similarly, if the direction of the arrangement order of the address terminals and the control terminals from d_LDQS to d_A3 arranged along the side 41 of the DDR-SDRAM 4 is the arrow Bd direction, the data processing device 3 corresponding to s_LDQS to s_A3 The direction of the arrangement order of the address terminals and the control terminals is the arrow Bs direction. As a result, on the first surface of the mounting substrate 2, the wiring pattern L_CA1 that connects the address terminals and control terminals from d_UDQS to d_A4 and the address terminals and control terminals from s_UDQS to s_A4 can be formed without crossing each other. Similarly, the wiring patterns L_CA2 that connect the address terminals and control terminals from d_LDQS to d_A3 and the address terminals and control terminals from s_LDQS to s_A3 can be formed without crossing each other.

  The second consideration is that the drawing directions of the data wiring patterns L_DQ0 to L_DQ15 coupled to the data terminals d_DQ0 to d_DQ15 of the DDR-SDRAM 4 are partially reversed. For example, as shown in FIG. 5 in which the area in the vicinity of the DDR-SDRAM 4 in FIG. 2 is enlarged, the data wiring patterns L_DQ15 to L_DQ13 of the data terminals d_DQ15 to d_DQ13 of the DDR-SDRAM 4 The data wiring patterns L_DQ12 to L_DQ9 of the terminals d_DQ12 to d_DQ9 are inside the chip with respect to the side 40, and the data wiring pattern L_DQ8 of the data terminal d_DQ8 is outside of the chip with respect to the side 40. In this example, the power supply terminal d_Vddr is arranged at a point where the drawing direction is changed, and the drawing directions of the power supply wiring patterns 302 and 303 connected to the power supply terminal d_Vddr are similarly changed. In consideration of the fact that the arrangement direction of the external terminals of the DDR-SDRAM 4 and the arrangement direction of the external terminals of the data processing device 3 intersect, there is no waste in the space for forming the wiring pattern without intersecting. It is to make it.

  According to the structure of the signal wiring pattern and the power supply wiring pattern connecting the DDR-SDRAM 4 and the data processing device 3, the power supply wiring patterns 300 to 307, the data wiring patterns L_DQ0 to L_DQ15, the address wiring pattern and the control wiring pattern L_CA1. Since L_CA2 is arranged in a non-intersecting state, the power supply wiring pattern and the signal wiring pattern can be formed exclusively using the first surface of the mounting substrate 2, and the second surface is used exclusively for the ground plane 100. It is possible to stabilize the ground potentials Gddr and Gcore, which are power supply references. The power supply wiring patterns 300 to 307, the data wiring patterns L_DQ0 to L_DQ15, the address wiring pattern and the control wiring pattern L_CA1. Since L_CA2 has a pattern layout that substantially follows the power supply wiring patterns 300 to 307 arranged at the center and outside, the signal wiring pattern through which a charging current flows in accordance with the output operation by the data processing device 3 or DDR-SDRAN4 and its return An undesired inductance component formed between the power supply wiring patterns 300 to 307 through which the current flows can be reduced. A return current path can be secured by the ground plane 100 for a signal wiring pattern in which a discharge current flows in accordance with an output operation by the data processing device 3 or the DDR-SDRAN 4.

<Alternate address and control wiring pattern alternately>
A part of the address wiring pattern and the control wiring patterns L_CA1 and L_CA2 shown in FIG. 4 are alternately distributed to the conductive patterns of the first surface and the second surface according to the arrangement order as shown in FIGS. Are laid out. That is, among the address wiring pattern and the control wiring pattern L_CA1, the wiring patterns L_A4, L_A6, L_A8, L_A11, L_CKE, L_CK, L_CKN, L_UDM, and L_UDQS are formed on the first surface (component surface) as illustrated in FIG. The wiring patterns L_A5, L_A7, L_A9, and L_A12 are formed on the second surface (solder surface). Further, among the address wiring pattern and the control wiring pattern L_CA2, the wiring patterns L_A3, L_A1, L_A10, L_BA0, L_RASN, L_WEN, L_LDM, and L_LDQS are formed on the first surface (component surface) as illustrated in FIG. The patterns L_A2, L_A10, L_BA1, L_CS0, and L_CASN are formed on the second surface (solder surface). Naturally, slits are formed in the portion of the ground plane 100 where the wiring patterns L_A2, L_A10, L_BA1, L_CS0, and L_CASN are formed on the second surface, and are electrically insulated.

  According to this, the pattern pitch between the address wiring patterns L_A0 to L_A11 and the control wiring pattern represented by L_CKE and L_RASN on the first and second surfaces is represented by the first address terminals d_A0 to d_A11 and d_CKE and d_RASN. It can be formed at approximately twice the arrangement pitch of the first control terminals, and inductance or capacitive coupling between adjacent wiring patterns can be reduced. As represented by the JEDEC standard DDR-SDRAM sealed in a TSOP type package, the first address terminals d_A0 to d_A11 and the first control terminals represented by d_CKE and d_RASN are arranged in an array. Since the power supply terminals and the ground terminals are rarely distributed, the address wiring patterns L_A0 to L_A11 and the control wiring patterns represented by L_CKE and L_RASN are alternately formed on the first and second surfaces as described above. There is significance to become. Since there are many power supply terminals d_Vddr in the arrangement of the data terminals d_DQ0 to DQ15, a power supply wiring pattern can exist between the data wirings. In such a case, the wiring patterns are alternately separated into layers as described above. It is not necessary to do.

<< Ground shield wiring between address and control wiring pattern >>
As described above, the ground plane 10 is formed on the second surface of the mounting substrate 2. The ground terminal d_Gddr of the DDR-SDRAM 4 and the ground terminal d_Vddr of the data processing device 3 have through holes (through vias) as conductive through holes. To the ground pattern 100. As shown in FIG. 2, between the wiring patterns L_A4, L_A6, L_A8, L_A11, L_CKE, and L_CK formed on the first surface of the mounting substrate 2, and between the wiring patterns L_A3, L_A1, L_A10, and L_BA0. , L_RASN, L_WEN, ground shield wiring L_GSLD is formed between the wiring patterns. The ground shield wiring L_GSLD is connected to the ground plane 100 through a through hole. The ground shield wiring L_GSLD can further reduce the inductance or capacitive coupling between the adjacent address wiring pattern and control wiring pattern.

  The wiring patterns L_A5, L_A7, L_A9, L_A12, L_A2, L_A10, L_BA1, L_CS0, and L_CASN of FIG. 3 formed on the second surface (solder surface) are disposed behind the ground shield wiring L_GSLD. 6 and 7 show an enlarged layout relationship between the wiring pattern and the ground shield wiring L_GSLD. TH_GS is a through hole that connects the ground shield wiring L_GSLD to the ground plane 100. The wiring patterns L_A5, L_A7, L_A9, L_A12, L_A2, L_A10, L_BA1, L_CS0, and L_CASN formed on the second surface are arranged so as to overlap the ground shield wiring L_GSL formed on the first surface of the mounting substrate. Therefore, the inductance or capacitive coupling in the front and back direction of the mounting substrate 2 is also reduced.

  Interference between the address and the control wiring pattern is reduced by the ground shield wiring L_GSL. This configuration is not adopted for the data wiring patterns L_DQ0 to L_DQ15 in the DR-SDRAM 4. This is because the power supply terminal d_Vddr and the ground terminal d_Gddr are unevenly distributed in the array of the data terminals d_QD0 to d_QD15 in the DDR-SDRAM 4. Thereby, the pattern pitch of the data wiring patterns L_DQ0 to L_DQ15 can be made larger than the arrangement pitch of the data terminals d_QD0 to d_QD15, and it becomes easy to secure an area margin in the space for forming the data wiring patterns L_DQ0 to L_DQ15. Because. Further, the bent wiring for equalizing the data wiring patterns L_DQ0 to L_DQ15 is facilitated. Since the DDR-SDRAM 4 has a stricter timing margin for data than the address and control signal, it is meaningful to make the wiring patterns equal to the data wiring patterns L_DQ0 to L_DQ15.

<< Power supply to power supply terminal d_Vddr of data processing device >>
In FIG. 4, the power supply terminal s_Vddr of the data processing device 3 is typically shown as being directly connected to the power supply wiring patterns 300 to 307. However, in fact, the sides 30 and 31 receive the necessary amount of power. In FIG. 4, another power supply terminal s_Vddr (not shown) is arranged. In order to supply power to such a power supply terminal, and to couple the power supply terminals s_Vddr to each other in the vicinity, the second surface (solder surface) of the mounting substrate 2 is connected to a power supply terminal as illustrated in FIG. A power terminal coupling pattern L_Vddr that couples some of the terminals s_Vddr to each other is provided. The power supply terminal coupling pattern L_Vddr is electrically separated from the ground plane 100. When a necessary and sufficient power supply wiring pattern cannot be formed due to the restriction that the power supply wiring patterns 300 to 307 are formed on the first surface of the mounting substrate 2, it can be compensated by the power supply terminal coupling pattern L_Vddr. When the package of the data processing device 3 is a QFP type, its external terminals typified by the power supply terminal s_Vddr are arranged in a line along the side of the package, and the number of external terminals is limited due to the nature of QFP. Since all the power supply terminals s_Vddr are not formed, even if a slit is formed in the ground plane 100 corresponding to the portion where the power supply terminal coupling pattern L_Vddr is provided, the area does not increase so much and the ground potential Gddr becomes unstable. It is thought that there is no risk of becoming a factor.

<< Power supply / ground terminal arrangement for core circuit of data processing device >>
The power supply terminal s_Vddr and the ground terminal s_Gddr in the data processing device supply operating power to the input / output circuit for the DDR-SDRAM 4 of the external interface circuit EXIF3B. Although not shown in FIG. 4, the data processing device 3 has a power supply terminal (third power supply terminal) s_Vcore and a ground terminal (third ground terminal) s_Gcore for supplying operating power to the core circuit 3A. FIG. 8 illustrates an arrangement relationship between the power supply terminal s_Vcore and the ground terminal s_Gcore, and the power supply terminal s_Vddr and the ground terminal s_Gddr.

  For example, in the region AER2 of FIG. 8, the power supply terminal s_Vddr and the ground terminal s_Gddr are sandwiched between the power supply terminal s_Vcore and the ground terminal s_Gcore. A data terminal s_DQ5 is arranged next to the outside of the power supply terminal s_Vcore, and a data terminal s_DQ3 is arranged next to the outside of the ground terminal s_Gcore. In the arrangement of the area AER2, for example, when the data processing device 3 outputs a signal that changes from a high level to a low level to the data terminal s_DQ5, a current flows from the data terminal s_DQ5 to the data processing device 3 and passes through the data terminal s_DQ5. It flows to s_Gddr. At this time, the core power supply terminal s_Vcore is sandwiched between the data terminal s_DQ5 and the ground terminal s_Gddr (Gddr) for the DDR interface. A return current flows through the DDR ground terminal s_Gddr in response to the signal current flowing into the data terminal s_DQ5. When viewed from the core power supply terminal s_Vcore, the direction of the return current of the adjacent ground terminal s_Gddr is opposite to the direction of the signal current flowing into the data terminal s_DQ5. Thus, the influence of inductance coupling due to the return current of the DDR ground terminal s_Gddr on the core power supply terminal s_Vcore and the influence of inductance coupling due to the signal current flowing into the DDR data terminal s_DQ5 on the core power supply terminal s_Vcore. Since the power supply terminals s_Vcore and s_Gcore for the core are offset by the DDR power supply terminal s_Vdd and the ground terminal s_Gddr, the external interface circuit 3B uses the DDR for the DDR. The operation power supply noise of the core circuit 3A generated during the output operation can be reduced. At this time, even when the data terminal s_DQ4 on the opposite side also outputs a signal that changes from the high level to the low level, the noise wraparound can be reduced by the same action with respect to the core ground terminal s_Gcore.

  Similarly, when the data processing device 3 outputs a signal that changes from a low level to a high level to the data terminal DQ4, a current flows from the DDR power supply terminal s_Vddr through the data processing device 3 to the data terminal s_DQ4. . At this time, the ground terminal s_Gcore for the core is sandwiched between the data terminal s_DQ4 and the DDR power supply terminal s_Vddr. A return current flows into the DDR power supply terminal s_Vddr for the signal current output from the data terminal s_DQ4. When viewed from the core ground terminal s_Gcore, the direction of the return current of the adjacent power supply terminal s_Vddr is opposite to the direction of the signal current output from the data terminal s_DQ4. Thereby, the influence of the inductance coupling due to the return current of the DDR power supply terminal s_Vddr on the core ground terminal s_Gcore and the influence of the inductance coupling due to the signal current output from the data terminal s_DQ4 on the core ground terminal s_Gcore are Since the power supply terminal s_Vcore and ground terminal s_Gcore for core are sandwiched between the power supply terminal s_Vdd and ground terminal s_Gddr for DDR, the output for DDR of the external interface circuit 3B has a canceling relationship. The operation power supply noise of the core circuit 3A generated during operation can be reduced. At this time, even when the data terminal s_DQ5 on the opposite side also outputs a signal that changes from the low level to the high level, the noise wraparound can be reduced by the same action for the core power supply terminal s_Vcore.

  Although not shown in particular, the same operation and effect can be obtained when the DDR power terminal s_Vddr is adjacent to the core power terminal s_Vcore and the DDR ground terminal s_Gvddr is adjacent to the core ground terminal Gcore.

FIG. 9 shows terminal arrangements P1 (s_DQ6), P2 (s_DQ5), P3 (s_Vcore), P4 (s_Gddr), P5 (s_Vddr), P6 (s_Gcore), P7 (s_DQ4), P8 (s_DQ3) in the area AER2 of FIG. ) And the mutual inductance between each terminal's self-inductance and the other terminals. The noise wraparound (ΔV) to the core power supply terminal and the core ground terminal due to the inductance coupling between the terminals during the output operation of the data terminal is
ΔV = ΣM · dIs / dt−ΣM · dIvg / dt. Here, M is the mutual inductance, dIs / dt is the current change in the signal terminal, and dIvg / dt is the current change in the DDR power supply terminal and the ground terminal. In the terminal arrangement of P1 to P8, the current corresponding to two data terminals P1 and P2 (P7 and P8) flows through the DDR power supply terminal s_Vddr (ground terminal s_Gddr), so dIvg / dt = 2.・ Dis / dt. When the noise voltage ΔV to the power supply terminal P3 (s_Vcore) of the core circuit is obtained,
ΔV = (dIs / dt) · (Mdq1 + Mdq2-2Mvddr-2Mgdr + Mdq3 + Mdq4)
ΔV = (dIs / dt) · (4.073 + 5.2235-2 × 5.215-2 × 4.087 + 2.937 + 2.59)
ΔV = −3.77 · (dIs / dt).

As a comparative example to the above, the function assignments for the terminal arrays P1 to P8 are P1 (s_DQ6), P2 (s_DQ5), P3 (s_Vddr), P4 (s_Vcore), P5 (s_Gcore), P6 (s_Gddr), P7 (s_DQ4), P8. When the noise voltage to the core power supply terminal s_Vcore (P4) when changed to (s_DQ3) is obtained in the same way,
ΔV = (dIs / dt) · (Mdq1 + Mdq2-2Mvddr-2Mgdr + Mdq3 + Mdq4)
ΔV = (dIs / dt) · (3.385 + 4.075-2 × 5.215-2 × 4.119 + 3.447 + 2.985)
ΔV = −4.78 · (dIs / dt). As is clear from this calculation, the noise wraps around the core power supply less when the DDR power supply terminal and the ground terminal are sandwiched between the core power supply terminal and the ground terminal.

  Next, a simulation result will be described for the signal waveform of the differential clock depending on the arrangement relationship between the DDR power supply terminal and ground terminal and the core power supply terminal and ground terminal. FIG. 10 shows a simulation model. MDL_CHP is a chip model of the DDR interface circuit in the external interface circuit 3B of the data processing device 3, MDL_PKG is a package model of the data processing device, MDL_PCB is a model of the mounting board 2, and MDL_DDR is a simulation model of the DDR-SDRAM 4. Here, the waveforms of the differential clocks CK and CKN (position of TGT) input to the DDR-SDRAM through the wiring pattern of the mounting substrate 2 were obtained by simulation. FIG. 11 shows, as simulation results when the power supply terminal s_Vddr and ground terminal s_Gddr for DDR are sandwiched by the power supply terminal s_Vcore and ground terminal s_Gcore for the core, The transition state of the cross point of the waveform is shown. In FIG. 12, as a comparative example, as a simulation result when the core power supply terminal s_Vcore and the ground terminal s_Gcore are sandwiched between the DDR power supply terminal s_Vddr and the ground terminal s_Gddr, the waveforms of the differential clock signals CK and CKN, The transition state of the waveform crosspoint is shown. In the case of FIG. 11, the clock waveform is more stable, and the cross-point voltages L1 and L2 are not likely to deviate from JEDEC standardization.

《Bypass capacitor placement》
Normally, a bypass capacitor is placed between the ground terminal and the power supply terminal, thereby stabilizing the power supply and trying to absorb power supply system noise. FIG. 13 shows a pair of a power supply terminal and a ground terminal arranged particularly in the vicinity of the side 30 of the data processing device 3 on the first surface of the mounting substrate 2. FIG. 14 shows the mounting land of the bypass capacitor on the second surface corresponding to FIG. In FIG. 14, only the outline of the bypass capacitor 201 is shown as a transparent body for convenience. In FIGS. 13 and 14, TH (s_Vddr) is connected to the power supply wiring pattern P_Vddr and penetrates the mounting substrate 2 to reach the second surface, and TH (s_Vcore) is TH (s_Vcore). A conductive power supply through hole (conductive power supply through hole), TH (s_Gddr), which is connected to the power supply pattern 200 and penetrates the mounting substrate 2 to reach the second surface, is connected to the ground terminal s_Gddr and penetrates the mounting substrate 2. A conductive ground through hole (conductive ground through hole) TH (s_Gcore) reaching the second plane ground plane 100 is connected to the ground terminal s_Gcore and penetrates the mounting substrate 2 to the second plane ground plane 100. It is a conductive ground through hole (conductive ground through hole). As shown in FIG. 14, the ground through holes TH (s_Gddr) and TH (s_Gcore) are arranged near the DDR-SDRAM 4, and the power through holes TH (s_Vddr) and TH (s_Vcore) are arranged near the data processing device 3. The

  According to this, in the ground plane 100 in which the ground-side return current path between the DDR-SDRAM 4 and the data processing device 3 is formed, the ground through hole TH (s_Gddr) that connects the ground terminals s_Gddr and s_Gcore to the ground plane 100. , TH (s_Gcore) and the DDR-SDRAM 4 are not provided with slits for escaping the power supply through holes TH (s_Vddr) and TH (s_Vcore). Such a slit is formed closer to the data processing device 3. As a result, the ground-side return current path connecting the data processing device 3 and the DDR-SDAM 4 is not narrowed, and an increase in ground noise can be suppressed. For example, when the positions where the power supply through holes TH (s_Vddr) and TH (s_Vcore) and the ground through holes TH (s_Gddr) and TH (s_Gcore) are formed are interchanged in FIG. ), TH (s_Gcore) and the width of the path connecting DDR-SDRAM are remarkably narrowed by the slit. In the configuration of FIG. 14, a large return current path can be ensured between the DDR-SDRAM 4 and the data processing device 3 on the ground plane.

  Furthermore, the impedance of the power supply system to the power supply terminal s_Vddr of the data processing device 3 is much larger than the impedance of the ground plane 100. This is because the power supply play for the power supply voltage Vddr is not provided because the two-layer mounting board 2 is employed. Under this circumstance, the bypass capacitor 201 has a function of absorbing the power supply noise accompanying the return current in the power supply system to the ground plane 100 having a small impedance. At this time, as described with reference to FIG. 14, a large return current path is secured between the bypass capacitor 201 and the DDR-SDRAM 4, so that power supply system noise is efficiently absorbed by the bypass capacitor 201. be able to. FIG. 15 illustrates a current path through the bypass capacitor 201 when the signal level changes from L to H.

<< Reference potential generator >>
The memory controller of the DDR-SDRAM 4 and the DDR-SDRAM of the data processing device 3 uses the reference voltage Vref to determine the logical value of the data. The data processing device 3 has an input terminal s_Vref (first input terminal) for a reference voltage Vref as illustrated in FIG. The reference voltage generation circuit 202 that generates the reference voltage Vref is formed on the second surface as illustrated in FIG. 16 and 17, TH (Vref) is a conductive through hole. A land LND_Vre that is electrically connected to the through hole TH (Vref) is formed on the second surface of the mounting substrate 2. LND_Gddr is a land connected to the ground pattern 100, and LND_Vddr is a land connected to the power supply wiring pattern L_Vddr. A resistor R1 and a bypass capacitor C1 are connected in parallel between the lands LND_Gddr and LND_Vref, a resistor R2 and a bypass capacitor C2 are connected in parallel between the lands LND_Vddr and LND_Vref, and a bypass is connected to the lands LND_Gddr and L_Vddr. A capacitor C3 is connected. The reference voltage Vref is formed to a voltage that is, for example, half of the power supply voltage Vddr by resistance voltage division between the resistance element R1 and the resistance element R2. Resistors R1 and R2 and bypass capacitors C1 to C3 are only shown as outlines for convenience.

  As illustrated in FIG. 4, the DDR-SDRAM 4 has an input terminal d_Vref (second input terminal) for a reference voltage Vref. A reference voltage generation circuit for generating the reference voltage Vref for the DDR-SDRAM 4 is formed in the vicinity of the DDR-SDRAM 4 by a resistance voltage dividing circuit or the like different from the circuit configuration of FIG. In FIG. 3, a first reference voltage generation circuit for the data processing device 3 is arranged in the area AER3, and a second reference voltage generation circuit for the DDR-SDRAM 4 is arranged in the area AER4. Since the first reference voltage generation circuit and the second reference voltage generation circuit are provided separately, compared with the case where the reference potential generated by one reference potential generation circuit is distributed to both the DDR-SDRAM 4 and the data processing device 3. Less wiring is required. As a result, the coupling with other wirings is reduced, and the reference potential can be stabilized. The first reference voltage generation circuit is preferably arranged in the vicinity of a chip corner portion of the data processing device 3. Normally, effective use of the vicinity of the chip corner portion on the mounting substrate, which often becomes a dead space, can contribute to size reduction of the mounting substrate 2.

<< Power supply to second power supply terminal of BGA type data processing device >>
FIG. 18 shows an example of a semiconductor device using a data processing device sealed in a BGA type package. FIG. 19 shows a configuration of the second surface side in the semiconductor device of FIG. A main difference from FIG. 2 is that a data processing device 3A of a BGA type package is adopted, and the other configuration is substantially the same, and thus detailed description thereof is omitted. In the example using the QFP type data processing device 3, as shown in FIG. 3, a power terminal coupling pattern L_Vddr that couples some of the power terminals s_Vddr to each other is formed on the second surface. A slit for electrically separating was formed in the ground plane 100. When the data processing device 3A of the BGA type package is used, a part of the plurality of second power supply terminals s_Vddr is formed on the first surface of the mounting board 2 as shown in an enlarged view in FIG. A power supply terminal coupling pattern L_VddrA that couples to each other is formed. As shown in FIG. 21, the power supply terminal coupling pattern L_VddrA is electrically connected to the bypass capacitor mounting lands on the second surface through through holes at a plurality of positions. The DDR power supply pin is required to be present uniformly with the SOC power supply pin. Although it is possible to supply power to the data pin area from the outer periphery, it is difficult to do so in the command / address pin area. Therefore, in order to supply power to the command / address pin area, it is necessary to continuously arrange the power pins. In FIG. 21, a schematic path of L_VddrA is indicated by a broken line. If the power supply pins are not continuously arranged, this path must be formed on the second surface of the mounting substrate 2. In this case, the GND plane is divided, and the GND potential becomes unstable. For this reason, especially when the package of the data processing device 3A is of the BGA type, as shown in FIG. 22, a large number of external terminals are concentrically arranged in a plurality of rows on the package surface, and the power supply terminal s_Vddr is also connected accordingly. Many are arranged around the circumference.

  According to the semiconductor device 1 described above, low cost is realized by using the mounting substrate 2 having a two-layer structure in which the DDR-SDRAM 4 and the data processing device 3 are mounted and the power supply system is stabilized and low signal noise is guaranteed. be able to. Since it is possible to stabilize the power supply system and guarantee low signal noise, it is not necessary to process the termination potential Vtt for the data system wiring or the like on the mounting substrate. For example, it is only necessary to perform termination processing for a very small part of the wiring such as a clock wiring, and it is possible to realize further low cost. In addition, all the wiring topologies can be in a one-to-one connection, whereby the wiring can be simplified and the effect of stabilizing the signal quality can be obtained.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory device is not limited to DDR-SDRAM. Further, it may be an SDRAM of a high-speed clock synchronous operation method. The memory is not limited to SDRAM, and may be other memory such as static synchronous SRAM (static random access memory). The data processing device is not limited to a specific application for digital TV, and may be a data processing device for any application. A microcomputer or a data processor having a DDR-SDRAM interface function may be used instead of the data processing device in the SOC form. Even when the DDR-SDRAM is a memory device, the specific terminal arrangement of the data processing device is not limited to that shown in FIG.

1 is a block diagram of a semiconductor device according to an example of the present invention. It is a top view which illustrates in plan the structure of the wiring pattern for the signal between the data processing device and DDR-SDRAM and power supply in a 1st surface (component surface). It is a top view which shows the planar layout structure of the 2nd surface (solder surface) corresponding to FIG. It is explanatory drawing which illustrates typically the arrangement | sequence of the data processing device connected with a wiring pattern, the external terminal of DDR-SDRAM, and its connection form. FIG. 3 is an enlarged plan view of a region near a DDR-SDRAM in FIG. 2. It is the top view of the 1st surface which expanded and showed the arrangement | positioning relationship between a wiring pattern and ground shield wiring L_GSLD. It is the top view of the 2nd surface which expanded and showed the arrangement | positioning relationship between a wiring pattern and ground shield wiring L_GSLD. It is a top view which illustrates the arrangement relation of power supply terminal s_Vcore and ground terminal s_Gcore, and power supply terminal s_Vddr and ground terminal s_Gddr. Inductance matrix for terminal array P1 (s_DQ6), P2 (s_DQ5), P3 (s_Vcore), P4 (s_Gddr), P5 (s_Vddr), P6 (s_Gcore), P7 (s_DQ4), and P8 (s_DQ3) in region AER2 of FIG. It is explanatory drawing which shows. It is explanatory drawing of the simulation model when simulating about the signal waveform of the differential clock by the arrangement | positioning relationship between the power supply terminal and ground terminal for DDR, and the power supply terminal for core and the ground terminal. It is explanatory drawing which illustrates the simulation result when the power supply terminal s_Vddr for DDR and the ground terminal s_Gddr are sandwiched between the power supply terminal for core s_Vcore and the ground terminal s_Gcore. As a comparative example, it is an explanatory diagram illustrating a simulation result when a core power supply terminal s_Vcore and a ground terminal s_Gcore are sandwiched between a DDR power supply terminal s_Vddr and a ground terminal s_Gddr. It is a top view which illustrates the through-hole arrangement | positioning of the power terminal and ground terminal which are arrange | positioned at the edge | side of a data processing device in the 1st surface of a mounting substrate. It is a top view which illustrates the mounting land of the bypass capacitor in the 2nd surface corresponding to FIG. It is a circuit diagram which illustrates the absorption route of power system noise via a bypass capacitor. It is a top view which shows the input terminal position of the reference voltage Vref in a data processing device. It is explanatory drawing of the reference voltage generation circuit which produces | generates the reference voltage of a data processing device. It is a top view which illustrates the semiconductor device using the data processing device sealed by the BGA type package. FIG. 19 is a plan view showing a configuration on a second surface side in the semiconductor device of FIG. 18. It is a top view which shows arrangement | positioning of the power supply terminal coupling pattern formed in the 1st surface of the mounting board | substrate in the data processing device of a BGA type package. It is a top view which illustrates the path | route of the power supply terminal coupling pattern with respect to the 2nd surface of a mounting board | substrate. It is a top view which illustrates the arrangement | sequence form of the ball electrode in the data processing device of a BGA type package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Mounting board 3 Data processing device 4 DDR-SDRAM
5 Flash memory (FLSH)
6-9 interface connectors (TCNCT, VNCCT, ANCCT, PCNCT)
3A Core circuit (CORE) 3A
3B External interface circuit (EXIF)
d_DQ0 to d_DQ15 Data terminal of DDR-SDRAM d_A0 to d_A12 Address terminal of DDR-SDRAM d_UDQS, d_LDQS, d_UDM, d_LDM, d_CKE, d_WEN, d_CASN, d_RASN, d_CKD d-CKD d_CKD Power supply terminal (first power supply terminal)
d_Gddr DDR-SDRAM ground terminal (first ground terminal)
s_Vddr DDR interface power supply terminal (second power supply terminal)
s_Gddr DDR interface ground terminal (second ground terminal)
s_DQ0 to s_DQ15 Data terminal for DDR interface s_A0 to s_A12 Address terminal for DDR interface s_UDQS, s_LDQS, s_UDM, s_LDM, s_CKE, s_WEN, s_CASN, s_RASN, s_CS0, s_CK, s_CKN DDRQ Patterns 300 to 307 Power supply wiring pattern L_CA1, L_CA2 Address wiring pattern and control wiring pattern Address wiring pattern L_A0 to L_A12
Power supply terminal (third power supply terminal) of the core circuit 3A of the s_Vcore data processing device
Ground terminal (third ground terminal) of the core circuit 3A of the s_Gcore data processing device
TH (s_Vddr) Power supply through hole (conductive power supply through hole)
TH (s_Vcore) Power through hole (conductive power through hole)
TH (s_Gddr) Ground through hole (conductive ground through hole)
TH (s_Gcore) Ground through hole (conductive ground through hole)
Bypass capacitor 201
Child 1, R2 Resistor element L_Vddr, L_VddrA Power supply terminal coupling pattern L_GSLD Ground shield wiring

Claims (19)

A semiconductor device in which a memory device and a data processing device capable of controlling access to the memory device are mounted on a first surface of a mounting board,
The mounting substrate has a two-layer conductive pattern structure in which a conductive pattern is formed on the first surface and the second surface on the back side thereof,
The memory device has a plurality of first power supply terminals, first ground terminals, first data terminals, first address terminals, and first control terminals as external connection terminals on two opposite sides of the package,
The data processing device has, as external connection terminals, the first power terminal, the first ground terminal, the first data terminal, the first address terminal, and the second control terminal corresponding to the first control terminal, the second ground terminal, A plurality of second data terminals, second address terminals and second control terminals;
The mounting board includes a power wiring pattern connecting the first power terminal and the second power terminal, a data wiring pattern connecting the first data terminal and the second data terminal, the first address terminal and the second address terminal. An address wiring pattern to be connected, and a control wiring pattern to connect the first control terminal and the second control terminal;
The mounting substrate has a ground plane formed with a conductive pattern on the second surface,
The first ground terminal and the second ground terminal are connected to the ground plane;
On the first surface of the mounting substrate, the power supply wiring pattern forms a plurality of spaced paths from the memory device to the data processing device, and the power supply wiring pattern, the data wiring pattern, the address wiring pattern, and the control wiring pattern Is a semiconductor device arranged in parallel in a non-intersecting state. The memory device has an arrangement in which the first data terminal is closer to the data processing device than the first address terminal and the first control terminal;
The semiconductor device according to claim 1, wherein in the data processing device, the second address terminal and the second control terminal are arranged so as to sandwich the second data terminal.   The semiconductor device according to claim 2, wherein the address wiring pattern and the control wiring pattern are arranged on the first surface of the mounting substrate so as to sandwich the data wiring pattern.   3. The semiconductor device according to claim 2, wherein a part of the address wiring pattern and the control wiring pattern is alternately distributed to another layer of conductive patterns according to an arrangement order of the first address terminals and the first control terminals. The mounting board has ground shield wiring formed between the address wiring pattern and the control wiring pattern on the first surface,
The semiconductor device according to claim 4, wherein the ground shield wiring is connected to the ground plane.   6. The wiring pattern formed on the second surface of the mounting board among the address wiring pattern and the control wiring pattern is arranged to overlap the ground shield wiring formed on the first surface of the mounting board. The semiconductor device described.   The semiconductor device according to claim 4, wherein the first power supply terminal and the first ground terminal are unevenly arranged in the first data terminal array.   The semiconductor device according to claim 7, wherein the data wiring pattern is bent to be equal in length.   The data processing device has a quad flat package type package, and a power terminal coupling pattern for coupling some of the plurality of second power terminals to each other on the second surface of the mounting substrate. The semiconductor device according to claim 1.   The data processing device has a ball grid array type package, and a power terminal coupling pattern for coupling some of the plurality of second power terminals to each other on the first surface of the mounting substrate. The semiconductor device according to claim 1. The data processing device includes a core circuit, and an external interface circuit for performing a signal interface between the core circuit and the outside,
The second power supply terminal and the second ground terminal supply operating power to the external interface circuit,
The data processing device has a third power supply terminal and a third ground terminal for supplying operating power to the core circuit,
The semiconductor device according to claim 9, wherein the second power supply terminal and the second ground terminal are disposed between the third power supply terminal and the third ground terminal.   In an arrangement in which the second power terminal and the second ground terminal are sandwiched between the third power terminal and the third ground terminal, the third power terminal is adjacent to the second power terminal, and the third ground terminal is 12. The semiconductor device according to claim 11, wherein the semiconductor device is adjacent to the second ground terminal, the third power supply terminal is adjacent to the second data terminal, and the third ground terminal is adjacent to the second data terminal.   In the arrangement in which the second power terminal and the second ground terminal are sandwiched between the third power terminal and the third ground terminal, the third power terminal is adjacent to the second ground terminal, and the third ground terminal is 12. The semiconductor device according to claim 11, wherein the semiconductor device is adjacent to the second power supply terminal, the third power supply terminal is adjacent to the second data terminal, and the third ground terminal is adjacent to the second data terminal. The data processing device includes a core circuit, and an external interface circuit for performing a signal interface between the core circuit and the outside,
The second power supply terminal and the second ground terminal supply operating power to the external interface circuit,
The data processing device has a third power supply terminal and a third ground terminal for supplying operating power to the core circuit,
A bypass capacitor mounted on the second surface of the mounting substrate;
A conductive ground through hole that penetrates the mounting substrate and connects one capacitor terminal of the bypass capacitor to the second ground terminal or the third ground terminal;
A conductive power supply through hole that penetrates the mounting substrate and connects the other capacitor terminal of the bypass capacitor to the second power supply terminal or the third power supply terminal;
The semiconductor device according to claim 9, wherein the conductive ground through hole is disposed closer to the memory device, and the conductive power supply through hole is disposed closer to the data processing device. The data processing device has a first input terminal for a reference voltage; the memory device has a second input terminal for a reference voltage;
The mounting board includes a first reference voltage generation circuit that supplies a reference voltage to the first input terminal and a second reference voltage generation circuit that supplies a reference voltage to the second input terminal. Semiconductor device.   The semiconductor device according to claim 15, wherein the first reference voltage generation circuit is disposed near a chip corner portion of the data processing device. A semiconductor device in which a memory device and a data processing device capable of controlling access to the memory device are mounted on a first surface of a mounting board,
The mounting substrate has a two-layer conductive pattern structure in which a conductive pattern is formed on the first surface and the second surface on the back side thereof,
The memory device has a first power supply terminal, a first ground terminal, a first data terminal, a first address terminal, and a first control terminal as external connection terminals on two opposite sides of the package, and the first data terminal is the first data terminal. Having an arrangement closer to the data processing device than one address terminal and the first control terminal;
The data processing device has, as external connection terminals, the first power terminal, the first ground terminal, the first data terminal, the first address terminal, and the second control terminal corresponding to the first control terminal, the second ground terminal, A second data terminal, a second address terminal, and a second control terminal, wherein the second address terminal and the second control terminal are disposed so as to sandwich the second data terminal;
The mounting board is arranged in parallel on the first surface, the power wiring pattern connecting the first power terminal and the second power terminal, the data wiring pattern connecting the first data terminal and the second data terminal, A semiconductor device comprising: an address wiring pattern that connects a first address terminal and a second address terminal; and a control wiring pattern that connects the first control terminal and a second control terminal.   In the first surface of the mounting substrate, the power supply wiring pattern has at least a path passing through a central portion and a path passing through the outermost part of the parallel path of the data wiring pattern, the address wiring pattern, and the control wiring pattern arranged in parallel. Item 18. A semiconductor device according to Item 17. A semiconductor device in which a memory device and a data processing device capable of controlling access to the memory device are mounted on a first surface of a mounting board,
The mounting substrate has a two-layer conductive pattern structure, the first surface has a signal wiring pattern and a power wiring pattern for connecting the memory device and the data processing device, and the second surface has a ground plane. Have
On the first surface of the mounting substrate, the power supply wiring pattern forms a plurality of spaced paths from the memory device to the data processing device, and the power supply wiring pattern and the signal wiring pattern are arranged in parallel in a non-intersecting state. The power supply wiring pattern is a semiconductor device having at least a path passing through a central portion of a parallel path of the signal wiring patterns arranged in parallel and a path passing through the outermost part thereof.

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