JP2004537871A - High performance network switch - Google Patents

Abstract

A backplane interface adapter with error control and redundant fabric for high performance network switches is provided. The redundant fabric transceiver of the backplane interface adapter properly and reliably receives the narrow input cells carrying data packets and enhances the adapter's ability to output wide striped cells to the switching fabric.

Description

【０１８３】
パケットは、ヘッダとデータ・ペイロードから成るセルにフォーマットされる。4バイトのヘッダは、4つのXAUIレーン上の1サイクルすなわち1行を必要とする。ヘッダは、現在ヘッダが転送されていることを示すK0特殊文字をレーン0上に有している。制御情報はヘッダのレーン1上で開始する。
【０１８４】
一態様では、IBT304は、2つのIPC/IGCバックプレーン・バスを受け入れ、1つの10Gbpsシリアル・ストリームに変換する。
【０１８５】
図22には、本発明の一態様によるバス・トランスレータの符号化プロセスの流れ図が示されている。プロセスは段階2202から開始し、ただちに段階2204に進む。
【０１８６】
段階2204で、IBT304は、それがパケットを受信するポートの種類を判定する。一態様では、各ポートはIPC/IGC構成要素からの4Gpsトラフィック向けに構成されている。プロセスはただちに段階2206に進む。
【０１８７】
段階2206で、IBT304は、それが処理するトラフィックの種類に基づいてセル・フォーマット・タイプを選択する。一態様では、IBT304は、部分的に段階2204でのポートの種類の判定に基づいて、セル・フォーマットの種類を選択する。プロセスはただちに段階2208に進む。
【０１８８】
段階2208で、IBT304は、前述のように、そのポートを介してインタフェース接続部から1つまたは複数のパケットを受信する。パケットが供給される速度は、パケットを送信する構成要素に依存する。プロセスはただちに段階2210に進む。
【０１８９】
段階2210で、IBT304は、段階2208で受信された1つまたは複数のパケットを解析し、それに含まれている情報を得る。一態様では、IBT304のパケット・デコーダは、パケットを解析し、パケットのペイロード部内に含まれている情報と、それぞれの所与のパケットのヘッダと共に含まれている制御または経路指定情報とを得る。プロセスはただちに段階2212に進む。
【０１９０】
段階2212で、IBT304は、段階2210の解析によって得られた情報を任意に格納する。一態様では、IBT304のメモリ・プールを用いて情報が格納される。プロセスはただちに段階2214に進む。
【０１９１】
段階2214で、IBT304は情報を1つまたは複数のセルにフォーマットする。一態様では、IBT304のセル・エンコーダは、1つまたは複数のパケットの解析によって得られた情報にアクセスする。この情報は、送信中のデータと、データがどこに送信されているかに関するスロット・状態情報（すなわち、制御情報）を含む。前述のように、セル・フォーマットは、情報に付加される特殊文字を含む。プロセスはただちに段階2216に進む。
【０１９２】
段階2216で、IBT304は、フォーマットされたセルを転送する。一態様では、IBT304のSERDESは、フォーマットされたセルを受信し、本発明のBIA302に転送できるように直列化する。プロセスは、特に指示がないかぎり先へ進む。
【０１９３】
図23A〜23Bにおいて、詳細流れ図は、本発明の一態様によるバス・トランスレータの符号化プロセスを示している。図23A〜23Bのプロセスは段階2302から開始し、ただちに段階2304に進む。
【０１９４】
段階2304で、IBT304は、それがパケットを受信するポートの種類を判定する。プロセスはただちに段階2306に進む。
【０１９５】
段階2306で、IBT304は、ポートの種類が、個々の種類であるか、またはいくつかの種類の組合せであるかにかかわらず、維持できるしきい値を超えているかどうかを判定する。言い換えれば、IBT304は、それが内部速度最大値に達することなく着信パケットの回線速度に一致させることができるかどうかをチェックする。一致させることができる場合、プロセスは段階2310に進む。一致させることができない場合、プロセスは段階2308に進む。
【０１９６】
段階2308で、IBT304がその最高レベルで動作することになると判定したと仮定すると、IBT304は、プロセスの後の段階でフォーマットされ転送されるセルの数をIBT304が減らすのを可能にする可変セル・サイズを選択する。一態様では、セル・フォーマットにより、受信された1つまたは複数のパケットの各々の整数倍数のセルが与えられる。他の態様では、IBT304は、パケットが完成するまで最大長のセルを供給できるようにする可変セル・サイズを与えるセル・フォーマットを選択する。たとえば、所与のパケットが2.3セル長である場合、3つのセルがフォーマットされるが、第3のセルは前の2つのセルのサイズの3分の1である。プロセスはただちに段階2312に進む。
【０１９７】
IBT304は、段階2310で、その最高レベルでは動作しないと判定した場合、IBT304がより低い処理オーバヘッドで情報を処理できるようになる一定のセル・サイズを選択する。プロセスはただちに段階2312に進む。
【０１９８】
段階2312で、IBT304は1つまたは複数のパケットを受信する。プロセスはただちに段階2314に進む。
【０１９９】
段階2314で、IBT304は1つまたは複数のパケットの各パケットの制御情報を解析する。プロセスはただちに段階2316に進む。
【０２００】
段階2316で、IBT304は、1つまたは複数のパケットの各々に関するスロット・状態情報を判定する。一態様では、スロット・状態情報は、部分的に制御情報、すなわち、1つまたは複数のパケットの各々の解析によって得られた制御情報から判定される。プロセスはただちに段階2318に進む。
【０２０１】
段階2318で、IBT304は、スロット・状態情報を格納する。プロセスはただちに段階2320に進む。
【０２０２】
段階2320で、IBT304は、1つまたは複数のパケットの各パケットのペイロードを解析し、それに含まれているデータを得る。プロセスはただちに段階2322に進む。
【０２０３】
段階2322で、IBT304は、1つまたは複数のパケットの各々の解析によって得られたデータを格納する。プロセスはただちに段階2324に進む。
【０２０４】
段階2324で、IBT304は制御情報にアクセスする。一態様では、IBT304のセル・エンコーダは、IBT304のメモリ・プールにアクセスして制御情報を得る。プロセスはただちに段階2326に進む。
【０２０５】
段階2326で、IBT304は1つまたは複数のパケットの各々の解析によって得られたデータにアクセスする。一態様では、IBT304のセル・エンコーダは、IBT304のメモリ・プールにアクセスしてこの情報を得る。プロセスはただちに段階2328に進む。
【０２０６】
段階2328で、IBT304は、現在構築されているセルの始めに特殊文字を挿入することによって各セルを構築する。一態様では、特殊文字はK0である。プロセスはただちに段階2330に進む。
【０２０７】
段階2330で、IBT304はスロット情報を挿入する。一態様では、IBT304は、スペース2194のような次のレーンにスロット情報を挿入する。プロセスはただちに段階2332に進む。
【０２０８】
段階2332で、IBT304は状態情報を挿入する。一態様では、IBT304は、予約ビット2196aのような、スロット情報に使用されるレーンの次のレーンに状態情報を挿入する。プロセスはただちに段階2334に進む。
【０２０９】
段階2334で、IBT304はデータを挿入する。プロセスはただちに段階2336に進む。
【０２１０】
段階2336で、IBT304は、フォーマットすべき追加のデータがあるかどうかを判定する。たとえば、所与のパケットに残りのデータがあるものとする。この場合、プロセスは段階2328に戻る。残りのデータがない場合、プロセスはただちに段階2338に進む。
【０２１１】
段階2338で、IBT304は（1つまたは複数のセルの）セル送信の終りを示す特殊文字を挿入する。一態様では、最後のセルが送信されたときの特殊文字はK1である。プロセスはただちに段階2340に進む。
【０２１２】
段階2340で、IBT304はセルを転送する。プロセスは、特に指示がないかぎり先へ進む。
【０２１３】
図24において、流れ図は、本発明の一態様によるバス・トランスレータの解読プロセスを示している。図24のプロセスは段階2402から始まり、ただちに段階2404に進む。
【０２１４】
段階2404で、IBT304は1つまたは複数のセルを受信する。一態様では、セルは、IBT304のSERDESによって受信され、IBT304のセル・デコーダに転送される。他の態様では、IBT304のSERDESは、セルの適切な順序を維持できるようにセルを一時保持する同期バッファまたはキューにセルを転送する。これらの段階については以下に、段階2406および2408に関して説明する。プロセスはただちに段階2406に進む。
【０２１５】
段階2406で、IBT304は1つまたは複数のセルを適切な順序に同期させる。プロセスはただちに段階2408に進む。
【０２１６】
段階2408で、IBT304は、任意に1つまたは複数のセルをチェックし、これらのセルがその適切な順序にあるかどうかを判定する。
【０２１７】
一態様では、段階2506、2508、および2510は同期FIFOによって実行される。プロセスはただちに段階2410に進む。
【０２１８】
段階2410で、IBT304は1つまたは複数のセルを解析して制御情報およびペイロード・データを得るプロセスはただちに段階2412に進む。
【０２１９】
段階2412で、IBT304は制御情報およびペイロード・データを格納する。プロセスはただちに段階2414に進む。
【０２２０】
段階2414で、IBT304は情報を1つまたは複数のパケットにフォーマットする。プロセスはただちに段階2416に進む。
【０２２１】
段階2416で、IBT304は1つまたは複数のパケットを転送する。プロセスは、特に指示がないかぎり先へ進む。
【０２２２】
図25A〜25Bには、本発明の一態様によるバス・トランスレータの解読プロセスの詳細流れ図が示されている。図25A〜25Bのプロセスは段階2502から始まり、ただちに段階2504に進む。
【０２２３】
段階2504で、IBT304は1つまたは複数のセルを受信する。プロセスはただちに段階2506に進む。
【０２２４】
段階2506で、IBT304は任意に1つまたは複数のセルをキューに格納する。プロセスはただちに段階2508に進む。
【０２２５】
段階2508で、IBT304は、セルが適切な順序で到着しているかを任意に判定する。適切な順序で到着している場合、プロセスはただちに段階2512に進む。適切な順序で到着していない場合、プロセスはただちに段階2510に進む。
【０２２６】
段階2510で、IBT304は、適切な順序が回復されるまで1つまたは複数のセルのうちの1つまたは複数を保持する。一態様では、セルが失われた場合、IBT304は、本明細書で説明するようにエラー制御機能を実行し、転送を中断し、かつ／または転送を再開させる。プロセスはただちに段階2514に進む。
【０２２７】
段階2512で、IBT304はセルを解析して制御情報を得る。プロセスはただちに段階2514に進む。
【０２２８】
段階2514で、IBT304はスロット・状態情報を判定する。プロセスはただちに段階2516に進む。
【０２２９】
段階2516で、IBT304はスロット・状態情報を格納する。プロセスはただちに段階2518に進む。
【０２３０】
一態様では、状態・スロット情報は、以下の表に示されているように構成情報を含む。

【０２３１】
一態様では、IBT304は構成レジスタを有している。構成レジスタは、バックプレーンおよびIPC/IGC宛先スロットをイネーブルするのに用いられる。
【０２３２】
段階2518で、IBT304はセルを解析してデータを得る。プロセスはただちに段階2520に進む。
【０２３３】
段階2520で、IBT304は、1つまたは複数のセルの各々の解析によって得られたデータを格納する。プロセスはただちに段階2522に進む。
【０２３４】
段階2522で、IBT304は制御情報にアクセスする。プロセスはただちに段階2524に進む。
【０２３５】
段階2524で、IBT304はデータにアクセスする。プロセスはただちに段階2526に進む。
【０２３６】
段階2526で、IBT304は1つまたは複数のパケットを形成する。プロセスはただちに段階2528に進む。
【０２３７】
段階2528で、IBT304は1つまたは複数のパケットを転送する。プロセスは、特に指示がないかぎり先へ進む。
【０２３８】
T．管理プロセスおよびエラー制御
この節では、バックプレーン内のシリアル・リンクおよびクロス・ポイント・スイッチで起こる可能性のあるエラー状態と、本発明の様々なエラー制御態様について説明する。本発明の様々な回復ルーチンおよびリセット・ルーチンについても説明する。
【０２３９】
本明細書で説明するルーチンは一般に、以下の性質を有するエラーを検出し、防止し、そのようなエラーから回復するように構成される。
【０２４０】
1）リンク・エラー：リンク・エラーは、SERDES内のビット・エラーまたはバイト整列問題の結果として起こる。クロックがデータ・ストリームから回復されるので、十分なデータ遷移がない場合にバイト整列問題が起こる可能性がある。ビット・エラーは回線上の外部ノイズの結果として起こる可能性がある。SERDESは、レーン1のSOP文字などの例外条件を検出することもでき、そのような条件をリンク・エラーとしてマークすることができる。
【０２４１】
2）レーン同期エラー：レーンは、10Gbps SERDESを構成する4つのシリアル・リンク間の1つのシリアル・リンクとして定義される。本明細書の他の個所で説明するように、統合された10Gbpsストリームがコア論理に与えられるように伝送線スキューを補償して各レーンを同期させるように、SERDESコア内に4つの深いFIFOがある。FIFOがオーバフローまたはアンダーフローし、その結果レーン同期エラーが起こる可能性がある。レーン同期シーケンスが整列問題を引き起こす場合もある。
【０２４２】
3）ストライプ同期エラー：ストライプ同期エラーとは、本発明による切替えファブリックを介して複数のストライプにわたって送信されるデータのワイド・セルのフローにおけるエラーを指す。このようなストライプ同期エラー（ストライプ同期エラー状態または単にエラー状態とも呼ばれる）は、クロス・ポイントに至るシリアル・パイプまたはクロス・ポイントからのシリアル・パイプのリンク・エラーまたはクロス・ポイント自体のエラーによって起こる可能性がある。
【０２４３】
一態様では、受信側BIAは、送信元およびストライプに応じてソートされる深いFIFO（56個のFIFOや64個のFIFOなど）を含む。ストライプ同期エラーは、FIFOを監視し、ストライプ化データ・パス内の1つまたは複数のFIFOのオーバフローおよび／またはアンダーフローを検出することによって検出することができる。他の状況では、各ストライプの同期がまったくとれなくなることがある。一回復態様では、いくつかまたはすべてのXPNTモジュールが独立に調停を行い、すなわち、各XPNTモジュールが、本明細書の他の個所で説明するように独立に動作し、影響を受けるFIFOをクリアして、既知の状態から回復する。
【０２４４】
当業者には少なくとも本明細書の開示に基づいて明らかになるように、他のエラー状態およびエラー状態の組合せが可能である。
【０２４５】
これらのエラー状態を検出するルーチンおよび防止するルーチンについて、以下に概略的に説明し、その後、本発明の詳細な態様に関して説明する。
【０２４６】
一般に、本発明は、図26に示されているようにバス・トランスレータを管理することができる。図26において、流れ図は、本発明の一態様によるバス・トランスレータの管理プロセスを示している。図26のプロセスは段階2602から始まり、ただちに段階2604に進む。
【０２４７】
段階2604で、IBT304は内部構成要素のステータスを判定する。プロセスはただちに段階2606に進む。
【０２４８】
段階2606で、IBT304は、その外部構成要素とのリンクのステータスを判定する。プロセスはただちに段階2608に進む。
【０２４９】
段階2608で、IBT304は、内部構成要素と外部構成要素の動作を監視する。プロセスはただちに段階2610に進む。
【０２５０】
段階2610で、IBT304は、管理コマンド用のレジスタを監視する。プロセスはただちに段階2612に進む。
【０２５１】
段階2612で、IBT304は、指示に応じて所与の構成要素のリセットを実行する。プロセスはただちに段階2614に進む。
【０２５２】
段階2614で、IBT304は所与の構成要素の動作を構成する。プロセスは、特に指示がないかぎり先へ進む。
【０２５３】
一態様では、BIA302の受信側で検出されたあらゆるエラーが、BIA302からXPNT202上で受信されるエラーに関して本明細書で説明するエラー制御方法と同一の方法で処理される。ある条件の下ではBIA302が宛先スロットを知ることができない動作態様では、BIA302によって以下のプロセスが実行される。
【０２５４】
a．パケットのアボート（AOP）信号をすべてのスロットに送信する。
【０２５５】
b．エラーが解消され、すなわち、バッファがクリアまたはフラッシュされるのを待つ。
【０２５６】
c．バッファがクリアされた後、SOPによって第1のK0トークンに同期してデータの受付けを開始する。
【０２５７】
IBT304の受信側でエラーが検出された場合、エラーは、それがBIA302によってIBT304から見られている場合と同様に処理される。以下のプロセスが使用される。
【０２５８】
a．下流側IPC/IGCのすべてのスロットにAOPを送信し、進行中のあらゆるパケットを終了させる。
【０２５９】
b．バッファが充填され、エラーを発生させたデータをクリアするのを待つ。
【０２６０】
c．エラーが解消された後（バッファがフラッシュされた後）K0トークンに同期してデータの受付けを開始する。
【０２６１】
（1）BIA管理モジュール
一態様では、図6の管理モジュール676は、本発明の監視・検出・補正機能を実行する。特に、管理モジュール676はストライプ同期エラーに対処する。図28Aに示されれているように、管理モジュール676はレベル・モニタ2806、ストライプ同期エラー検出器2808、制御文字（K2）存在トラッカ2810、およびフロー・コントローラ2812を含んでよい。レベル・モニタ2806は、FIFOをチェックし、各FIFO内のデータ量および／または特定のストライプおよび送信元（スロットや、スロットの特定の送信元パケット・プロセッサなど）に関連するグループFIFO内のデータ量を判定する。
【０２６２】
ストライプ同期エラー検出器2808は、レベル・モニタ2806によって監視されたFIFOの状態に基づいてストライプ同期エラーを検出する。ストライプ同期エラーは、本発明による切替えファブリックを介して複数のストライプにわたって送信されるデータのワイド・セルのフローにおける任意のエラーであってよい。このようなストライプ同期エラーは、クロス・ポイントに至るシリアル・パイプまたはクロス・ポイントからのシリアル・パイプにおけるリンク・エラーあるいはクロス・ポイント自体のエラーによるエラーであってよい。説明を明確にするために、送信側BIAからクロス・ポイントに至るシリアル・パイプのリンク・エラーを「着信リンク・エラー」と呼び、クロス・ポイントから受信側BIAに至るシリアル・パイプのリンク・エラーを「発信リンク・エラー」と呼ぶ。ストライプ同期エラーが検出されると、ストライプ同期エラー検出器2808は信号をフロー・コントローラ2812に送信する。フロー・コントローラ2812は次いで、適切な回復ルーチンを開始し、切替えファブリック内の各ストライプにわたるデータ・フローを再同期させる。特に、このような回復ルーチンは、切替えファブリック内の各ストライプにわたる制御文字（特殊K2文字など）を送信することを含んでよい。制御文字（K2）存在トラッカ2810は、BIAにおけるデータ・フローで受信される特殊K2文字を監視する。フロー・コントローラ2812は、管理モジュール676および管理モジュール内の各モジュールの制御論理も構成している。フロー・コントローラ2812により、管理モジュール676の各モジュールは、本発明の様々なFIFO、BIA、XPNT、および他の構成要素のステータスに関する情報を送受信することによって、本明細書で説明する各モジュールの機能を実行することができる。以下に、ストライプ同期エラーの検出およびこのエラーからの回復の例について、さらに、図28Bに関して説明する。
【０２６３】
図28Bは、本発明による、5つのクロス・ポイント（sXPNT）2856A〜2856Eを介してスロット2852に結合されたスロット2852、2854を有するスイッチ2800Bを示す図である。スロット2852は、1組の同期受信キューまたはFIFO2860を含んでいる。シリアル・リンク2853は、スロット2852とクロス・ポイント2856Aを結合している。シリアル・リンク2857は、クロス・ポイント2856Aとスロット2858を結合している。スロット2852、2854をそれぞれスロット0およびスロット1とも呼び、スロット2858をスロット2とも呼ぶ。説明を明確にするために、この例では2つのスロットのみが示されているが、他のスロットを追加することができる。
【０２６４】
データのワイド・セルがスロット0および1からストライプ0〜4にわたりそれぞれのクロス・ポイント2856A〜2856Eを介してスロット2858に送信される例を考える。スロット0 2852とxpnt0 2856Aの間のリンクが破壊されたときにある種のエラーが起こる可能性がある。このような場合、xpnt0 2856Aは、送信元スロット0 2852にエラー信号を送り返させる破壊されたリンクを検出する。これによってスロット0 2852は、トラフィックの送信を停止し、K2シーケンスを送出する。xpnt0 2856Aはすべての宛先にアボート・セル（AOP）を送信し、エラーが発生したことをこれらの宛先に通知することができる。一態様では、これはエラーが検出された直後に行われる。
【０２６５】
他の態様では、xpnt1 2856Bからxpnt4 2856Eが依然としてスロット0 2852およびスロット1 2854からスロット2 2858にデータを送信し、一方、スロット0 2852とxpnt0 2856Aの間でリンク2853が破壊されているためxpnt0 2856Aがスロット1 2854からのみデータを送信する状況が瞬間的に存在する。このため、ストライプ0／スロット1リンクに対応するスロット2 2858内の同期キューは、他のストライプよりも多くのデータをスロット1 2854から受信するためオーバフローする恐れがあり、ストライプ0／スロット0 2852に対応するスロット2 2858内のキューでは、このリンクが破壊されているためにアンダーフローが起こる恐れがある。図31は、スロット2内のFIFO 2862に存在するデータの各レベルにおいて着信リンク2853内のこのようなエラー状態がどれだけ明白であるかを示している。図31は、ストライプおよび送信元スロットによってソートされた10個のFIFO 2862を示している。この例では、5つのストライプ0〜4および2つのスロット0および1が示されている。図31に示されているように、着信リンク・エラーによって、ストライプ0／スロット1リンクに対応するスロット2 2858内の同期キューは、他のストライプよりも多くのデータをスロット1 2854から受信するためオーバフローする恐れがあり、ストライプ0／スロット0 2852に対応するスロット2 2858内のキューでは、リンク2853が破壊されているためにアンダーフローが起こる恐れがある。
【０２６６】
管理モジュール676は、以下のようにこの種のストリップ同期エラー条件を検出することができる。レベル・モニタ2806は各FIFO2862のレベルを監視する。ストライプ同期エラー検出器2808は次いで、格納されているFIFOのレベルにおけるオーバフローおよび／またはアンダーフロー条件の存在を検出する。着信リンク・エラーのこの例では、ストライプ同期エラー検出器2808は、ストライプ0／スロット0用のFIFOにおけるアンダーフロー条件およびストライプ0／スロット1用のFIFOにおけるオーバフロー条件の発生を検出する。ストライプ同期エラー検出器2808はフロー・コントローラ2812に信号を送信する。フロー・コントローラ2812は次いで、適切な回復ルーチンを開始し、切替えファブリック内の各ストライプにわたるデータ・フローを再同期させる。特に、このような回復ルーチンは、切替えファブリック内の各ストライプにわたるスロット0からの制御文字（特殊K2文字など）を送信することを含んでよい。制御文字（K2）存在トラッカ2810は、BIAにおけるデータ・フローで受信される特殊K2文字を監視する。
【０２６７】
上述の例では、スロット0 2852は、各キューが同期できるようにするK2シーケンスを送出できるときにはK2シーケンスを送出する。SOPと共にスロット0 2852から送信される第1のK0文字で同期が行われ、言い換えれば、K2の後の最初の新しいパケットに対する同期が行われる。スロット2 2858内のスロット1／ストライプ0に対応する同期キューがオーバフローする可能性があるので、スロット1 2854からのデータの送信を停止し、したがって、スロット0 2852リンクの障害の結果としてのスロット1 2854からのトラフィックが行われないようにし、スロット1 2854からのデータに対して同期を維持するフロー制御イベントがスロット2 2858からxpnt0 2856Aに送信される。
【０２６８】
他の例では、XPNT0 2856Aが動作を停止し、もはや動作できなくなる。このような場合、図28Bに示されているスイッチが故障する。後述のように、本発明の冗長スイッチ・ファブリックおよび冗長ファブリック・トランシーバ（RFT）が存在するため、システム全体は依然として機能する。このような場合、RFTは、リンク障害を検出することができ、以下に概略的に説明する各段階に従って他のスイッチのファブリックに切り替える。
【０２６９】
他の例では、xpnt0 2856Aとスロット2 2858の間のリンク2857が破壊される。このような場合、スロット2におけるBIAが破壊を検出する。一態様では、以下に本発明の態様に関して説明するように、BIAのRFTが破壊を検出する。BIAのフロー・コントローラ2812は、xpnt0 2856Aにフロー制御イベント／信号を送り返し、この信号がスロット0 2852、スロット1 2854、およびシステムに存在するあらゆるスロットに伝搬する。これによって送信元スロットはスロット2 2858へのトラフィックの送信を停止することができる。これらのスロットは依然として、スロット2 2858と同様の他の宛先スロットにトラフィックを送信することができる。一方、BIAは、それが受信している部分的なパケットを中断し、K2シーケンスがリンクを回復するのを待つ。本明細書で説明するように、BIAは、K2に続く最初のSOPに同期する。K2に続く最初のSOPの存在は、制御文字存在トラッカ2810によって検出することができる。
【０２７０】
管理モジュール676の機能について、さらに、図29に関して説明する。図29では、ストライプ化セル・トラフィックの同期を維持するルーチンを示す流れ図について説明する。
【０２７１】
段階2902で、モジュール676は、所定数のサイクルにわたってすべてのレーンにおいてストライプ化セルで共通の制御文字を送信する。一態様では、システムを介していくつかの共通制御文字が送信される。
【０２７２】
段階2904で、モジュール676は、ストライプ受信同期キューで受信された共通制御文字を評価する。モジュール676は、受信された共通制御文字を評価し、システムを再同期しているかどうかを判定する。
【０２７３】
段階2906で、モジュール676は再同期条件を判定する。システムが再同期している場合、ルーチンは段階2910に進む。システムが再同期していない場合、システムは段階2908に進む。一態様では、モジュール676は、FIFOがすべて空であるか、または同時にクリアされているかどうかを判定する。他の態様では、モジュール676は各FIFOの状態ビットをチェックする。
【０２７４】
段階2908で、モジュール676はエラー・メッセージまたはその他の管理信号を生成する。一態様では、モジュール676は、システムの他の構成要素が新たに回復措置を開始するようにエラー・メッセージを生成する。
【０２７５】
段階2910で、モジュール676は、段階2902に戻り、エラー条件またはルーチン2900を開始する管理コマンドを受信するのを待つ。
【０２７６】
モジュール676の他のルーチンが図30に示されている。図30において、流れ図（ルーチン）3000は、バックプレーン切替えファブリック内のクロス・ポイント・スイッチを介した非同期トラフィック・フローに対するルーチンを示している。一態様では、ルーチン3000によって、モジュール676は、ルーチン2900がいつ必要であるかを判定する。
【０２７７】
段階3002で、モジュール676はストライプ受信同期キューのレベルを監視する。一態様では、レベル・モニタ2806はモジュール676内でこの機能を実行する。
【０２７８】
段階3004で、モジュール676は、オーバフローおよび／またはアンダーフロー条件などの非同期キューしきい値が検出されたかどうかを判定する。一態様では、ストライプ同期エラー検出器2808はモジュール676内でこの機能を実行する。非同期キューしきい値が検出された場合、プロセスは段階3006に進む。非同期キューしきい値が検出されない場合、プロセスは段階3002に進む。一態様では、モジュール676が、他のシステムによって受信し将来の参照用に記録することのできるエラー・メッセージや信号を送信することはない。
【０２７９】
段階3006で、モジュール676は、非同期メッセージ、または同期が失われたことを本発明の他の構成要素に知らせる他の管理信号を生成する。一態様では、フロー・コントローラ2812は送信側SXPNTに信号を送り返し、この信号がさらにRFTに送り返され、RFTは、本明細書の他の個所で説明するように本発明のK2シーケンスをインスタンス化することができる。
【０２８０】
段階3008で、モジュール676は、すべてのレーンにわたるストライプ化セル・トラフィックに対する再同期ルーチンを開始する。一態様では、モジュール676は図29のルーチンを開始する。
【０２８１】
管理モジュール676、ならびにレベル・モニタ2806、ストライプ管理エラー検出器2808、制御文字（K2）存在トラッカ2810、およびフロー・コントローラ2812のうちのどれかをソフトウェア、ファームウェア、ハードウェア、またはそれらの組合せで実施することができる。さらに、管理モジュール676、ならびにレベル・モニタ2806、ストライプ管理エラー検出器2808、制御文字（K2）存在トラッカ2810、およびフロー・コントローラ2812の各々で実行される機能について、都合上モジュールまたはブロックに関して説明する。しかし、このようなモジュールの境界およびモジュール間の機能の分散は例示的なものであり、本発明を制限するものではない。管理モジュール676、ならびにレベル・モニタ2806、ストライプ管理エラー検出器2808、制御文字（K2）存在トラッカ2810、およびフロー・コントローラ2812の各々の機能を1つのモジュールとして組み合わせることも、モジュールの任意の組合せにおいて分散させることもできる。
【０２８２】
（2）冗長ファブリック・トランシーバ
以下に、本発明の他の詳細な態様について、モジュール676の機能を実現する1つまたは複数の冗長ファブリック・トランシーバ（RFT）の実現態様に関して説明する。
【０２８３】
本発明の態様によれば、本明細書で説明する切替えシステムにおいて切替え冗長性をもたらすために1つのSBIA ASICと2つの切替えファブリック・モジュール（SFM）との間にRFT ASICが設けられる。
【０２８４】
図32A〜32Bはスイッチ・ファブリックの基本的な接続を示している。図32Aにおいて、図3200Aは非冗長切替えシステムを示している。ブレードA 3202はスイッチA 3204を介してブレードA 3206と通信する。ブレードAとブレードBは共に、入出トラフィックに対処する。図32Bで、図3200Bは冗長切替えシステムを示している。ブレードA 3202は、それぞれ2つのスイッチA 3204およびB 3205を介してブレードB 3206と通信する。マルチプレクサ（MUX）3208は、スイッチ3204および3205からの2つの信号の一方を選択する。
【０２８５】
図32Bの冗長切替えの場合、ファブリック・アクティブ3210はすべてのスレーブ・モジュール（入出）に信号を供給する。一態様では、バックプレーン上でポイント・ツー・ポイント・シリアル・リンクが使用される。この冗長手法は、非冗長手法の2倍のシリアル・リンクを使用する。したがって、入モジュール3202は、アクティブSFMに着信トラフィックを送信し、待機SFMにアイドル・トラフィック・パターンを送信する。一態様では、アクティブSFMはスイッチ3204であり、待機SFMはスイッチ3205である。出ブレード3206はこれらのSFMからトラフィックの2つのデータ・パスを受信する。出ブレード3206は、ファブリック・アクティブ3210の指示に応じてアクティブ信号を選択する。
【０２８６】
したがって、本発明のRFTは、冗長切替えを行い、以下のタスク、すなわち、i）マルチプレクサおよびデマルチプレクサとしての動作、ii）フロー制御に対処するための、符号化された送信元／宛先スロット情報に基づくトラフィックのソート、iii）フロー制御生成、iv）SERDES、およびv）エラー処理を実行することができる。このため、RFTは、すでに本明細書でモジュール676に関して説明した機能を実行する本発明の実現態様である。
【０２８７】
図33Aは、RFTが冗長システムで実施される一態様を示す詳細図3300Aである。図示のように、切替えブレード（SFM-A）3302および切替えブレード（SFM-B）3304は、入出ブレード（スレーブ・モジュール）3308に結合されたバックプレーン3306に結合されている。ブレード3302および3304はそれぞれ、データ・パスを介してデータを送受信するSXPNTを含んでいる。図33Aに示されているように、ブレード3302はSXPNT3310A〜3310Eを含み、ブレード3304はSXPNT3312A〜3312Eを含んでいる。SXPNT3310A〜3310Eおよび3312A〜3312Eの各群はそれぞれ、データ・パス3311A〜3311Eおよび3313A〜3313Eに結合され、バックプレーン接続部3306を介してブレード3308内の1つまたは複数のRFT 3316A〜3316Eに結合されている。
【０２８８】
ブレード3308内に、一態様では、受信される各ストライプごとに1つのRFTがある。RFT3316A〜3316Eは、受信されたデータをSBIA3320に転送する。他の態様では、1つのRFTはXAUIリンク（たとえば、15個のリンク、切替えブレードからの10個のリンク、SBIAからの5個のリンク）のブリッジを形成する。ある信頼できる態様では各XAUIリンクごとに4個のSERDESが必要であるため、このような実現態様では数十個のSERDESが必要になる可能性が高い。さらに、使用するRFTが1つであると、この1つのRFTがすべてのトラフィックに対処するのでシステムにバルヌラビリティが導入される可能性がある。したがって、5個のRFTモジュールの図示の態様では、処理作業負荷が論理的に分割される。
【０２８９】
図33Bは、本発明の一態様によるRFTの図3300Bである。図33Bには、SXPNT3310Aおよび3312Aからのストライプ0トラフィックに対してRFT3316Aが実施されるのと同様にRFT3300Bが実施されることが示されている。本明細書の他の個所で説明するように、SERDES3350および3352は、データ・インタフェースを形成し、図33Bに示されているように、それぞれSYNCHQ FIFO 3354および3356にトラフィックを経路指定する。
【０２９０】
一態様では、受信されたシリアル・データデータは、本明細書の他の個所で説明するように、SERDESによってパラレル・データに変換される。このデータと共に、着信データ・ストリームからクロックを回復することができる。したがって、各SERDESは、データから回復されたクロックを生成する。一態様では、FIFO3354および3356は、FIFOデータ・ストリームに対してアイドル文字の追加および／または削除を行うことによって、データの送受信に対するクロック補償を行う。FIFO3354とFIFO3356は共にMUX3358にデータを供給する。MUX3358は着信トラフィックを組み合わせ、発信トラフィックを分割し、冗長ストライプにデータ／制御信号とフロー制御信号の両方を与える。
【０２９１】
一態様では、すべてのトラフィックはアップリンク／ダウンリンク論理用の対称アーキテクチャに経路指定される。このアーキテクチャは、構成要素3360、3362、および3364、さらに構成要素3366、3368、および3370によって図33Bに示されている。BIA_RX3370およびBP_RX3360は、直列化解除され同期させられたパケット・データをFIFOから受信する。SYNCQ FIFO3372は、上述のFIFO3354および3356と同じ機能を実行するが、SERDES3374に関しては、BIA_RX3370が、データを、符号化された宛先スロット番号に基づいてUPLINK_RAM3368内に7つの論理データ・キューとしてソートする（たとえば、7つのキューはそれぞれの異なる宛先を有するパケットをソートするのに用いられる）。同様に、BP_PXは、データを、符号化された送信元スロット番号に基づいてDOWNLINK_RAM3362内にソートする。
【０２９２】
一態様では、SERDES3350、3352、および3374における呼出し時間は、上述の7つの論理データ・キューでトラフィックを減速させることによって補償される。
【０２９３】
BIA_TX3364モジュールとBP_TX3366モジュールは共に、それぞれダウンリンク／アップリンクRAM3362および3368からの読取り動作を調停し、送信されるデータを構成する。
【０２９４】
RFTレジスタ3376は、モジュール676から管理できる内部レジスタにアクセスすることができる。RFT3300Bの各モジュールの動作は、モジュール3376の各レジスタに設定されたパラメータに依存する。一態様では、モジュール3376は、RFT3300Bの各モジュールのステータスに関する情報をモジュール676に与える。
【０２９５】
上記に図33Aに関して説明したように、バックプレーンは切替えファブリック・モジュールとスレーブ・モジュールとの接続を確立する。一態様では、この接続は、i）シリアルTXとシリアルRXの対、ii）フロー制御データおよび同期、iii）クロス・ポイント・エラー信号、インターセプト信号、ファブリック・アクティブ信号などであるが、これらに限定されない制御信号、およびiv）クロック分散の各信号を含む。
【０２９６】
パケット符号化方式について、上記のI節およびJ節に関して詳しく説明し、ストライピング方式を図15Aに関して例示した。特にRFTに注目し、図26、図29、および図30のプロセスについて、本発明のRFTに関して説明した。
【０２９７】
一態様では、バックプレーンで転送されるペイロードの最大サイズは160バイトである（148バイトのデータ・マックス、10バイトの「セルの始め」（Start of Cell：SOC）制御情報、および2つの予約バイト）。この態様では、完全な160バイト転送を「セル」と呼ぶ。本明細書の他の個所で説明するように、セルはこの態様によって制限されない。したがって、1サイクルは単一の3.2nsクロック・パルス（すなわち、312.5MHZ）である。セル転送は、8連続サイクルにおいて20バイト「ブロック」で（図15Aに示されているように）行うことができる。
【０２９８】
「状態」バイトは、以下の表に示されているように割り当てることができる。

【０２９９】
この表の情報が、すでに図25A〜25Bに関し、IBTからBIAに関して説明した情報に類似していることに留意されたい。ここでは、BIAからXPNTについて議論する。各態様において、符号化方式用の3つの特殊K文字、すなわち、K0（SOC）、K1（EOP）、およびK2（ストライプ同期）が存在してよい。
【０３００】
K0は、すべての5つのストライプにわたるセルの第1のブロックである「セルの始め」を示す。
【０３０１】
K1は、セルの任意のブロックに現れることのできる「パケットの終り」を示す。これはRFTおよびSXPNTに対して透過的である。
【０３０２】
K2は、ストライプ同期シーケンスを符号化するのに用いられる。ストライプ同期では、すべてのレーンおよびすべてのストライプにわたってK2文字を送信する必要がある。一態様では、特殊文字は112回送信される。その後、同期キューのすべてのストライプが「イン・シンク（同期）」とマーク付けされる。数112が選択されたのは、それがこの態様では同期キューの深さに一致し、したがって、最後のK2が検出された後でキューに残っているデータがない場合、これをストライプ同期エラーとみなすことができるからである。本発明はこの態様によって制限されず、同期キューは異なる深さを有してもよい。
【０３０３】
当業者には本明細書に記載された開示に基づいて認識されるように、特殊文字を実施する機能は同期キューの充填／フラッシュである。一態様では、SBIAは、図34Aに示されているパターンを112回送信する。
【０３０４】
一態様では、状態フィールドが送信元スロット番号で符号化されると共に、セルがシーケンスの始めに近いかまたは終りをに近いかを示すのに1ビットが用いられる。たとえば、状態フィールドを送信元スロット番号で符号化することができると共に、セルがストライプ・シーケンスの（112回のうちの）最初の96回の転送の途中であるかどうか、またはこれが（112回のうちの）最後の16回のK2転送であり、その後有効なデータが送信されるかどうかを示すのに1ビットが用いられる。
【０３０５】
K2シーケンス同期ルーチンは、図34Bのフローチャート3450に示されている。K2シーケンスは、SBIAにおいて5つのストライプを同期させるために、連続するサイクルで到着する必要がある。これを保証するために、以下のルーチンが開始される。
【０３０６】
段階3452で、送信元SBIAがRFT/SXPNTの準備完了状態についてチェックする。
【０３０７】
段階3454で、RFT/SXPNTがその状態を返す。RFT/SXPNTの準備が完了している場合、ルーチンは段階3456に進む。RFT/SXPNTの準備が完了していない場合、ルーチンは段階3452に戻る。一態様では、送信元SBIAは所定の期間の後で再チェックを行うことができる。
【０３０８】
段階3456で、送信元SBIAはRFT/SXPNTにアイドル文字を送信する。一態様では、送信元SBIAは、宛先SBIAのバッファから残りのデータを引き出すのに十分な時間を宛先SBIAに与えるのに十分なアイドル文字を送信する。一態様では、送信元SBIAは768x2語のアイドル文字を送信する。
【０３０９】
段階3458で、送信元SBIAはRFT/SXPNTに特殊文字（K2）を送信する。一態様では、送信元スロット用のRFT/SXPNT内のFIFOは、K2が送信されるまでに空になるべきである。RFT/SXPNTは、K2シーケンスを受信したときに、FIFOが空でない場合、このシーケンスをSBIAが受信したデータのエラーとみなす。RFTは、データを首尾よく受信すると、K2シーケンスを送信する前に、SXPNTがデータを受信する準備が完了しているかどうかをチェックする。一態様では、K2シーケンスは、一度RFTからSXPNTに送信されると、シーケンス全体が送信されるまで停止しない。一態様では、112語のK2文字が送信される。
【０３１０】
段階3460、3462、および3464は上述の状況を示している。
【０３１１】
段階3466で、送信元SBIAは、RFT/SXPNTにさらにアイドル文字を送信し、バッファから残りのK2文字をクリアする。一態様では、送信元SBIAは512x2語のアイドル文字を送信する。
【０３１２】
一態様では、FIFOをクリアし本発明のシステムを再同期させるためにモジュール676によって周期的にルーチン3450が実行される。
【０３１３】
図34Bの議論では、SXPNTおよびSBIAのクロックの重要性が強調されている。というのは、このクロックは、ルーチン3450を適切に実行するために厳しいジッタおよび立上り時間要件を維持すべきであるからである。さらに、RFTおよびSXPNTのストライプ化性のため、常に同期を維持する必要がある。したがって、本明細書で説明するルーチン、およびエラー検出および回復のためのこれらのルーチンの様々な態様は、特に重要である。
【０３１４】
本発明の態様では、同期システムと非同期システムの両方を実施することができる。非同期システムでは、ファブリックを含むすべてのブレードが同じクロック送信元を使用する。クロック送信元は、ファブリック上に位置することができ、バックプレーンが純粋に受動的な構成要素として働くようにバックプレーンを横切って各スレーブ・モジュールに分散させることができる。
【０３１５】
冗長スイッチ・ファブリック・システムの一態様では、2つのシステム・クロックを2つのスイッチ・ファブリック・モジュールから1つのスレーブ・モジュールに送ることができる。スレーブ・モジュール上の回路はマスタ・クロックとして働く。マスタ・クロックがフェールオーバ・イベントで障害を起こした場合、他のクロックがマスタ・クロックになり、切替えはスレーブ・モジュール上の構成要素に対して透過的であるべきである。
【０３１６】
非同期システムでは、システムはブレード間でクロック・ドメインを結合解除する。このことは、今やあらゆるブレードがそれ自体のクロック送信元を有することを意味する。非同期システムを構成する目的は、MUXによって供給されるクロック信号によって課される厳しいジッタ要件をなくすことである。しかし、このシステムは、（スレーブ・モジュールにおける）両端でのインタフェース信号の再同期に関する新しい問題を引き起こす。
【０３１７】
SERDES信号の場合、すでに上記で説明したように、TXおよびRXがそれぞれの異なるクロック送信元を使用するときにRXクロック補償を行うある種の組込み機能がある。しかし、RX補償をイネーブルすると、SERDES内部の呼出し時間が長くなる。
【０３１８】
上述のフロー制御信号に関して、システムはファブリック上で制御論理を実施し、時分割多重（TDM）信号をパラレル信号に解読し、中央準備完了同期信号を不要にする。詳細な態様について以下に説明する。
【０３１９】
同期フロー制御実現態様の場合、SXPNTとRFTの間を通るフロー制御情報はTDMであり、共通同期信号によってタイム・スロットの始めを定める必要がある。クロック分散を追跡する中央同期信号は、システムのロバストネスを高める。
【０３２０】
図35は、RFTを含む同期フロー制御態様のブロック図3500である。ブレード・モジュール3502は5つのSXPNT3508A〜3508Eを含んでいる。フロー・コントローラ・モジュール3506は、本明細書で説明するように様々な信号を生成する。一態様では、モジュール3506はシステムの各構成要素にクロック信号を供給する。ブレード・モジュール3504は、バックプレーン接続部を横切ってRFT3510A〜3510Eに至る信号を受信する。RFTはSBIA3512との間で信号を送受信する。フロー・コントローラ・モジュール3504はRFT3510A〜3510EのそれぞれおよびSBIA3512にバックプレーンを横切って連結されている。
【０３２１】
一態様では、バックプレーンにわたる2組のフロー制御信号がある。他の態様では、2つよりも多くの信号がフロー制御に使用される。前者の態様では、以下の準備完了信号が実施される。
【０３２２】
a）受信準備完了：各SBIA3512は、特定のストライプにそれぞれの特定のスロットからパケットを送信するのを停止させる、各RFT3510A〜3510Eの専用1ビット準備完了信号を有する。各RFT3510A〜3510Eは、内部受信FIFO（たとえば、ダウンリンクRAM）内の利用可能な空間に基づいて特定の送信元SXPNT3508A〜3508Eからのパケットの受信を制御する専用1ビット準備完了信号も送信する。
【０３２３】
b）送信準備完了：各SXPNTは、宛先スロットでの輻輳状況を通知する、各RFT3510A〜3510Eの専用2ビット準備完了信号を有する。あらゆるSBIA3512は、宛先スロット用のトラフィックを停止する2ビット準備完了信号を各RFT3510A〜RFT3510Eから受信する。
【０３２４】
一態様では、RFT/SXPNTとRFT/SBIAの間のすべての送信準備完了信号および受信準備完了信号を同期させるのに共通同期信号が用いられる。たとえば、制限としてではなく、送信準備完了信号は、2ビットを用いて4つのスロット（8サイクル）における7つの状態を符号化し、受信準備完了信号は、1ビットのみを用いて7つのスロット（14サイクル）における7つの状態を符号化する。共通同期は、8と14の最小公倍数である56サイクルごとの同期パルスであってよい。もちろん、本発明はこれらのサイクル数に限らず、当業者には、異なる持続時間を実施できることが認識されよう。
【０３２５】
一態様では、各状態についてのタイム・スロットは、コア周波数の2分の1が78.125MHzであり、すなわち、コア周波数が156.25MHzである場合には、78.125MHzに設定することができる。タイム・スロットに2サイクル手法を用いる理由は、SBIA準備完了レジスタとSXPNT準備完了レジスタとの間のワイヤ／セル遅延に2サイクルのマージンが与えられるからである。
【０３２６】
図36は、SBIAがSXPNTからの準備完了信号をどのように解釈するかの時間流れ図である。同期パルスを用いてSBIAとSXPNTの両方の内部カウンタがリセットされる。例示のために図36に示されているように、カウンタの値が55または0であるとき、SXPNTは、スロット1および0に対応する準備完了状態を内部で送出する。カウンタが1または2に等しいとき、SXPNTはスロット2準備完了信号およびスロット3準備完了信号を符号化し、以下同様の動作が実行される。このパターンは8サイクルごとに繰り返される。言い換えれば、あらゆるスロットは、2つの同期パルスの間で7回符号化される。
【０３２７】
詳細な態様では、3サイクル後に、準備完了状態信号はバックプレーンを横切る。次いで、SBIAは準備完了信号に別の2サイクルの呼出し時間を付加する。したがって、カウントが5に等しいとき準備完了信号はSBIA内部にラッチされる。これによって、パスはSXPNTからSBIAまでの真のマルチサイクル・パスになる。
【０３２８】
RFTがSBIAとSXPNTの間に配置されたとき、フロー制御動作はそのまま実行される。しかし、SBIA/RFTおよびSXPNT/RFTの呼出し時間は、ハードウェア・トレースにおいて追加のマージンが残るようにプログラム可能である。したがって、本発明の態様では、システムの呼出し時間レベルを事前に決定し、したがって、システムの動作パラメータをよりうまく予想するためにオフセットを導入することができる。
【０３２９】
図35と同様に、図37は、非同期フロー制御を有する本発明の切替えシステムを示している。システム3700は、SXPNT3708A〜3708Eを有するブレード・モジュール3702と、RFT3714A〜3714Eを有するブレード・モジュールとを含んでいる。一態様では、図35と同様に、フロー・コントローラ・モジュール3706および3707はシステムの構成要素にクロック信号を供給することができる。
【０３３０】
SXPNT3708A〜3708EとRFT3714A〜3714Eとの間のフロー制御は、ブレード3702内の制御論理モジュール3710およびブレード3704内のモジュール3712を介して非同期に変更することができる。一態様では、制御論理モジュール3710は、ファブリック上に位置し、SXPNT3708A〜3708Eの同期フロー制御インタフェースとして働く。制御論理モジュール3710は、様々な信号を受信し、解釈し、送信することができる。一態様では、モジュール3710は以下の動作を実行する。
【０３３１】
a）2ビット送信準備完了信号を各SXPNT3708A〜3708Eからの7ビット準備完了信号として解読し、これらの準備完了信号を組み合わせて各RFT3714A〜3714Eへの7ビット送信スロット準備完了信号を生成する。
【０３３２】
「組み合わせる」とは、特定のスロットに対する準備が完了していないSXPNTがある場合、どのRFTもそのスロット用のパケットを送信することを許可されないことを意味する。これは、ストライプ間に独立のフロー制御を有する同期システムとは異なる。
【０３３３】
b）やはり5つのストライプからの組合せ準備完了信号であり、5つのSXPNT用の1ビット受信準備完了信号に符号化されている7ビット受信スロット準備完了信号を、RFTから受信する。
【０３３４】
本明細書で説明するRFT態様に関して、シリアル・リンクおよびバックプレーンで起こる可能性のあるエラー状態と、防止措置および回復措置について説明する。さらに、あるスイッチ・ブレードから他のスイッチ・ブレードに変更するフェールオーバ手順の態様について説明する。
【０３３５】
本発明のRFTモジュールは上述のエラーの受信側に位置してよい。RFTチップによって検出できるエラーの種類には以下のものが含まれる。
【０３３６】
a）リンク・エラー：これは、ビット・エラーまたはバイト整列エラーの結果として起こる可能性がある。一態様では、SERDESは、リンク・エラーを示す「/E」特殊文字（エラー通知文字）をパラレル・データ・パス上で送信すべきである。
【０３３７】
b）レーン同期エラー：これは同期FIFOオーバフロー／アンダーフローである。一態様では、SERDESは、受信側レーン同期エラーを示す「GLINK」信号を送信すべきである。
【０３３８】
c）フォーマット・エラー：これは、セルのフォーマットが正しくないために起こる。一態様では、レーン0以外のレーンに現れる「/K0」特殊文字がフォーマット・エラーを示す。
【０３３９】
d）XPNTエラー： これは5つのSXPNTチップからのワイヤまたは信号である。一態様では、この信号は、SXPNTにエラーがあるか、または受信データに問題があることを示している。
【０３４０】
RFTエラー処理ルーチンは前述のルーチン（たとえば、図29、図30、および図34Bのルーチン）に適合する。
【０３４１】
一態様では、SBIAからRFTへの送信において、RFTは、SBIAから受信されたデータにエラーを検出する。このエラーは、リンク・エラー、レーン同期エラー、およびフォーマット・エラーを含んでよい。エラーが検出された後、以下の手順（段階1〜4）を適用してエラーから回復することができる。
【０３４２】
1）SBIAにRFTエラー信号を送信する。SBIAは、セル境界でのデータの送信を停止し、RFTによってRFTエラーがアサート解除されるまでレーン同期シーケンスを繰り返す。一態様では、アサート解除された後、（たとえば、図34Bに関して説明したように）すべてのスロットに対してストライプ同期シーケンスが送出される。
【０３４３】
2）すべてのスロットにAOPを送信しアップリンクRAMをフラッシュする。受信されたデータでエラーが検出されたときは、符号化された宛先スロットが誤動作している可能性がある。したがって、すべての宛先スロットにアボート信号が送信され、すでに送信されたパケットが破棄される。
【０３４４】
3）バッファがクリアされ、したがってエラーがクリアされるのを待つ。
【０３４５】
4）ストライプ同期シーケンスおよびSOPがデータの受付けを開始するのを待つ。
【０３４６】
一態様では、SXPNTからRFTへの送信において、RFTは、それが接続されているSXPNTの1つから受信されたデータにエラーを検出する。このエラーは、リンク・エラー、レーン同期エラー、およびフォーマット・エラーを含んでよい。1つまたは複数のエラーが検出された後、以下の手順を適用してエラーから回復することができる。
【０３４７】
1）SXPNTがこのスロットにおいてさらにデータを受信するのを停止する。
【０３４８】
2）すべてのスロットについてSBIAにAOPを送信し、ダウンリンクRAMをフラッシュする。
【０３４９】
3）バッファがクリアされ、したがってエラーがクリアされるのを待つ。
【０３５０】
4）ストライプ同期シーケンスおよびSOPがデータの受付けを開始するのを待つ。
【０３５１】
本発明の態様では、RFTエラー信号は、SBIAがRFTへのパケット送信を停止するように、SBIAに、そのRFTがエラー状態にあることを通知する。この信号は、以下のエラー通知を含む。
【０３５２】
a）クロス・ポイント・エラー：これは、アクティブ切替えモジュール上の5つのSXPNTからのワイヤまたは結果である。
【０３５３】
b）ファブリック・アクティブ・エラー： このエラーは、「ファブリック」アクティブ」信号が両側で同時にアクティブまたはイナクティブになったときに起こる。
【０３５４】
c）SBIAから受信されたデータにおける検出されたリンク・エラー、レーン同期エラー、またはフォーマット・エラー。
【０３５５】
エラーが、切替えモジュールで検出されたか、または切替えモジュールに関係するものとみなされる場合、モジュール676は、現在の切替えモジュールをディスエーブルし、予備切替えモジュールがシステムのプロセスをアクティブに維持できるようにする機能を有している。
【０３５６】
一態様では、RFTは、SXPNTから受信されたデータにエラーを検出したときに、モジュール676内で行われているフロー制御を中断する割込み信号を生成することができる。モジュール676は次いで、SXPNTおよびRFT内のステータス・レジスタを読み取り、どんな種類のエラーが起こったかと、エラーを補正するためにどのルーチンをインスタンスかすべきかを判定する。
【０３５７】
割込み信号を生成することのできるエラーは、RFT内に割込みマスク・レジスタをプログラムすることによって事前に決定しておくことができる。これらのエラーには、a）コアからSERDESへの同期FIFOオーバフロー、b）SERDESからコアへの同期FIFOオーバフロー、c）リンク動作不能、e）符号エラー、および／またはフォーマット・エラー、ならびにf）XPNTエラーを含めてよいが、これらに限定されない。当業者には少なくとも本明細書に記載された開示に基づいて認識されるように、他のエラーを監視し事前に決定しておくことができる。
【０３５８】
モジュール676は、すべてのスレーブ・モジュールから割込み信号を収集し、一態様では、他の2ビット「ファブリック存在」信号も収集し、モジュール676のフェールオーバ決定手順を開始する。「ファブリック存在」信号は、対応する切替えモジュールが所定の位置にあることを示すことができる。たとえば、ユーザがある切替えモジュールを取り外した場合、対応する「ファブリック存在」信号はアサート解除される。
【０３５９】
モジュール676は、2ビット「ファブリック・アクティブ」信号を用いて、どのスイッチ・モジュールがトラフィックを送るかをすべてのスレーブ・モジュールに通知する。一態様では、モジュール676は、フェールオーバ手順を開始するために、まず予備スイッチ・モジュールをリセットし、2ビット信号を反転する。
【０３６０】
冗長切替え態様では、ネットワーク・スイッチは1つのアクティブ／作動切替えブレードと1つのアイドル／予備切替えブレードとを有している。これらの態様によれば、RFTは、アクティブ・ブレードにパケットを送信することができ、アイドル・ブレードにアイドル文字を送信することができる。作動切替えブレードの障害または作動切替えブレードが取り外されていることを、モジュール676が検出すると、RFTは、システムによって、2ビット「ファブリック・アクティブ」信号を用いてフェールオーバ状況を通知される。フェールオーバが起こると、新しい切替えブレードは、リセット後に初期状態にあると仮定される。モジュール676は、フェールオーバ・コマンドを発行する前に新しい切替えブレードのステータスをチェックする。
【０３６１】
RFTは常に、予備切替えブレードにレーン同期シーケンスを送信して正常なリンクを維持する。したがって、フェールオーバが起こったとき、予備切替えブレードを作動させる時間は不要になる。
【０３６２】
フェールオーバが起こったときは、フェールオーバ手順を実行して他の切替えブレードへの安全な遷移を保証することができる。以下に、本明細書で説明するルーチンの特定の態様について詳しく説明する2つのルーチン例を示す。
【０３６３】
一態様では、SBIAからRFTへの送信において、RFTは、「ファブリック・アクティブ」信号を監視することによってフェールオーバを検出する。
【０３６４】
1）SBIAにRFTエラー信号を送信する。SBIAは、セル境界でデータの送信を停止し、RFTエラー信号がアサート解除されるまでレーン同期シーケンスを繰り返す。アサート解除された後、すべてのスロットに対してストライプ同期シーケンスが送出される。
【０３６５】
2）アップリンクRAMをフラッシュする。
【０３６６】
3）バッファがクリアされ、したがってエラーがクリアされるのを待つ。
【０３６７】
4）ストライプ同期シーケンスおよびSOPがデータの受付けを開始するのを待つ。
【０３６８】
一態様では、SXPNTからRFTへの送信において、RFTは、「ファブリック・アクティブ」信号を監視することによってフェールオーバを検出する。
【０３６９】
1）すべてのスロットについてSBIAにAOPを送信し、ダウンリンクRAMをフラッシュする。SBIAは、AOPを受信すると、受信されたデータをストライプ同期の前に破棄する。
【０３７０】
2）バッファがクリアされ、したがってエラーがクリアされるのを待つ。
【０３７１】
3）ストライプ同期シーケンスおよびSOPがデータの受付けを開始するのを待つ。
【０３７２】
本発明の特徴によれば、システムの各ブレードのヒットレス切替えが可能である。語「ヒットレス」は、ファブリックの変更によるパケットの損失が生じないことを意味する。通常の状態で、ユーザがそれにもかかわらず、性能を高めるかまたはより安定させるためにファブリックの変更を望む場合がある。この場合、ユーザはパケットの不要な破棄を回避することを望む。さらに、アップグレード手順を使用するもう1つの理由は、ファブリックの試験である。少なくとも2つの手順、すなわち、デバッグおよび作成を用いて切替えを行うことができる。
【０３７３】
一態様では、第1の手順によって、モジュール676は、レジスタのプログラミングによって切替えイベントを制御することができる。
【０３７４】
1）まず、モジュール676は、構成レジスタ内の「ファブリック・イネーブル・モード」および「ヒットレス・イネーブル・モード」ビットに「1」をセットする。これによって、モジュール676は、レジスタのプログラミングによって新しいファブリックおよびヒットレス・モードをイネーブルすることができる。
【０３７５】
2）モジュール676は、「構成」レジスタ内の「ヒットレス・イネーブル」ビットをセットする。これによって、RFTは、損失のない切替えを行うモードになる。
【０３７６】
3）次いで、モジュール676は、たとえばRFTレジスタに対応するビットをセットすることによってBIA受信機をディスエーブルする。これによって、SBIAが抑制され、SBIAがRFTにさらにセルを送信するのが防止される。
【０３７７】
4）ある時間（SXPNTバッファおよびRFTバッファ内のすべてのパケットを送出するのに十分な時間。本明細書ですでに説明したように、モジュール676がこの持続時間を決定することができる。）が経過した後、モジュール676は、RFTレジスタ内の「ファブリック・アクティブ」ビットをセットすることによって新しいファブリックを選択する。
【０３７８】
5）モジュール676は次いで、SBIAがRFTへの新しいセルの送信を継続できるように（イネーブルされるように設定されるように）各ビットをクリアする。RFTは、データを破棄することなく新しいファブリックにセルを転送する。
【０３７９】
6）モジュール676は「ヒットレス・イネーブル」ビットをクリアして、RFTをフェールオーバ・モードにする。
【０３８０】
他の態様では、第2の手順として以下のルーチンが使用される。一態様では、RFT/SXPNTバッファ内のパケットを送出する切替えタイマはRFTに位置しており、SBIAトラフィックの減速は、上述のように自動的に行われる。この態様では、モジュール676が介入する必要はない。
【０３８１】
1）まず、本発明の一ハードウェア態様では、コマンド入力ピンを「ハイ」に駆動してヒットレス切替えをイネーブルすることができる。一ソフトウェア態様では、ヒットレス切替えをイネーブルするように「ヒットレス・イネーブル・モード」ビットおよび／または「スイッチ遅延イネーブル」ビットをセットすることもできることにも留意されたい。
【０３８２】
2）モジュール676は、減速の前に、「スイッチ遅延カウンタ」レジスタの値を求めることができる。これは、「ファブリック・アクティブ」信号がトグルされるときに切替えタイマをプログラムするのに用いられる。
【０３８３】
3）「ファブリック・アクティブ」入力ピンはすべてのRFTでトグルされ、各RFTは、SBIAトラフィックを減速させ、切替えタイマが満了するまで古い切替えファブリックにパケットを送信し続ける。
【０３８４】
4）タイマが満了したとき、RFTとSXPNTは共に、内部バッファ内のすべてのパケットを送信しているはずである。RFTは、新しいファブリックを作動させ、新しい切替えファブリックとの間でのパケットの送受信を開始する。
【０３８５】
5）上記の態様では、コマンド入力ピンが「ロー」に駆動され、ヒットレス切替えがディスエーブルされる。
【０３８６】
フェールオーバと切替えのどちらの場合でも、モジュール676が交換の前にまず新しいファブリックをリセットするよう示唆されることに留意されたい。SXPNTがリセット後にすべてのスロットに対してAOPを生成する（リンクが動作不能になるため）ので、モジュール676には、スイッチ・ファブリックを交換する前に十分な時間が与えられる。
【０３８７】
U．リセット手順および回復手順
SERDESを同期させるときは以下のリセット手順に従う。コアにリセットが適用されると、SERDESに対して外部リセットがアサートされる。SERDESに対するリセット・パルスの持続時間は10サイクル以下でよい。リセット・パルスの後、SERDESの送信機および受信機は定められた手順によって互いに同期する。SERDESは、コアがリセットを解除された後に同期すると仮定する。このため、コアに対するリセット・パルスは、SERDESコアに対するリセット・パルスよりもかなり大きくなければならない。
【０３８８】
コアは、コアを同期させる場合にソフトウェアによる対話に依存する。BIA302、600、IBT304、およびXPNT202は、リセットを解除された後、連続的にレーン同期シーケンスを送信する。受信機は、そのレーンが同期していることを示すソフトウェア可視ビットをセットする。ソフトウェアは、各レーンが同期していると判定すると、各ストライプの同期を試みる。これは、ストライプ同期シーケンスの連続的な送信をイネーブルするソフトウェアによって行われる。この場合も、BIA302の受信側は、それが特定の送信元スロットと同期していることを示すビットをセットする。ソフトウェアは、このことを判定すると、BIA302、XPNT202、およびIBT304に対する送信をイネーブルする。
【０３８９】
管理ブレード上に存在する管理ソフトウェアは、システム・メンテナンス作業に責任を負う。本発明の態様によれば、モジュール676は管理ソフトウェアについてのインスタンス化およびアクセスを行う。他の態様では、管理ブレードは、各スレーブ・モジュールおよび切替えモジュールに対する専用リセット信号を含む。
【０３９０】
一態様では、システム・リブート時に以下のリセット手順を実行することができる。
【０３９１】
1）コアにリセットが適用されると、SERDESに対して外部リセットがアサートされる。SERDESに対するリセット・パルスの持続時間は32サイクルより長くなければならない（156MHzクロックの場合）。
【０３９２】
2）リセット・パルスの後、SERDESの送信機および受信機は定められた手順によって互いに同期する。SERDESは、コアがリセットを解除された後に同期すると仮定することができる。。このため、コアに対するリセット・パルスは、SERDESコアに対するリセット・パルスよりもかなり大きくなければならない。
【０３９３】
3）コアは、コアを同期させる場合にモジュール676との対話に依存する。BIA、IBT、およびXPNTは、リセットを解除された後、連続的にレーン同期シーケンスを送信する。
【０３９４】
4）SERDESは、レーン同期ステータスをモジュール676から見えるようにする。
【０３９５】
5）モジュール676は、各レーンが同期していると判定すると、各ストライプの同期を試みる。これは、ストライプ同期シーケンスの連続的な送信をイネーブルするソフトウェアによって行われる。
【０３９６】
6）この場合も、BIAの受信側は、それが特定の送信元スロットと同期していることを示すビットをセットする。
【０３９７】
7）モジュール676は、このことを判定すると、BIA、XPNT、およびIBTに対する送信をイネーブルする。
【０３９８】
SBIA/SXPNTリセット手順と同様に、RFTは、モジュール676がその3つの10Gbps SERDESのそれぞれを個別にリセットするのを可能にする。SERDESがリセットされると、リンクは動作不能になり、SERDESから受信されたデータは破壊される。エラー回復プロセスは、前述のリンク・エラー処理と同じであってよい。
【０３９９】
リセットによるパケット損失を減らすために、以下の手順を適用する。
【０４００】
a）セル境界で送信側SERDESへのデータの送信を停止する。
【０４０１】
b）SERDESのリセット中にレーン同期シーケンスを送信する。
【０４０２】
c）データの送信を開始する（SERDESはリセット状態を解除される）。
【０４０３】
RFTは3つのSERDESを有するが、一態様では、2つのSERDESのみがパケットを転送し、1つのSERDESは待機モードである。ユーザが本体に1つの切替えファブリックのみを設置した場合、冗長SERDESの対応するSERDESトランシーバがなくなる。したがって、冗長SERDES用のリンクは常に動作不能になる。ユーザは、本体に切替えファブリックを設置することを望まない場合、冗長SERDESの電源を落としてエネルギーおよびサイクルを節約し、処理オーバヘッドを低下させることができる。このために、モジュール676はRFTの各レジスタのうちの「電力制御」レジスタにアクセスすることができる。
【０４０４】
IV．制御論理
上記にスイッチ100の動作に関して説明した機能は制御論理で実施することができる。このような制御論理は、ソフトウェア、ファームウェア、ハードウェア、またはそれらの任意の組合せで実施することができる。
【０４０５】
V．結論
本発明の特定の態様について上記に説明したが、これらの態様は一例としてのみ示されており、制限として示されたものではないことを理解されたい。当業者には、添付の特許請求の範囲に定義された本発明の趣旨および範囲から逸脱せずに、これらの態様の形態および詳細に様々な変更を加えられることが理解されよう。したがって、本発明の範囲は、上述の例示的な態様によって制限されるべきではなく、特許請求の範囲およびその均等物に従ってのみ定義されるべきである。
【図面の簡単な説明】
【０４０６】
【図１】本発明の態様による高性能ネットワーク・スイッチの図である。
【図２】本発明の態様によるブレードに結合されたクロス・ポイント・スイッチを有する切替えファブリックを示す高性能ネットワーク・スイッチの図である。
【図３Ａ】本発明の態様による図1の高性能ネットワーク・スイッチで使用されるブレードの図である。
【図３Ｂ】本発明の他の態様によるブレードの構成を示す図である。
【図４】本発明の態様によるポート・スライスを有するクロス・ポイント・スイッチのアーキテクチャの図である。
【図５】本発明の態様によるポート・スライスのアーキテクチャの図である。
【図６】本発明の態様によるバックプレーン・インタフェース・アダプタの図である。
【図７】本発明の態様による、バックプレーン・インタフェース・アダプタで受信されるローカル・シリアル・トラフィック用のトラフィック処理パスを示す図である。
【図８】本発明の態様による、バックプレーン・インタフェース・アダプタに結合された切替えファブリックの一例の図である。
【図９】本発明の態様による、バックプレーン・インタフェース・アダプタで受信されるバックプレーン・シリアル・トラフィック用のトラフィック処理パスを示す図である。
【図１０】本発明の態様による、バックプレーン・インタフェース・アダプタで受信されるローカル・シリアル・トラフィック用のトラフィック処理パスに沿って実行される動作段階のフローチャートである。
【図１１】本発明の態様による、バックプレーン・インタフェース・アダプタで受信されるバックプレーン・シリアル・トラフィック用のトラフィック処理パスに沿って実行される動作段階のフローチャートである。
【図１２】本発明の態様による、ワイド・ストライプ化セルを生成するルーチンのフローチャートである。
【図１３】本発明の態様による、ナロー・セルで使用されるナロー・セル・状態情報を示す図である。
【図１４】本発明の態様による、ワイド・ストライプ化セルを符号化するルーチンのフローチャートである。
【図１５Ａ】本発明の態様による、ワイド・ストライプ化セルを符号化する段階を示す図である。
【図１５Ｂ】本発明の態様による、ワイド・ストライプ化セルで使用される状態情報を示す図である。
【図１５Ｃ】本発明の態様による、ワイド・ストライプ化セルで使用されるパケットの終り符号化情報を示す図である。
【図１５Ｄ】本発明の態様による、ワイド・ストライプ化セルを複数のストライプで送信する際のセル境界整列条件の例を示す図である。
【図１６】本発明の態様による、ワイド・ストライプ化セルを複数のストライプで送信する際のパケット境界整列条件の例を示す図である。
【図１７】本発明の一態様によるバス・トランスレータのブロック図を示す。
【図１８】本発明の一態様による受信構成要素のブロック図を示す。
【図１９】本発明の一態様による送信構成要素のブロック図を示す。
【図２０】本発明の一態様によるバス・トランスレータの詳細ブロック図を示す。
【図２１Ａ】本発明の他の態様によるバス・トランスレータの詳細ブロック図を示す。
【図２１Ｂ】本発明の一態様による、バス・トランスレータの受信構成要素を有するデータ・パスの機能ブロック図を示す。
【図２１Ｃ】本発明の一態様による、バス・トランスレータの送信構成要素を有するデータ・パスの機能ブロック図を示す。
【図２１Ｄ】本発明の一態様による、バス・トランスレータのネイティブ・モード受信構成要素を有するデータ・パスの機能ブロック図を示す。
【図２１Ｅ】本発明の一態様によるセル・フォーマットのブロック図を示す。
【図２２】本発明の一態様によるバス・トランスレータの符号化プロセスの流れ図を示す。
【図２３Ａ−２３Ｂ】本発明の一態様によるバス・トランスレータの符号化プロセスの詳細流れ図を示す。
【図２４】本発明の一態様によるバス・トランスレータの復号プロセスの流れ図を示す。
【図２５Ａ−２５Ｂ】本発明の一態様によるバス・トランスレータの復号プロセスの詳細流れ図を示す。
【図２６】本発明の一態様によるバス・トランスレータの管理プロセスの流れ図を示す。
【図２７Ａ−２７Ｅ】本発明の一態様による、ワイド・セル符号化およびフロー制御条件に基づいてポート・スライス内のデータを処理するルーチンを示す。
【図２８Ａ】本発明の一態様による管理モジュールのブロック図を示す。
【図２８Ｂ】本発明の一態様によるクロス・ポイント・アーキテクチャのブロック図を示す。
【図２９】本発明の一態様による、ストライプ化セル・トラフィックの同期を維持するルーチンを示す。
【図３０】本発明の一態様による、バックプレーン切替えファブリックを有するクロス・ポイント・スイッチを通る非同期トラフィック・フローを検出するルーチンを示す。
【図３１】本発明の一態様による、ストライプおよび送信元ごとにソートされた受信側ブレード同期キューに存在するデータのレベルにおいて着信リンクにおけるエラー条件がどれだけ明白であるかの一例を示す。
【図３２Ａ−３２Ｂ】本発明の態様によるアーキテクチャの例のブロック図を示す。
【図３３Ａ】本発明の一態様による、冗長ファブリック・トランシーバによってイネーブルされるブレード・モジュールのブロック図を示す。
【図３３Ｂ】本発明の一態様による冗長ファブリック・トランシーバのブロック図を示す。
【図３４Ａ】本発明の一態様による5つのストライプにわたるセル文字を示す表を示す。
【図３４Ｂ】本発明の一態様によるK2（特殊文字）同期シーケンスに関するルーチンを示す。
【図３５】本発明の一態様による冗長ファブリック・トランシーバの同期フロー制御実現態様のブロック図を示す。
【図３６】本発明の一態様による、同期フロー制御実現態様の時間ドメイン多重化のタイミング図を示す。
【図３７】本発明の一態様による、冗長ファブリック・トランシーバの非同期フロー制御実現態様のブロック図を示す。【Technical field】
[0001]
Field of the invention
The present invention generally relates to network switches.
[Background Art]
[0002]
Related technology
A network switch is a device that performs a switching function (determines a physical path) in a communication network. In switching, information such as digital data packets and frames are transferred between entities in a network. Typically, a switch is a computer that has multiple circuit cards coupled to a backplane. Circuit cards are commonly referred to as "blades" in switching technology. The blades are interconnected by a "switch fabric". Each blade includes several physical ports that couple the switch to other network entities over various types of media such as Ethernet, Fiber Distributed Data Interface (FDDI), and Token Ring connections. Network entities include any device that sends and receives data on such media.
[0003]
The switching function performed by the switch typically includes receiving data from a network entity at a source port and forwarding the data to a destination port. The source port and destination port may be located on the same blade or on different blades. For "local" switching, the source and destination ports are on the same blade. Otherwise, the source and destination ports are on different blades, and switching requires transferring data from the source blade to the destination blade through the switch fabric. In some cases, data is provided to multiple destination ports on the switch. This is called multicast data transfer.
[0004]
The switch operates by examining the header information accompanying the data in the data frame. The header information includes the International Standards Organization (ISO) 7-layer OSI (Open Systems Interconnection). In the OSI model, switches typically route data frames based on lower level protocols such as Layer 2 or Layer 3. In contrast, routers generally determine the physical path of a data frame based on a higher level protocol, based on table lookups, or other forwarding routines or management configured to determine the physical path. Route by routine.
[0005]
Ethernet is a widely used low-layer network protocol that uses broadcast technology. Ethernet has six fields. These fields include the preamble, destination address, source address, type, data, and frame check sequence. For Ethernet frames, the digital switch determines the physical path of the frame based on the source and destination addresses. Standard Ethernet operates at a 10Mbps data signal rate. Another implementation of Ethernet, called "Fast Ethernet" (FE), has a data signal rate of 100 Mbps. Other implementations of FE operate at 10 Gbps.
[0006]
Digital switches typically have physical ports configured to communicate using a variety of protocols, each with a different data rate. For example, a blade in a switch may have any port that is a 10 Mbps port or a 100 Mbps port. The blade may have other ports that comply with optical standards such as SONET and are capable of data signal rates such as 10 Gbps.
[0007]
Digital switch performance is often evaluated based on criteria such as the number of physical ports present and the number of physical ports that can be switched without interrupting or slowing down data traffic. The limiting factor in the bit transfer capacity of many switches is the switch fabric. For example, one conventional switch fabric was limited to 8 gigabits per second per blade. In the eight-blade example, this is equivalent to 64 gigabits per second of traffic. It is possible to increase the data signal rate of a particular blade to over 8 gigabits per second. However, the switch fabric cannot handle this increased traffic.
[0008]
It is desirable to utilize new optical techniques to increase the port density on the blade and increase the data signal rate. However, there is a need for switches and switch fabrics that handle higher bit rates and provide a maximum total bit transfer capacity that is well above conventional switches.
DISCLOSURE OF THE INVENTION
[0009]
Summary of the Invention
The present invention provides a high performance network switch. The switching fabric uses serial link technology. In a switching fabric, a serial data stream is switched instead of a parallel data stream. The blade outputs a serial data stream in a serial pipe. The serial pipe may be some serial link that couples the blade to the switching fabric. The serial data stream represents a collection of incoming serial data streams supplied to each blade through a physical port. Each blade outputs a serial data stream having in-band control information in a plurality of stripes to the switching fabric.
[0010]
In one aspect, the serial data stream transfers packets of data in wide striped cells across multiple stripes. Wide striped cells are encoded. In-band control information is transferred in one or more blocks of the wide cell. For example, the initial block of the wide cell contains control and status information. Further, control information and status information are transferred in each stripe. In particular, control and status information is transferred in each sub-block of the initial block of the wide cell. Thus, control and status information is obtained in-band in a serial data stream (also called stripe). The control information is provided in-band and indicates traffic flow conditions such as beginning of cell, end of packet, abort, and other error conditions.
[0011]
A wide cell has one or more blocks. Each block extends over five stripes. Each block has a size of 20 bytes composed of 5 sub-blocks, each size being 4 bytes. In one example, a wide cell has a maximum size of 8 blocks (160 bytes) that can transfer 148 bytes of payload data and 12 bytes of in-band control information. Packets of data for full-duplex traffic can be transferred at a rate of 50 Gbps in each direction through one slot of a digital switch in a wide cell. According to one feature, choosing a maximum wide cell block size of 160 bytes determined by the inventor allows maintaining 4x10Gbps Ethernet (also called 4X10GE) line speed through the backplane interface adapter. . This line speed is maintained for Ethernet packets having a range of sizes allowed by Ethernet, including but not limited to packet sizes between 84 and 254 bytes.
[0012]
In one aspect, a digital switch has a plurality of blades coupled to a switching fabric via a serial pipe. The switching fabric can be provided on a backplane and / or one or more blades. Each blade outputs a serial data stream to the switching fabric in a plurality of stripes along with in-band control information. The switching fabric includes a plurality of cross points corresponding to a plurality of stripes. Each cross point has a plurality of port slices coupled to a plurality of blades. In one embodiment, five stripes and five cross points are used. Each blade has five serial links coupled to each of the five cross points. In one example of an implementation, the serial pipe coupling the blades to the switching fabric is a 50 Gbps serial pipe made up of five 10 Gbps serial links. Each 10 Gbps serial link is coupled to a respective cross point and transfers a serial data stream. The serial data stream includes a wide cell data slice corresponding to one stripe.
[0013]
In one aspect of the invention, each blade has a backplane interface adapter (BIA). BIA has three traffic processing flow paths. The first traffic processing flow path extends in a traffic flow direction from the local packet processor toward the switching fabric. The second traffic processing flow path extends in a traffic flow direction from the switching fabric toward the local packet processor. The third traffic processing flow path forwards local traffic from the first traffic processing flow path. This local traffic is sorted and routed locally at the BIA without having to traverse the switching fabric.
[0014]
The BIA includes one or more receivers, wide cell generators, and transmitters along a first path. The receiver receives a narrow input cell that forwards a data packet. Such narrow input cells are output from a packet processor and / or an IBT (Integrated Bus Translator) coupled to the packet processor. The wide cell generator generates a wide striped cell that forwards data packets received by the BIA on narrow input cells. The transmitter transmits the wide striped cells to the switching fabric in a plurality of stripes.
[0015]
According to the present invention, a wide cell extends over a plurality of stripes, each stripe containing in-band control information. In one aspect, each wide cell generator parses each narrow input cell, checks for control information indicating the beginning of the packet, and checks that all narrow input cells of the packet have one or more new wide striped cells. Encode one or more new wide-striped cells until it is distributed to and write one or more new wide-striped cells to multiple transmit queues.
[0016]
In one example, a BIA has four deserializer receivers, 56 wide cell generators, and five serializer transmitters. The four deserializer receivers receive narrow input cells output from up to eight sources (ie, up to two IBTs or packet processors per deserializer receiver). The 56 wide cell generators receive a number of received narrow input cells sorted based on destination slot identifier and source. The five serializers transmit a wide cell data slice corresponding to the stripe.
[0017]
According to another feature, the BIA may include a traffic sorter that sorts received input cells based on a destination slot identifier. In one example, the traffic sorter includes both a global / traffic sorter and a backplane sorter. The global / traffic sorter sorts received narrow input cells having destination slot identifiers identifying local destination slots from received narrow input cells having destination slot identifiers identifying global destination slots across the switching fabric. The backplane sorter further sorts the received narrow input cells having a destination slot identifier that identifies a global destination slot as a group based on the destination slot identifier.
[0018]
In one aspect, the BIA also includes a plurality of stripe transmit queues and a switched fabric transmit arbitrator. The switch fabric transmit arbitrator arbitrates the order in which data stored in the stripe transmit queue is transmitted by the transmitter to the switch fabric. In one example, arbitration proceeds in a round-robin fashion. Each stripe and queue stores a respective group of wide striped cells corresponding to a respective source packet processor and destination slot identifier. Each wide striped cell has one or more blocks that span multiple stripes. During a processing cycle, the switching fabric transmit arbitrator selects a stripe and a queue and pushes the next available cell (possibly one or more blocks of cells at a time) to the transmitter. Each stripe of the wide cell is pushed to a respective transmitter for that stripe.
[0019]
The BIA includes one or more receivers, a wide / narrow cell translator, and a transmitter along a second path. The receiver receives wide striped cells from the switching fabric in multiple stripes. Wide striped cells transfer data packets. The translator converts the received wide striped cells into narrow input cells that forward data packets. The transmitter then sends the narrow input cell to the corresponding destination packet process or IBT. In one example, five deserializer receivers receive five sub-blocks of a wide striped cell in multiple stripes. A wide stripe cell transfers data packets across multiple stripes and includes destination slot identifier information.
[0020]
In one aspect, a BIA includes a stripe interface and a stripe receive synchronization queue. Each stripe interface sorts the received sub-blocks in each stripe based on the source slot identifier information and stores the sorted received sub-blocks in a stripe receive synchronization queue.
[0021]
The BIA includes an arbitrator, a stripe-based wide cell assembler, and a narrow / wide cell translator along a second traffic flow processing path. The arbitrator arbitrates the order in which data stored in the stripe receive synchronization queue is transmitted to the stripe-based wide cell assembler. A stripe-based wide cell assembler assembles wide striped cells based on received data sub-blocks. The narrow / wide cell translator then converts the arbitrated received wide striped cell to a narrow input cell that forwards the data packet.
[0022]
According to an aspect of the invention, a second level of arbitration is also performed. The BIA further includes a destination queue and a local destination transmission arbitrator in the second pass. The destination queue includes narrow cells transmitted by the local traffic sorter (from the first path) and narrow cells translated by the translator (from the second path). The local destination transmit arbitrator arbitrates the order in which narrow input cells stored in the destination queue are transmitted to the serializer transmitter. Finally, the serializer transmitter then sends the narrow input cell to the corresponding IBT and / or source packet processor (eventually from the blade through the physical port).
[0023]
According to another aspect of the present invention, there is provided a system and method for encoding a wide striped cell. A wide cell extends over a plurality of stripes, each stripe containing in-band control information. Each stripe may include status information, reserved information, and payload data. In one aspect, the wide cell generator encodes one or more wide striped cells.
[0024]
The wide cell generator encodes the initial block of the starting wide striped cell with the initial cell coding information. The initial cell coding information includes control information (such as a special K0 character) and state information given to each sub-block of the initial block of the wide cell. The wide cell generator also spreads the initial bytes of packet data over the available space in the initial block. The remaining bytes of the packet data span one or more blocks in the first wide striped cell (and subsequent wide cells) until either the end-of-packet condition is reached or the maximum cell size is reached. Distributed. Finally, the wide cell generator further encodes the ending wide striped cell with different end-of-packet information depending on the degree of filling of the wide striped cell with data. In one coding scheme, the end-of-packet information includes whether the end of the packet occurs at the end of the initial block, in a block after the initial block, at a block boundary, or at a cell boundary. Depends on the end condition of a set of packets.
[0025]
According to another aspect of the invention, a method of interfacing a serial pipe for transferring data packets with narrow input cells and a serial pipe for transferring data packets with wide striped cells is provided. , Generating wide striped cells, and transmitting a block of wide striped cells across a plurality of stripes. The method comprises the steps of: sorting received narrow input cells based on destination slot identifier; and generating the generated wide striped cells with corresponding stripes and queues based on destination slot identifier and source packet processor. And arbitrating the order in which the stored wide striped cells are selected for transmission.
[0026]
In one example, the generating step includes parsing each narrow input cell, checking for control information indicating the beginning of a packet, and determining whether the data of all narrow input cells that forward the packet has one or more new wide cells. Encoding the one or more new wide-striped cells until distributed to the striped cells; and writing the one or more new wide-striped cells to a plurality of transmit queues. The encoding step includes encoding an initial block of the starting wide striped cell with initial cell encoding information such as control information and status information. Encoding distributes the initial bytes of packet data over the available space in the initial block of the first wide striped cell, and makes available the end of the initial block of the first wide striped cell Adding reservation information to each of the remaining bytes of the packet, until the end-of-packet condition is reached, or until the maximum cell size is reached. The method may further include the steps of distributing over a plurality of blocks and encoding the ending wide striped cell with end-of-packet information. End-of-packet information is a set of packets that includes whether the end of the packet occurs at the end of the initial block, within any block after the initial block, at a block boundary, or at a cell boundary. Depends on the end condition.
[0027]
The method includes receiving a wide striped cell for forwarding a data packet in a plurality of stripes from a switching fabric and converting the received wide striped cell to a narrow input cell for forwarding a data packet. And transmitting the narrow input cell to a corresponding source packet processor. The method comprises the steps of: sorting received sub-blocks in each stripe based on sender slot identifier information; storing the sorted received sub-blocks in a stripe reception synchronization queue; Arbitrating the order in which the data stored in the queue is assembled. Other steps include assembling the wide striped cells in the order of the arbitration phase based on the received data sub-blocks and forwarding the arbitrated received wide striped cells to a data packet. Converting the narrow cells into narrow input cells and storing the narrow cells in a plurality of destination queues. In one aspect, arbitrating the order in which the data stored in the destination queue is transmitted and transmitting the narrow input cells to the corresponding source packet processor and / or IBT in the order of the further arbitration stages. And other arbitrations are performed.
[0028]
The present invention further provides for error detection and recovery. Such errors may include stripe synchronization errors. In one aspect, the management module includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The level monitor monitors data received by the receiving blade. The stripe synchronization error detector detects a stripe synchronization error based on the amount of data monitored by the level monitor. Examples of stripe synchronization errors include incoming link errors, cross point failures, and outgoing link errors. In one example, data received at the receiving blade is sorted based on stripe / source information and stored in a set of data structures (eg, FIFO). The level monitor monitors the level of data stored in each data structure. The stripe synchronization error detector detects at least one of an overflow condition and an underflow condition in the amount of data received on each stripe from a particular source.
[0029]
The flow controller initiates a recovery routine that resynchronizes data between stripes in response to detecting a stripe synchronization error. The control character presence tracker identifies the presence of a K2 character in the recovery routine.
[0030]
The present invention is a method for detecting a stripe synchronization error in a network switch, comprising the steps of: sorting data received in a receiving slot based on stripe / source information; Storing in data structures; monitoring the level of data stored in each data structure; and determining overflow and underflow conditions in the amount of data received on each stripe from a particular source. Detecting at least one of the steps. The source information may identify the slot that transmitted data across the switching fabric of the network switch, or may identify the source packet processor that transmitted data from the slot across the switching fabric of the network switch. it can.
[0031]
The present invention is a method of maintaining synchronization of striped cell traffic, comprising transmitting a common character in a striped cell for a predetermined number of cycles in all lanes, and receiving a common character in a striped receive synchronization queue. The method further includes evaluating a common control character and detecting a synchronization condition, if any, indicating that the stripe receive synchronization queue has been cleared.
[0032]
The present invention is a method for managing asynchronous traffic flow through cross-point switches in a switching fabric, comprising the steps of monitoring the level of a stripe receive synchronous queue, and determining whether an asynchronous condition exists. Starting a resynchronization routine if an asynchronous condition exists. The resynchronization routine includes transmitting a common character in a striped cell over a predetermined number of cycles in all lanes, evaluating a common control character received in a stripe receive synchronization queue, Detecting a synchronization condition, if any, indicating that has been cleared.
[0033]
According to another aspect of the present invention, there is provided a redundant switching system. The redundant switching system includes two switching blades and at least one input / output blade (or slave blade). Each switching blade has a plurality of cross points corresponding to respective stripes of the serial data stream. Each incoming / outgoing blade is coupled to each switching blade by a backplane connection. Each ingress / egress blade also includes a plurality of redundant fabric transceivers (RFTs). RFT can switch traffic between cross points on two switching blades. This ensures redundancy.
[0034]
In one aspect, a redundant fabric transceiver is coupled to a bus interface adapter and includes one or more first and second ports, a multiplexer, a downlink transceiver, and an uplink transceiver. The multiplexer selects communication data to be transmitted from similar data. The downlink transceiver receives, conditions, and transmits this communication data. Uplink transceivers also receive, condition, and transmit communication data. A register module may be used that includes condition information indicating operation of the downlink transceiver and / or the uplink transceiver, where the condition information includes configuration and parameter settings for received and transmitted data. included.
[0035]
Other aspects, features, and advantages of the present invention, as well as the structure and operation of various aspects of the present invention, are described below with reference to the accompanying drawings.
[0036]
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the invention and, together with the description, explain the principles of the invention; Work to enable you to
[0037]
Next, the present invention will be described with reference to the accompanying drawings. In the drawings, identical reference numbers indicate identical or functionally similar elements. Further, the left-most digit (s) of a reference number identifies the drawing in which the reference number first appears.
[0038]
Detailed description of the invention
table of contents
I. Overview and discussion
II. the term
III. Digital switch architecture
A. Cross point architecture
B. Port slice operation including wide cell coding and flow control
C. Backplane interface adapter
D. Overall operation of the backplane interface adapter
E. First traffic processing path
F. Narrow cell format
G. Sort traffic
H. Generating wide striped cells
I. Encoding wide striped cells
J. Initial block coding
K. End-of-packet encoding
L. Switching fabric transmission arbitration
M. Cross point processing of stripes
N. Second traffic processing path
O. Cell boundary alignment
P. Packet alignment
Q. Wide striped cell size at line speed
R. IBT and packet processing
S. Narrow cell encoding process and packet encoding process
T. Management process and error control
U. Reset and recovery procedures
IV. Control logic
V. Conclusion
[0039]
I. Overview and discussion
The present invention is a high performance digital switch. Each blade is coupled to the switching fabric through a serial pipe. The switching fabric uses serial link technology. A sparsely striped switching fabric switches a serial data stream instead of a parallel data stream. Each blade outputs a serial data stream on a serial pipe. Serial pipes are some serial links that couple blades to the switching fabric. The serial data stream represents a collection of input serial data streams supplied to each blade through a physical port. Each blade outputs a serial data stream having in-band control information to the switching fabric in a plurality of stripes. In one aspect, a serial data stream transfers data packets in a wide striped cell across a plurality of loosely coupled stripes. The wide striped cells are coded. In-band control information is transferred in one or more blocks of the wide striped cell.
[0040]
In one implementation, each blade of the switch sends and receives 50 gigabits per second of full-duplex traffic over the backplane. This is done to ensure line speed, wire speed, and non-blocking over all packet sizes.
[0041]
The high performance switch according to the present invention may be any switch, including, but not limited to, the Internet, enterprise systems, Internet service providers, and any protocol layer switching (Layer 2, Layer 3, Layer 4-7 switching, etc.). Can be used in a switching environment.
[0042]
The present invention will be described with respect to this example environment. This example environment is only used for illustrative purposes. The present invention is not limited to application to such example environments. In addition, it will be apparent to those skilled in the art, after reading the following description, how to implement the invention in other environments now known or later developed.
[0043]
II. the term
In order to more clearly describe the present invention, the following term definitions will be adhered to as consistently as possible throughout the specification.
[0044]
The term "switch fabric" or "switch fabric" refers to a switchable interconnect between blades. The switch fabric can be located on a backplane, blades, multiple blades, units separated from the blades, or any combination thereof.
[0045]
The term "packet processor" refers to any type of packet processor, including but not limited to an Ethernet packet processor. The packet processor analyzes and determines where to send the packet.
[0046]
The term "serial pipe" refers to one or more serial links. In one non-limiting embodiment, the serial pipe is a 10 Gbps serial pipe and includes four 2.5 Gbps serial links.
[0047]
The term "serial link" refers to a data link or bus that transfers digital data serially between points. Relatively high bit rate serial links can also be formed by combining lower bit rate serial links.
[0048]
The term "stripe" refers to one data slice of a wide cell. The term "sparsely coupled" stripes refers to the data flow within each stripe that is autonomous with respect to the other stripes. It is not necessary that the data flow be completely synchronized in each stripe; the data flow can proceed independently in each stripe and be skewed relative to other stripes.
[0049]
III. Digital switch architecture
FIG. 1 shows an outline of the architecture of the switch 100 of the present invention. The switch 100 includes a switch fabric 102 (also called a switching fabric or switching fabric module) and a plurality of blades 104. In one aspect of the invention, switch 100 includes eight blades 104a-104h. Each blade 104 communicates with the switch fabric 102 via a serial pipe 106. Each blade 104 further includes a plurality of physical ports 108 that receive various types of digital data from one or more network connections.
[0050]
In a preferred embodiment of the present invention, a switch 100 having eight blades can switch 400 gigabits per second (Gbps) full-duplex traffic. As used herein, all data rates are full duplex unless otherwise indicated. Each blade 104 communicates data over the serial pipe 106 at a rate of 50 Gbps.
[0051]
Switch 100 is shown in more detail in FIG. As shown, switch fabric 102 includes five cross points 202. Data transmitted and received between each blade and the switch fabric 102 is striped across the five cross point chips 202A-202E. Each cross point 202A-E then receives one-fifth of the data passing through one stripe or switch fabric 102. As shown in FIG. 2, each serial pipe 106 of blade 104 is made up of five serial links 204. The five serial links 204 of each blade 104 are coupled to five corresponding cross points 202. In one example, each serial link 204 is a 10G serial link, such as a 10G serial link composed of four 2.5 Gbps serial links. In this manner, data is transmitted across the backplane 102 using serial link technology.
[0052]
Each cross point 202A-202E is an 8-port cross point. In one example, each cross point 2202A-E receives eight 10G data streams. Each data stream corresponds to a particular stripe. The stripe has data in a wide cell format including, inter alia, a destination port number (also called a destination slot number) and special in-band control information. The in-band control information includes K special characters such as K0 character and K1 character. The K0 character delimits the beginning of a new cell in the stripe. The K1 character delimits the end of the packet in the stripe. Such encoding within each stripe allows each cross point 202A-202E to operate autonomously or independently of the other cross points. In this manner, the cross points 202A-202E and their associated stripes are loosely coupled.
[0053]
Each cross point 202 has a set of data structures, such as a data FIFO (first in first out data structure). These data structures store data based on source and destination ports. In one aspect, for an 8-port cross point, 56 data FIFOs are used. Each data FIFO stores data associated with a respective source port and destination port. Packets arriving at each source port are written to the data FIFO corresponding to the associated source and destination ports. The source port is associated with the port (and port slice) where the packet is received. The destination port is associated with a destination port or slot number found in-band in data sent as a stripe to a port.
[0054]
In an aspect of the invention, the switch size is defined as one cell, and the cell size is defined as any of 8 bytes, 28 bytes, 48 bytes, 68 bytes, 88 bytes, 108 bytes, 128 bytes, 148 bytes. You. Each port (or port slice) sends and receives serial data at 10 Gbps over its respective serial link. Each of the cross points 202A to 202E has a switching capacity of 160 Gbps (160 Gbps = 10 Gbps * 8 ports * 2-way full duplex). Such cell sizes, serial link data rates, and switching capacities are exemplary and not limiting of the present invention. The cross-point architecture and operation are described in detail below.
[0055]
In the prior art, to increase the throughput of the switch, the width of the data bus is increased to improve the "parallel processing" function of the switch, and to increase the clock rate. However, the advantages of both approaches are reduced. For example, very wide data buses are constrained by the physical limitations of the circuit board. Similarly, very high clock rates are limited by the characteristics of the printed circuit board. The inventor has discovered that the use of serial link technology in the backplane significantly increases the switching bandwidth compared to the prior art.
[0056]
In a preferred embodiment, each serial pipe 106 can carry full-duplex traffic at 50 Gbps, and each serial link 204 can carry full-duplex traffic at 10 Gbps. As a result of this architecture, each of the five cross points 202 combines five serial links at 10 gigabits per second to achieve a total data rate of 50 gigabits per second for each serial pipe 106. Thus, the total switching capacity across the backplane 102 for eight blades is 50 Gigabits per second x 8x2 (for duplex), or 800 Gigabits per second. Such switching capacity is not possible with the prior art using synchronized parallel data buses in the switching fabric.
[0057]
The advantage of such a switch with a 50 Gbps serial pipe from blade 104 to backplane 102 is that each blade 104 supports four 10 Gbps Ethernet packet processors at line speeds over a range of packet sizes Or support four Optical Channels OC-192C at line speed, or one OC-768C at line speed. The invention is not limited to these examples. Other configurations and types of packet processors can be used with the switches of the present invention by those skilled in the art given in this description.
[0058]
Referring now to FIG. 3A, the architecture of blade 104 is shown in more detail. Blade 104 includes a backplane interface adapter (BIA) 302 (also referred to as a "super backplane interface adapter" or SBIA), multiple integrated bus translators (IBTs) 304, and multiple packets. -Includes processor 306. BIA 302 is responsible for striping data across five cross points 202 of backplane 102. In a preferred embodiment, BIA 302 is implemented as an application-specific circuit (ASIC). BIA 302 receives data from packet processor 306 through IBT 304 (or directly from a compatible packet processor). The BIA 302 can pass data to the backplane 102 or perform a local switch between local ports on the blade 104. In a preferred embodiment, BIA 302 is coupled to four serial links 308. Each serial link 308 is coupled to IBT 304.
[0059]
Each packet processor 306 includes one or more physical ports. Each packet processor 306 receives an inbound packet from one or more physical ports, determines the destination of the inbound packet based on the control information, and determines a local address for the physical port to which the packet processor is connected. Local switching is performed on the packet, the packet addressed to the remote port is formatted so as to create parallel data, and the parallel data is switched to the IBT 304. Each IBT 304 receives parallel data from each packet processor 306. IBT 304 then converts the parallel data into at least one serial bit stream. IBT 304 provides a serial bit stream to BIA 302 via pipe 308, described herein as one or more serial links. In a preferred embodiment, each pipe 308 is a 10 Gb / s XAUI interface.
[0060]
In the example shown in FIG.3A, packet processors 306C and 306D include 24 Ethernet ports of 10 or 100 Mbit / s and two Ethernet ports of 1000 Mbit / s, or 1 Gbps. I have. Before the data is converted, the input data packets are converted to 32-bit parallel data clock data 133 MHz to achieve a data rate of 4 Gbps. Data is placed in cells (also referred to as "narrow cells"), and each cell includes a header that combines control signals in-band with the data stream. Packets are interleaved every 32 different destination slots depending on cell boundaries.
[0061]
In the example of FIG. 3A as well, IBT 304C is connected to packet processors 306C and 306D. This may be, for example, a 10 Gigabit per second OC-192 packet processor. In these examples, each IBT 304 receives as its input a 64-bit wide data stream clocked at 156.25 MHz. Each IBT 304 then outputs a 10 Gigabit per second serial data stream to BIA 302. According to one narrow cell format, each cell contains a 4-byte header followed by 32 bytes of data. The 4-byte header occupies one cycle on four XAUI lanes. Each data byte is serialized on one XAUI lane.
[0062]
The BIA 302 receives the outputs of the IBTs 304A to 304D. Therefore, the BIA 302 receives 4 × 10 Gbps data. Or it receives 8x5 Gigabits of data per second. The BIA302 operates at a clock rate of 156.25 MHz. The BIA 302 outputs a 5 × 10 Gbit / s data stream to five cross points 202 in the backplane 102 by adding management overhead and striping.
[0063]
BIA 302 receives the serial bit stream from IBT 304, determines the destination of each inbound packet based on the packet header information, performs local switching between local IBTs 304, formats data destined for the remote port, Aggregate the serial bit stream from IBT304 to create a total bit stream. The aggregated bit stream is then striped across five cross points 202A-202E.
[0064]
FIG. 3B shows a configuration of a blade 104 according to another aspect of the present invention. In this configuration, BIA 302 receives output from a 10 Gbps packet processor 316A, IBT 304C, and an optical channel OC-192C packet processor 316B on a serial link. IBT 304 is further coupled to packet processors 306C, 306D as described above. 10 Gbps packet processor 316A outputs a serial data stream of narrow input cells that transfers data packets over serial link 318A to BIA 302. IBT 304C outputs a serial data stream of narrow input cells that transfers data packets to BIA 302 over serial link 308C. Optical channel OC-192C packet processor 316B outputs two serial data streams of narrow input cells that transfer data packets to BIA 302 over two serial links 318B, 318C.
[0065]
A. Cross point architecture
FIG. 4 shows the architecture of the cross point 202. Cross point 202 includes eight ports 401A-401H coupled to eight port slices 402A-402H. As shown, each port slice 402 is connected to each of the other seven port slices 402 by a wire 404 (or other connection medium). Each port slice 402 is also coupled to a respective blade 104 through port 401. To illustrate this, FIG. 4 shows the connection of port 401F and port slice 402F (also called port_slice 5). For example, port 401F is coupled to blade 104F via serial link 410. Serial link 410 may be a 10G full-duplex serial link.
[0066]
Port slice 402F is coupled to each of the other seven port slices 402A-402E and 402G-402H via lines 420-426. Links 420-426 receive on other port slices 402A-402E and 402G-402H having a destination port number (also called a destination slot identifier) associated with the port of port slice 402F (ie, destination port number 5). Routed data. Finally, port slice 402F includes a link 430 that couples the port associated with port slice 402F to the other seven port slices. Link 430 allows data received on the port of port slice 402F to be transmitted to the other seven port slices. In one aspect, each link 420-426 and 430 between port slices is a bus that transfers data in parallel within cross point 202. Similar connections (not shown for clarity) are provided on each of the other port slices 402A-402E, 402G and 402H.
[0067]
FIG. 5 shows the architecture of port 401F and port slice 402F in more detail. The architecture of the other ports 401A-401E, 401G, and 401H and port slices 402A-402E, 402G, and 402H is similar to port 401F and port slice 402F. Therefore, only the port 401F and the port slice 402F need to be described in detail. Port 401F includes one or more deserializer receiver 510 and serializer transmitter 580. In one aspect, deserializer receiver 510 and serializer transmitter 580 are implemented as a serializer / deserializer circuit (SERDES) that converts data into a serial data stream and a parallel data stream. In aspects of the invention, port 401F may be part of port slice 402F, on a common chip, or on separate chips, or in separate units.
[0068]
Port slice 402F includes a receive synchronization FIFO module 515 coupled between deserializer receiver 510 and accumulator 520. The reception synchronization FIFO module 515 stores data output from the deserializer receiver 510 corresponding to the port slice 402F. Accumulator 520 writes data to the appropriate data FIFOs (not shown) in other port slices 402A-402E, 402G, and 402H based on the destination slot or port number in the header of the received data. .
[0069]
Port slice 402F also receives data from other port slices 402A-402E, 402G, and 402H. This data is received at the other seven ports of port slices 402A-402E, 402G, and 402H and corresponds to data having a destination slot number corresponding to port slice 402F. Port slice 402F includes seven data FIFOs 530 that store data from corresponding port slices 402A-402E, 402G, and 402H. The accumulators (not shown) in the seven port slices 402A-402E, 402G, and 402H extract the destination slot number associated with port slice 402F and each of the seven data FIFOs 530 in port slice 402F. Write the data corresponding to. As shown in FIG. 5, each data FIFO 530 includes a FIFO controller and a FIFO random access memory (RAM). The FIFO controller is coupled to a FIFO read arbitrator 540. FIFO RAM is coupled to multiplexer 550. FIFO read arbitrator 540 is further coupled to multiplexer 550. Multiplexer 550 has an output coupled to dispatcher 560. Dispatcher 560 has an output coupled to transmit synchronization FIFO module 570. Transmit synchronization FIFO module 570 has an output coupled to serializer transmitter 580.
[0070]
In operation, FIFO RAM accumulates data. After the data FIFO RAM has accumulated one cell of data, the corresponding FIFO controller generates a read request to the FIFO read arbitrator 540. FIFO read arbitrator 540 processes read requests from each different FIFO controller in a desired order, such as a round robin order. After one cell of data has been read from one FIFO RAM, the FIFO read arbitrator 540 proceeds to the processing of the next requesting FIFO controller. In this way, arbitration is performed for each different requesting FIFO controller, and data received at each different source port is transferred. This maintains a relatively uniform but loosely coupled data flow through the cross point 202.
[0071]
The FIFO read arbitrator 540 switches the multiplexer 550 to process the read request and transfers one cell of data from the data FIFO RAM associated with the read request to the dispatcher 560. Dispatcher 560 outputs data to transmission synchronization FIFO 570. The transmit synchronization FIFO 570 stores the data and continues to store the data until it is transmitted by the serializer transmitter 580 in a serial data stream to the blade 104F.
[0072]
B. Port slice operation with wide cell coding and flow control
According to another aspect, a port slice operates on wide cell coding and flow control conditions. FIGS. 27A-27E show a routine 2700 for processing data in a port slice based on wide cell encoding and flow control conditions (steps 2710-2790). For simplicity, the routine 2700 is described with respect to the cross point 202 and example port slice 402F embodiment. The operation of the other port slices 402A-402E, 402G, and 402H is similar.
[0073]
At step 2710, an entry in the receive synchronization FIFO 515 is managed. In one example, receive synchronization FIFO module 515 is an 8-entry FIFO where the write and read pointers are initialized to be 3 entries apart. The receive synchronous FIFO module 515 writes the 64-bit data from the SERDES deserializer receiver 510, reads the 64-bit data from the FIFO by the clock signal, supplies the data to the accumulator 520, and the separation distance becomes 1 or less. In this case, the read pointer is adjusted to maintain a three-entry separation between the read pointer and the write pointer.
[0074]
At step 2720, accumulator 520 receives the two 32-bit data chunks received from receive synchronization FIFO 515. Accumulator 520 detects the special character K0 in the first byte of the first and second chunks (stage 2722). Accumulator 520 then extracts the destination slot number from the status field in the header if K0 is detected (step 2724).
[0075]
As shown in FIG. 27B, accumulator 520 further determines whether the cell header is low-ordered or high-ordered (step 2726). The accumulator 520 writes the 64-bit data to the data FIFO corresponding to the destination slot if the cell header is low-ordered or high-ordered, but not low-ordered and high-ordered (stage). 2728). At step 2730, accumulator 520 determines whether the cell header appears in the first and second chunks of data (low-ordered and high-ordered) by two destination slots (or ports). Write two 64-bit data to two data FIFOs corresponding to. Accumulator 520 then fills the second chunk of 32-bit data with idle characters if the cell does not end on a 64-bit boundary and the destination of a subsequent cell is a different slot (step 2732). Accumulator 520 performs early termination of the cell if an error condition is detected by inserting K0 and ABORT status information into the data (step 2734). When accumulator 520 detects the K1 character in the first byte of data_l (first chunk) and data_h (second chunk) (stage 2736), accumulator 520 determines whether the following 64 bits Write the data to all destination data FIFOs (step 2738).
[0076]
If two 32-bit data chunks are valid, as shown in FIG. 27C, those chunks are written to the data FIFO RAM in one data FIFO 530. At step 2742, if only one 32-bit chunk is valid, the chunk is stored in a temporary register if the FIFO depth has not fallen below a predetermined level. The stored 32-bit data and subsequent 32-bit data are combined and written to FIFO RAM. If only one 32-bit chunk is valid and the FIFO depth is less than 4 entries, the valid 32-bit chunk is combined with 32-bit idle data and written to FIFO RAM ( Step 2744).
[0077]
At step 2746, each FIFO controller indicates to the FIFO read arbitrator 540 if K0 has been read or if the FIFO RAM is empty. This indication is a read request for arbitration. At step 2748, each FIFO controller indicates to FIFO read arbitrator 540 whether K0 is aligned with the first 32-bit chunk or the second 32-bit chunk. When flow control from the output port is detected (such as when a predetermined flow control sequence of one or more characters is detected), the FIFO controller reads the FIFO after the current cell has been completely read from FIFO RAM. The request to the arbitrator 540 is stopped (step 2750).
[0078]
As shown in FIG. 27D, at step 2760, the FIFO read arbitrator 540 arbitrates seven requests from seven FIFO controllers and switches on a cell (K0) boundary. If the end of the current cell is 64-bit aligned, the FIFO read arbitrator 540 switches to the next requester and supplies 64-bit data from the requesting FIFO controller's FIFO RAM to the dispatcher 560 (step 2762). If the end of the current cell is 32 bits aligned, the FIFO read arbitrator 540 combines the lower 32 bits of the current data with the lower 32 bits from the next requesting FIFO controller and combines the combined 64-bit data. Supply to dispatcher 560 (step 2764). Further, at step 2766, FIFO read arbitrator 540 indicates to dispatcher 560 if all seven FIFO RAMs are empty.
[0079]
As shown in FIG.27E, if non-idle data is received from FIFO read arbitrator 540 at step 2770, dispatcher 560 provides 64-bit data to SERDES synchronous FIFO module 570 and serializer transmit Machine 580. When the FIFO read arbitrator 540 indicates that all seven FIFO RAMs are empty, the dispatcher 560 inserts a first alignment sequence to send to the SERDES synchronous FIFO module 570 and send to the transmitter 580 ( Step 2772). When the programmable timer expires and the previous call has been completely transmitted, dispatcher 560 inserts a second alignment sequence to be transmitted to SERDES synchronous FIFO module 570 and transmitted to transmitter 580 (step 2774). ). Dispatcher 560 instructs FIFO read arbitrator 540 to temporarily suspend processing for the requester until the pre-scheduled current alignment sequence has been completely transmitted (step 2776). Control ends (step 2790).
[0080]
C. Backplane interface adapter
To describe the structure and operation of the backplane interface adapter, reference is made to the components shown in FIGS. FIG. 6 is a diagram of a backplane interface adapter (BIA) 600 according to aspects of the present invention. BIA 600 includes two traffic processing paths 603,604. FIG. 7 is a diagram illustrating a first traffic processing path 603 for local serial traffic received at a BIA 600, in accordance with an aspect of the present invention. FIG. 8 is a diagram illustrating an exemplary switching fabric 645 in more detail, in accordance with aspects of the present invention. FIG. 9 is a diagram illustrating a second traffic processing path 604 for backplane serial traffic received at BIA 600, in accordance with an aspect of the present invention. For convenience, the BIA 600 of FIG. 6 will also be described with reference to a more detailed embodiment of the elements along paths 603, 604 shown in FIGS. 7 and 9, and the example switching fabric 645 shown in FIG. . The operation of the backplane interface adapter will also be described with respect to the routines and example diagrams for the wide striped cell encoding schemes shown in FIGS.
[0081]
D. Overall operation of the backplane interface adapter
FIG. 10 is a flowchart of a routine 1000 (steps 1010-1060) that interfaces a serial pipe transferring data packets with narrow input cells to a serial pipe transferring data packets with wide striped cells. . Routine 1000 receives a narrow input cell (step 1010), sorts the received input cell based on destination slot identifier (1020), and generates a wide striped cell (step 1030). Storing the generated wide striped cells in a corresponding stripe transmit queue based on the destination slot identifier and the source packet processor (step 1040); Arbitrating the order selected for this (step 1050) and transmitting a data slice representing a block of wide cells across multiple stripes (step 1060). For simplicity, each of these steps will be further described with respect to the operation of the first traffic processing path in BIA 600 in the embodiments of FIGS. 6 and 7 below.
[0082]
FIG. 11 is a flowchart of a routine 1100 (steps 1110-1180) that interfaces a serial pipe transferring data packets with wide striped cells and a serial pipe transferring data packets with narrow input cells. . Routine 1100 includes receiving a wide striped cell from the switching fabric that transfers the data packet in a plurality of stripes from the switching fabric (step 1110), and identifying the received sub-blocks in each stripe with a source packet processor identifier and a transmission. Sorting based on the original slot identifier information (step 1120); storing the sorted received sub-blocks in a stripe receive synchronization queue (step 1130); arbitrating based on the received data sub-blocks Assembling the wide striped cells in a sequence of steps (step 1140), converting the received wide striped cells into narrow input cells for transferring data packets (step 1150); Storing the cells in a plurality of destination queues (step 1160); Arbitrating the order in which the data stored in is assembled (step 1170) and transmitting the narrow output cells to the corresponding source packet processor (step 1180). In certain other aspects, arbitrating the order in which the data stored in the destination queue is transmitted, and transmitting the narrow input cells to the corresponding source packet processor and / or the IBT in the order of the arbitration phase. Other arbitrations including steps are performed. For simplicity, each of these steps is further described with respect to the operation of the second traffic processing path within BIA 600 in the embodiments of FIGS. 6 and 7 below.
[0083]
As shown in FIG. 6, a traffic processing flow path 603 extends from the local packet processor toward the switching fabric 645 in the traffic flow direction. A traffic processing flow path 604 extends from the switching fabric 645 to the local packet processor in the traffic flow direction. BIA 600 includes a deserializer receiver 602, a traffic sorter 610, a wide cell generator 620, a stripe transmit queue 625, a switched fabric transmit arbitrator 630, and a serializer transmitter 640 coupled along a path 603. The BIA 600 includes a deserializer receiver 650, a stripe interface module 660, a stripe receive synchronization queue 685, a controller 670 (arbitrator 672, a stripe-based wide cell assembler 674, and a management module coupled along a path 604). 676), a wide cell translator 680, a destination queue 615, a local destination transmit arbitrator 690, and a serializer transmitter 692.
[0084]
E. First traffic processing path
Deserializer receiver 602 receives a narrow input cell that forwards a data packet. These narrow input cells are output to deserializer receiver 602 from a packet processor and / or an integrated bus translator (IBT) coupled to the packet processor. In one example, four deserializer receivers 602 are coupled to four serial links (such as links 308A-308D, 318A-318C described above in FIGS. 3A-3B). As shown in the example of FIG. 7, each deserializer receiver 602 includes a deserializer receiver 702 coupled to a cross clock domain synchronizer 703. For example, each deserializer receiver 702 coupled to a cross clock domain synchronizer 703 is a set of four SERDES deserializer receivers and a domain synchronizer that transfers data bytes on four lanes of narrow input cells. May be. In one aspect, each deserializer receiver 702 can receive an interleaved data stream from two serial links coupled to two sources. FIG. 7 shows an example where four deserializer receivers 702 (q = 4) are coupled to two sources (j = 2) on a total of eight serial links (k = 8). In one example, each deserializer receiver 702 receives serial data with a capacity of 10 Gb / s.
[0085]
F. Narrow cell format
FIG. 13 shows the format of an exemplary narrow cell 1300 used to transfer data packets on narrow input cells. Such a format may include, but is not limited to, a data cell format received from the XAUI interface. Narrow cell 1300 includes four lanes (lanes 0-3). Each lane 0-3 transfers one data byte on the serial link. The beginning of the cell contains the header, followed by the payload data. The header includes one byte of control information in lane 0 and one byte of state information in lane 1. One byte is reserved for each of lanes 2 and 3. Table 1310 shows examples of usable state information. This state information may include any combination of state information including one or more of a slot number, a payload state, and a source or destination packet processor identifier. The slot number is an encoded number, such as 00, 01, or other identifier (eg, alphanumeric or ASCII value) that identifies the blade (also called a slot) to which the narrow cell will be transmitted. The payload state may be any encoded number or reserved (meaning reserved cells without data), SOP (meaning the beginning of a packet cell), data (packet) Other identifiers that indicate the specific state of the data in the cell being transmitted, such as a cell that transfers the payload data of the cell), abort (meaning that the packet transfer is interrupted). May be.
[0086]
G. Traffic sorting
Traffic sorter 610 sorts the received narrow input cells based on destination slot number. Traffic sorter 610 routes narrow cells (also referred to as local traffic) destined for the same blade as BIA 600 to destination queue 615. Narrow cells (also referred to as global traffic) destined for other blades in the switch beyond the switching fabric are routed to the wide cell generator 620.
[0087]
FIG. 7 illustrates another aspect where the traffic sorter 610 includes a global / traffic sorter 712 coupled to a backplane sorter 714. Global / traffic sorter 712 sorts the received narrow input cells based on the destination slot identifier. Traffic sorter 712 routes narrow cells destined for the same blade as BIA 600 to destination queue 615. Narrow cells (also referred to as global or backplane traffic) destined for other blades in the switch beyond the switching fabric are routed to the backplane traffic sorter 714. Backplane traffic sorter 714 further sorts the received narrow input cells having a destination slot identifier that identifies a group of global destination slots based on the destination slot identifier. In this way, narrow cells are grouped by the blade to which they are transferred. The backplane traffic sorter 714 then routes the sorted group of narrow input cells of the backplane traffic to the corresponding wide cell generator 720. Each wide cell generator 720 then processes the corresponding narrow input cell group. Each narrow input cell group represents a portion of a packet transmitted from two corresponding interleaved sources (j = 2) and destined for a respective blade. In one example, 56 wide cell generators 720 are coupled to the outputs of four backplane traffic sorters 714. A total of 56 wide cell generators 720 are given by 56 = q * j * l-1, where j = 2 sources, l = 8 blades, q = 4 serial input pipes and 4 One deserializer receiver 720.
[0088]
H. Wide striped cell generation
Wide cell generator 620 generates wide striped cells. Wide striped cells transport data packets received by BIA 600 on narrow input cells. A wide cell extends over a plurality of stripes, each stripe containing in-band control information. For simplicity, the operation of wide cell generators 620, 720 will be further described with respect to routine 1200 of FIG. However, the routine 1200 is not limited to use with the wide cell generators 620, 720, but can be used with other structures and applications.
[0089]
FIG. 12 illustrates a routine 1200 (steps 1210-1240) for creating a wide striped cell according to the present invention. In one aspect, each wide cell generator 620, 720 performs steps 1210-1240. In step 1210, wide cell generators 620, 720 analyze each narrow input cell to identify a header. If control information is found in the header, a check is made to determine if the control information indicates the beginning of a packet (step 1220). For example, to perform steps 1210 and 1220, wide cell generator 620, 720 reads lane 0 of narrow cell 1300 and determines control information indicating that the beginning of a packet is present. In one example, the start control information of the packet is a special control character K0.
[0090]
Each time a packet is detected (step 1225), steps 1230 to 1240 are performed. At step 1230, the wide cell generators 620, 720 perform one or more new wide striping operations until the data of all narrow input cells of the packet is distributed to one or more new wide striped cells. Encode the cell. The encoding is further described below with respect to routine 1400 and FIGS. 15A-15D and FIG.
[0091]
Then, at step 1230, wide cell generator 620 writes one or more new wide striped cells to multiple transmit queues 625. In the example of FIG. 7, a total of 56 wide cell generation devices 720 are coupled to 56 stripe transmission queues 725. In this example, each of the 56 wide cell generators 720 writes the newly generated wide striped cell to each of the 56 stripe transmit queues.
[0092]
I. Encoding wide striped cells
According to another aspect of the present invention, there is provided a system and method for encoding a wide striped cell. In one aspect, wide cell generators 620, 720 each generate a wide striped cell to be encoded (stage 1230). FIG. 14 is a flowchart of a routine 1400 (steps 1410-1460) for encoding a wide striped cell according to aspects of the present invention.
[0093]
J. Initial block coding
In step 1410, the wide cell generators 620, 720 encode the initial block of the starting wide striped cell with the initial cell coding information. The initial cell coding information includes control information (such as a special K0 character) and state information given to each subblock of the initial block of the wide striped cell. FIG. 15A illustrates encoding of an initial block in a wide striped cell 1500 according to aspects of the present invention. The initial block is called cycle 1. The initial block has 20 bytes extending over five stripes 1-5. Each stripe has a 4-byte sub-block. The four bytes of the sub-block correspond to four one-byte lanes. Thus, a stripe is a data slice of a wide cell sub-block. A lane is a 1-byte data slice of a sub-block. Next, in step 1410, control information (K0) is provided to each lane 0 of stripes 1 to 5. State information is given to each lane 1 of the stripes 1 to 5. In addition, two bytes are reserved for lanes 2 and 3 of stripe 5.
[0094]
FIG. 15B is a diagram illustrating state information used in a wide striped cell according to aspects of the present invention. As shown in FIG. 15B, status information for a wide striped cell may include any combination of status information including one or more of a slot number, a payload status, and a reserved bit. The slot number is an encoded number, such as 00, 01, or other identifier (eg, alphanumeric or ASCII value) that identifies the blade (also called a slot) in which the wide striped cell is transmitted. The payload state can be any encoded number, or reserved (meaning reserved cells without data), SOP (meaning the beginning of a packet cell), data (payload data of the packet) Other identifiers that indicate the particular state of the data in the cell being transmitted, such as aborting (meaning that the packet transfer is interrupted). Reserved bits are also provided.
[0095]
At step 1420, wide cell generators 620, 720 distribute the initial bytes of packet data over the available space in the initial block. In the example wide striped cell 1500 shown in FIG.15A, two bytes of data D0, D1 are provided in lanes 2 and 3 of stripe 1, and two bytes of data D2, in lanes 2 and 3 of stripe 2. D3 is provided, two bytes of data D4 and D5 are provided to lanes 2 and 3 of stripe 3, and two bytes of data D6 and D7 are provided to lanes 2 and 3 of stripe 4.
[0096]
At step 1430, wide cell generators 620, 720 spread the remaining bytes of the packet data across one or more blocks of the first wide striped cell (and subsequent wide cells). In the example wide striped cell 1500, the maximum size of the wide striped cell is 160 bytes (8 blocks), corresponding to a maximum of 148 bytes of data. The wide striped cell 1500 further has data bytes D8-D147 distributed over seven blocks (referred to as blocks 2-8 in FIG. 15A), as well as data bytes D0-D7 in the initial block.
[0097]
In general, the packet data continues to be distributed until the end-of-packet condition is reached or the maximum cell size is reached. Thus, a check is made as to whether the maximum cell size has been reached (step 1440) and whether the end of the packet has been reached (step 1450). If the maximum cell size has been reached at step 1440 and further packet data needs to be distributed, control returns to step 1410 to create additional wide striped cells to transfer the remaining packet data. If the maximum cell size is not reached in step 1440, an end-of-packet check is performed (step 1450). If the end of the packet is reached, the wide striped cell currently filled with packet data becomes the ending wide striped cell. Note that for packets smaller than 148 bytes, only one wide striped cell is required. Otherwise, multiple wide striped cells are used to transfer data packets across multiple stripes. When the end of the packet is reached in step 1450, control proceeds to step 1460.
[0098]
K. End-of-packet encoding
In step 1460, the wide cell generators 620 and 720 further encode the wide striped cells with different end-of-packet information depending on the degree of filling of the wide striped cells with data. In some coding schemes, the end-of-packet information is dependent on a set of end-of-packet information, including whether the end of the packet occurs in an initial or subsequent cycle, at a block boundary, or at a cell boundary. Different.
[0099]
FIG. 15C is a diagram illustrating end-of-packet encoding information used in an ending wide-striped cell according to aspects of the present invention. The special character byte K1 is used to indicate the end of the packet. End conditions for a set of four packets are shown (items 1-4). The four packet end conditions are whether the end of the packet occurs during the initial block (item 1) or during subsequent blocks (items 2-4). The end-of-packet condition of the subsequent block further includes whether the end of the packet occurs within a block (item 2), at a block boundary (item 3), or at a cell boundary (item 4). As shown in item 1 of FIG. 15C, when the end of the packet occurs during the initial block, the control and state information (K0, state) and the reservation information are saved as in other initial block transmissions. You. The K1 byte is provided as data in the remaining data bytes.
[0100]
As shown in item 2 of FIG. 15C, if the end of the packet occurs during a subsequent block (rather than at a block or cell boundary), the data in the remaining data bytes will be K1 until the end of the block is reached. A byte is appended. In item 2 of FIG. 15C, the end of the packet is reached at data byte D33 (stripe 2, lane 1 in block of cycle 3). The K1 byte is added for each lane for the rest of the block. When the end of the packet occurs at the block boundary of the subsequent block (item 3), a K1 byte is added as data for the entire subsequent block. In item 3 of FIG. 15C, the end of the packet is reached at data byte D27 (end of block of block 2). For the entire block (block 3), a K1 byte is added for each lane. When the end of the packet occurs at a cell boundary in a subsequent block (item 4), one wide striped cell with an initial block with the K1 byte appended as data is created. In item 4 of FIG. 15D, the end of the packet is reached at data byte D147 (end of cell and end of block 8). One wide striped cell is created that has only the initial block with normal control information, state information, and reservation information, with the K1 byte added. As shown in FIG. 15D, such an initial block with K1 bytes includes stripe 1 (K0, state, K1, K1), stripe 2 (K0, state, K1, K1), stripe 3 (K0, It is composed of stripes 1 to 5 having bytes such as state, K1, K1), stripe 4 (K0, state, K1, K1), and stripe (K0, state, reservation, reservation).
[0101]
L. Switching fabric transmission arbitration
In one aspect, BIA 600 also includes a switched fabric transmit arbitrator 630. The switching fabric transmission arbitrator 630 arbitrates the order in which data stored in the stripe transmission queues 625, 725 is transmitted by the transmitters 640, 740 to the switching fabric. Each stripe transmit queue 625, 725 stores a respective group of wide striped cells corresponding to a respective source packet processor and destination slot identifier. Each wide striped cell has one or more blocks that span multiple stripes. In operation, the switched fabric transmit arbitrator 630 selects the stripe transmit queues 625, 725 and pushes the next available cell to the transmitters 640, 740. In this way, one complete cell is transmitted at a time. (Alternatively, a portion of the cell can be transmitted.) Each stripe of the wide cell is pushed to its respective transmitter 640,740. In one example, during normal operation, a particular packet processor sends a complete packet to any particular slot or blade, and then a different packet processor sends a new packet to that slot. However, packets for each different slot are transmitted during the arbitration cycle. In other aspects, other blades or slots are then selected in a land-robin fashion.
[0102]
M. Cross point processing of stripes including wide cell coding
In one aspect, switching fabric 645 includes a number of cross-point switches 202 corresponding to each stripe. Each cross point switch 202 (also referred to herein as a cross point or cross point chip) handles one data slice of a wide cell corresponding to one respective stripe. In one example, five cross point switches 202A to 202E corresponding to five stripes are provided. For clarity, only two of the five cross-point switches corresponding to stripes 1 and 5 are shown in FIG. As described above with respect to FIG. 2, five cross point switches 202 are coupled between the transmitter and the receiver on all blades of the switch. For example, FIG. 8 shows a cross point switch 202 coupled between a set of transmitters 740 for one blade stripe and another set of receivers 850 on a different blade.
[0103]
The operation of cross point 202, and in particular, port slice 402F, will now be described with respect to the manner in which the stripe further includes wide cell coding and flow control conditions.
[0104]
Port slice 402F also receives data from other port slices 402A-402E, 402G, and 402H. This data corresponds to data received on the other seven ports of port slices 402A-402E, 402G, and 402H having a destination slot number corresponding to port slice 402F. Port slice 402F includes seven data FIFOs that store data from corresponding port slices 402A-402E, 402G, and 402H. An accumulator (not shown) in the seven port slices 402A-402E, 402G, and 402H extracts the destination slot number associated with port slice 402F and stores the seven data FIFOs 530 for port slice 402F. Write the data corresponding to each. As occupied in FIG. 5, each data FIFO 530 includes a FIFO controller and a FIFO random access memory (RAM). The FIFO controller is coupled to a FIFO read arbitrator 540. FIFO RAM is coupled to multiplexer 550. FIFO read arbitrator 540 is further coupled to multiplexer 550. Multiplexer 550 has an output coupled to dispatcher 560. Dispatcher 560 has an output coupled to transmit synchronization FIFO module 570. Transmit synchronization FIFO module 570 has an output coupled to serializer transmitter 580.
[0105]
In operation, FIFO RAM accumulates data. After the data FIFO RAM has accumulated one cell of data, the corresponding FIFO controller generates a read request to the FIFO read arbitrator 540. FIFO read arbitrator 540 processes read requests from each different FIFO controller in a desired order, such as a round robin order. After one cell of data has been read from one FIFO RAM, the FIFO read arbitrator 540 proceeds to the processing of the next requesting FIFO controller. In this way, arbitration is performed for each different requesting FIFO controller, and data received at each different source port is transferred. This maintains a relatively uniform but loosely coupled data flow through the cross point 202.
[0106]
The FIFO read arbitrator 540 switches the multiplexer 550 to process the read request and transfers one cell of data from the data FIFO RAM associated with the read request to the dispatcher 560. Dispatcher 560 outputs data to transmission synchronization FIFO 570. The transmit synchronization FIFO 570 stores the data and continues to store the data until it is transmitted by the serializer transmitter 580 in a serial data stream to the blade 104F.
[0107]
In the following, the cross-point operation according to the invention will be described with respect to other aspects involving wide cell coding and flow control.
[0108]
N. Second traffic processing path
FIG. 6 also illustrates a traffic processing path for backplane serial traffic received at the backplane interface adapter 600 according to aspects of the present invention. FIG. 9 shows the second traffic processing path in more detail.
[0109]
As shown in FIG. 6, BIA 600 includes one or more deserializer receivers 650, a wide / narrow cell translator 680, and a serializer transmitter 692 along a second path. Receiver 650 receives wide striped cells in multiple stripes from switching fabric 645. Wide striped cells transfer data packets. In one example, five deserializer receivers 650 receive five sub-blocks of a wide striped cell in multiple stripes. A wide striped cell transfers data packets across multiple stripes and includes source slot identifier information. In one digital switch embodiment, source slot identifier information is written to the wide striped cell as it passes through the cross point in the switching fabric as described above with respect to FIG.
[0110]
The translator 680 converts the received wide striped cells into narrow input cells that forward data packets. Serializer transmitter 692 sends the narrow input cell to the corresponding source packet processor or IBT.
[0111]
BIA 600 further includes a stripe interface 660 (also referred to as a stripe interface module) coupled between deserializer receiver 650 and controller 670, a stripe receive synchronization queue (685), and a controller 670. Each stripe interface 660 sorts the received sub-blocks in each stripe based on source packet processor identifier and source slot identifier information, and places the sorted received sub-blocks in a stripe receive synchronization queue 685. Store.
[0112]
Controller 670 includes arbitrator 672, stripe-based wide cell assembler 674, and management module 676. The arbitrator 672 arbitrates the order in which the data stored in the stripe receive synchronization queue 685 is transmitted to the stripe-based wide cell assembler 674. Stripe-based wide cell assembler 674 assembles wide striped cells based on received data sub-blocks. Narrow / wide cell translator 680 then converts the arbitrated received wide striped cells to narrow input cells that forward data packets. A management module 676 is provided to perform flow control, queue threshold level detection, and error detection (such as stripe synchronization error detection), or other desired management functions.
[0113]
According to aspects of the invention, a second level of arbitration is also performed. BIA 600 further includes a destination queue 615 and a local destination send arbitrator 690 in the second pass. Destination queue 615 stores narrow cells transmitted by traffic sensor 610 (from the first path) and narrow cells translated by translator 680 (from the second path). Local destination transmit arbitrator 690 arbitrates the order in which narrow input cells stored in destination queue 690 are transmitted to serializer transmitter 692. Finally, serializer transmitter 692 then sends the narrow input cell to the corresponding IBT and / or source packet processor (finally out of the blade via the physical port).
[0114]
FIG. 9 illustrates the second traffic processing in more detail. BIA 600 includes five components that process data slices from five slices. In FIG. 9, only two groups 900 and 901 are shown for clarity, and only group 900 needs to be described in detail with respect to one stripe. This is because the other groups of operations for the other four stripes are similar.
[0115]
In the second traffic path, deserializer receiver 950 is coupled to cross clock domain synchronizer 952. Deserializer receiver 950 converts the data slices (eg, sub-blocks) of the stripe into parallel data. Cross clock domain synchronizer 952 synchronizes the parallel data.
[0116]
Stripe interface 960 includes a decoder 962 and a sorter 964 for decoding and sorting the received sub-blocks in each stripe based on source packet processor identifier and source slot identifier information. Sorter 964 then stores the sorted received sub-blocks in stripe receive synchronization queue 965. In total, five groups of 56 stripe receive synchronization queues 965 are provided. This allows one queue to be used exclusively for each group of sub-blocks received from a particular source per global blade (up to eight transmissions per blade for seven blades not including the current blade) Former packet processor).
[0117]
The arbitrator 672 arbitrates the order in which the data stored in the stripe receive synchronization queue 685 is transmitted to the stripe-based wide cell assembler 674. Stripe-based wide cell assembler 674 assembles wide striped cells based on received data sub-blocks. Narrow / wide cell translator 680 then converts the arbitrated received wide striped cell to a narrow input cell that forwards the data packet, as described above in FIG.
[0118]
Destination queues include a local destination queue 982 and a backplane traffic queue 984. Local destination queue 982 stores the narrow cells transmitted by local traffic sorter 716. Backplane traffic queue 984 stores the narrow cells translated by translator 680. Local destination transmit arbitrator 690 arbitrates the order in which narrow input cells stored in destination queues 982, 984 are transmitted to serializer transmitter 992. Finally, the serializer transmitter 992 then sends the narrow input cell to the corresponding IBT and / or source packet processor (finally out of the blade via the physical port).
[0119]
O. Cell boundary alignment
FIG. 15D is a diagram illustrating an example of a cell boundary alignment condition when a wide striped cell is transmitted in a plurality of stripes according to an embodiment of the present invention. Encoding and wide striped cell generation ensure that there is a K0 character every 8 blocks for any given stripe. Cell boundaries between the stripes themselves may be misaligned. However, this misalignment is compensated and addressed by a second traffic processing flow path in BIA 600.
[0120]
P. Packet alignment
FIG. 16 is a diagram illustrating an example of packet boundary alignment conditions when a wide striped cell is transmitted in a plurality of stripes according to an embodiment of the present invention. Although the cells can be different from stripe to stripe, all stripes basically transmit the same packet or packets close to each other. Because each cross point arbitrates its source independently, not only can skew occur at the cell boundaries, but also the transmission of packets on one serial link and the transmission of packets on any other link. A skew of as much as 7 cell time units (time to transmit a cell) may occur during this time. This means that when transmitting multiple stripes on the switching fabric, each packet may be interlaced with other packets.
[0121]
Q. Wide striped cell size at line speed
In one example, the maximum size of a wide cell is 8 blocks (160 bytes) that can transfer 148 bytes of payload data and 12 bytes of in-band control information. Data packets for full-duplex traffic can be transferred at 50 Gbps through digital switches in wide cells.
[0122]
R. IBT and packet processing
The Integrated Packet Controller (IPC) and Integrated Giga Controller (IGC) functions include a bus translator described above as an IPC / IGC Bus Translator (IBT) 304. In one aspect, the IBT is an ASIC that connects one or more IPC / IC ASICs. In such an embodiment, the IBT converts two 4/5 Giga parallel streams into one 10 Gbps serial stream. The parallel interface may be an IPC / IGC ASIC backplane interface. For example, as described herein for interface adapters and striping, one additional 10 Gbps serial stream can be processed.
[0123]
Further, IBT 304 may be configured to operate with other architectures that will become apparent to those skilled in the art based at least on the disclosure herein. For example, IBT 304 can be implemented in a packet processor using a 10GE configuration and an OC-192 configuration. The functionality of the IBT 304 can be incorporated into an existing packet processor or be installed as an add-on component of the system.
[0124]
In FIG. 17, a block diagram 1700 illustrates components of a bus translator 1702 according to one embodiment of the present invention. The above-described IBT 304 can be configured as the translator 1702 in FIG. For example, IBT 304 may be implemented to include the functionality of bus translator 1702.
[0125]
Specifically, the bus translator 1702 converts the data 1704 into data 1706 and the data 1706 into data 104. Data 1706 is received by transceiver 1710 and forwarded to translator 1712. Translator 1712 analyzes the data 1706 and encodes it into the desired format.
[0126]
In this case, the translator 1712 converts the data 1706 into the format of the data 1704. The translator 1712 is managed by the management module 1718. One or more pools 1716 store information for data 1706 and data 1704. One or more clocks 1714 provide timing information for the translator 1712 conversion operation. When the translator 1712 completes the conversion of the data 1706, the translator 1712 transfers the newly formatted information as data 1704 to the transceiver 1708. Transceiver 1708 transfers data 1704.
[0127]
Reversing the direction of operation of bus translator 1702, receiving data 1704 by bus translator 1702, and transferring data 1706 after conversion, as will be appreciated by those skilled in the art based on the disclosure set forth herein. be able to.
[0128]
For ease of illustration without limitation, the process of converting data 1706 to data 1704 is described herein as receiving and the like. Further, for ease of illustration without limitation, the process of converting data 1704 to data 1706 is described herein as transmission or the like.
[0129]
FIG. 18 is a block diagram of a receiving component according to one aspect of the present invention. In one aspect, bus translator 1802 receives data in the form of packets from interface connections 1804a-1804n. Interface connections 1804a-1804n are coupled to one or more receivers 1808 of bus translator 1802. Receiver 1808 forwards the received packet to one or more packet decoders 1810. In one aspect, receiver 1808 includes one or more physical ports. In other aspects, each receiver 1808 includes one or more logical ports. In one particular embodiment, receiver 1808 comprises four logical ports.
[0130]
Packet decoder 1810 receives the packet from receiver 1808. The packet decoder 1810 analyzes information of the packet. In one aspect, as described in more detail below, the packet decoder 1810 may include the payload information of each packet and other information about the packet, such as creation time and location, in the beginning (SOP) portion of the packet. From the end of the packet (EOP). The packet decoder 1810 transfers the information obtained by the analysis to the memory pool 1812. In one aspect, bus translator 1802 includes a plurality of memory pools 1812. In other aspects, information may be sent to another memory pool 1818. In other aspects, the packet decoder 1810 can transfer various types of information, such as payload, transmission time, origin, etc., to different memory pools of each of the pools 1812 and 1818.
[0131]
Reference clock 1820 provides timing information to packet decoder 1810. In one aspect, reference clock 1820 is coupled to an IPC / IGC component that transmits packets via connections 1804a-1804n. In another aspect, reference clock 1820 provides reference and timing information to all parallel components of bus translator 1802.
[0132]
Cell encoder 1814 receives information from memory pool 1812. In another aspect, cell encoder 1814 receives information from another memory pool 1818. Cell encoder 1814 formats the information into cells.
[0133]
In the following description, these cells are also referred to as narrow cells. Further, cell encoder 1814 can be configured to format the information into one or more cell types. In one aspect, the cell format is a fixed size. In another aspect, the cell format is variable size.
[0134]
The cell format is described below with respect to the cell encoding and decoding processes of FIGS. 22, 23A-23B, 24, and 25A-25B.
[0135]
Cell encoder 1814 forwards the cell to transmitter 1816. Transmitter 1816 receives the cell and transmits it via interface connections 1806a-1806n.
[0136]
Reference clock 1828 provides timing information to cell encoder 1814. In one aspect, reference clock 1828 is coupled to an interface adapter component that receives cells via connections 1806a-1806n. In another aspect, reference clock 1828 provides reference and timing information to all serial components of bus translator 1802.
[0137]
Flow controller 1822 measures and controls incoming and outgoing packets by determining the status of components of bus translator 1802 and the status of components connected to bus translator 1802. Such components have already been described herein and will be described in detail with respect to the interface adapter of the present invention.
[0138]
In one aspect, the flow controller 1822 asserts the ready signal and de-asserts the ready signal when an overflow occurs in the bus translator 1802 or further connected IPC / IGC components. The traffic is controlled via the unit 1806.
[0139]
Management module 1824 performs control functions for bus translator 1802. In one aspect, management module 1824 performs error control and power on reset functions for bus translator 1802.
[0140]
FIG. 19 is a block diagram of a transmission component according to one aspect of the present invention. In one aspect, bus translator 1902 receives data in the form of cells from interface connections 1904a-1904n. Interface connections 1904a-1904n are coupled to one or more receivers 1908 of bus translator 1902. In one aspect, receiver 908 includes one or more physical ports. In other aspects, each receiver 1908 includes one or more logical ports. In one particular embodiment, receiver 1908 consists of four logical ports. Receiver 1908 sends the received signal to synchronization module 1910. In one aspect, the synchronization module 1910 is a FIFO used to synchronize the incoming cell with the reference clock 1922. Although the direct arrow from the reference clock 1922 to the synchronization module 1910 is not shown in FIG. 19, it should be noted that the two modules can communicate so that the synchronization module can synchronize the incoming cells. Synchronization module 1910 transfers data to one or more cell decoders 1912.
[0141]
Cell decoder 1912 receives cells from synchronization module 1910. The cell decoder 1912 analyzes cell information. In one aspect, the cell decoder 1912 copies the payload information of each cell and other information about the cell, such as the location of the creation, from the slot / state information portion of the cell, as described in more detail below.
[0142]
In one aspect, the cell format can be fixed. In other aspects, the cell format may be variable. In other aspects, the cells received by bus translator 1902 may be cells of a multiple cell format. Bus translator 1902 can be configured to interpret these cell formats, as will be appreciated by those skilled in the art based on the disclosure herein. The cell format will be described in detail with respect to the cell encoding process of the present invention.
[0143]
The cell decoder 1912 transfers information obtained by the analysis to the memory pool 1914. In one aspect, bus translator 1902 includes multiple memory pools 1914. In other aspects, information may be sent to another memory pool 1916. In other aspects, the cell decoder 1912 can transfer various types of information, such as payload, transmission time, origin, etc., to different memory pools of each of the pools 1914 and 1916.
[0144]
Reference clock 1922 supplies timing information to cell decoder 1912. In one aspect, reference clock 1922 is coupled to an interface adapter component that transmits cells via connections 1904a-1904n. In another aspect, reference clock 1922 provides reference and timing information to all serial components of bus translator 1902.
[0145]
Packet encoder 1918 receives information from memory pool 1914. In another aspect, the packet encoder 1918 receives information from another memory pool 1916. Packet encoder 1918 formats the information into packets.
[0146]
The packet format is determined by the configuration of the IPC / IGC components and the requirements of the system.
[0147]
Packet encoder 1918 forwards the packet to transmitter 1920. The transmitter 1920 receives the packet and transmits the packet via the interface connection units 1906a to 1906n.
[0148]
Reference clock 1928 provides timing information to packet decoder 1918. In one aspect, reference clock 1928 is coupled to an IPC / IGC component that transmits packets via connections 1906a-1906n. In another aspect, reference clock 1928 provides reference and timing information to all parallel components of bus translator 1902.
[0149]
Flow controller 1926 measures and controls incoming and outgoing packets by determining the status of components of bus translator 1902 and the status of components connected to bus translator 1902. Such components have already been described herein and will be described in detail with respect to the interface adapter of the present invention.
[0150]
In one aspect, the flow controller 1926 asserts the ready signal and deasserts the ready signal when an overflow occurs at the bus translator 1902 or further connected IPC / IGC component, Control traffic via unit 1906.
[0151]
Management module 1924 performs control functions for bus translator 1902. In one aspect, management module 1924 performs error control and power on reset functions for bus translator 1902.
[0152]
FIG. 20 shows a detailed block diagram of a bus translator according to one embodiment. Bus translator 2202 incorporates the functionality of bus translators 1802 and 1902.
[0153]
For packet processing, a packet is received by a receiver 2012 by a bus translator 2002. The packet is processed as a cell and transferred to a serializer / deserializer (SERDES) 2026. SERDES 2026 acts as a transceiver for cells processed by bus translator 2002. The SERDES 2026 transmits the cell via the interface connection 2006.
[0154]
For cell processing, it is received by the bus translator 2002 via the interface connection 2008 with the SERDES 2026. The cells are processed as packets and forwarded to transmitter 2036. Transmitter 2036 forwards the packet to the IPC / IGC component via interface connections 2010a-2010n.
[0155]
Reference clocks 2040 and 2048 are similar to reference clock 2040 already described in FIGS. Reference clock 2040 provides timing information to the serial components of bus translator 2002. As shown, reference clock 2040 provides timing information to cell encoder 2020, cell decoder 2030, and SERDES 2026. Reference clock 2048 provides timing information to the parallel components of bus translator 2002. As shown, reference clock 2048 provides timing information to packet decoder 2016 and packet encoder 2034.
[0156]
Separating serial and parallel operations as described above is a feature of aspects of the present invention. In such an embodiment, the parallel format of incoming and outgoing packets at ports 2014a-2014n and 2038a-2038b, respectively, is remapped to a serial cell format at SERDES 2026.
[0157]
Further, according to aspects of the present invention, the degree of sharing of the line speed of ports 2014a-2014n is limited only by the line speed of output 2006. The same applies to the ports 2038a to 2038n and the input 2008.
[0158]
The remapping of parallel packets to serial cells is described in detail herein, and is described in particular with respect to FIG. 21E.
[0159]
FIG. 21A shows a detailed block diagram of a bus translator according to another aspect of the present invention. The receiver and transmitter in FIGS. 18, 19, and 20 have been replaced by CMOS I / Os 2112 that can perform the same functions as described above. The CMOS I / O 2112 can be configured to accommodate various numbers of physical and logical ports that receive and transmit data.
[0160]
The management module 2140 operates as described above. As shown, management module 2140 includes management control elements and management registers. The management control element manages the operation of the bus translator 2102 and performs the reset and power on functions as described above with respect to FIGS. 18, 19 and 20. The management register can capture the operating parameters and determine the state of the bus translator 2102 based on comparisons with the captured parameters or reference to these parameters.
[0161]
Reference clocks 2134 and 2136 are similar to reference clocks 2134 and 2136 already described in FIGS. 18, 19, and 20. Reference clock 2136 provides timing information to the serial components of bus translator 2102. As shown, reference clock 2136 provides timing information to cell encoder 2118, cell decoder 2128, and SERDES 2124. Reference clock 2134 provides timing information to the parallel components of bus translator 2102. As shown, reference clock 2134 provides timing information to packet decoder 2114 and packet encoder 2132.
[0162]
As shown in FIG. 21A, memory pool 2116 includes two pairs of FIFOs. Each FIFO is paired with a header queue. The memory pool 2116 operates similarly to the memory pool already described with reference to FIGS. 18 and 20. In one aspect, the payload or information portion of the decrypted packet is stored in one or more FIFOs, and the timing, creation location, destination, and similar information are stored in a corresponding header queue.
[0163]
In addition, memory pool 2130 includes two pairs of FIFOs. Memory pool 2130 operates similarly to the memory pool already described in FIGS. 19 and 20. In one aspect, the decrypted cell information is stored in one or more FIFOs along with corresponding timing, location, destination, and similar information.
[0164]
Interface connections 2106 and 2108 connect the aforementioned interface adapter to bus translator 2102 via SERDES 2124. In one aspect, connections 2106 and 2108 are serial links. In another aspect, the serial link is divided into four lanes.
[0165]
In one aspect, bus translator 2102 is an IBT 304 that converts one or more 4 Gbps parallel IPC / IGC components into four 3.125 Gbps serial XAUI interface links or lanes. In one aspect, the backplane is an IPC / IGC interface connection. Bus translator 2102 converts incoming data into one or more cell formats.
[0166]
In one aspect, the cell format may be a 4-byte header and a 32-byte data payload. In another aspect, the header of each cell is separated by a special K character. In another aspect, the last cell of the packet is indicated by one or more special K1 characters.
[0167]
The cell format may include both fixed length and variable length cells. 36 byte (4 byte header and 32 byte payload) encoding is an example of a fixed length cell format. In another aspect, a cell format with a cell length greater than the 36 bytes (4 bytes + 32 bytes) described above can be implemented.
[0168]
In FIG. 21B, a functional block diagram shows the data path with the receiving components of the bus translator. Packet decoders 2150a-2150b transfer packet data to the FIFO and header as a pair. For example, packet decoder 2150a transfers packet data to FIFOs 2152a-2152b and sideband information to header 2154. The same process is performed for the packet decoder 2150b. The packet decoder 2150b transfers packet data to the FIFOs 2156a to 2156b, and transfers sideband information to the header 2158. Cell encoder 2160 receives data and control information, and transmits cells to a serializer / deserializer (SERDES) circuit, shown as functional elements of a serializer / deserializer (SERDES) circuit, SERDES special characters 2162 and SERDES data 2164a-2164b. Create SERDES special characters 2162 include characters used to indicate the beginning and end of the cell's data payload. The SERDES data 2164a to 2164b includes a data payload for each cell and control reception of the cell. The cell structure is described in detail below with respect to FIG. 21E.
[0169]
The bus translator 2102 has a memory pool 2116 that serves as an internal data buffer to handle pipeline call times. For each IPC / IGC component, bus translator 2102 is shown as a FIFO in memory pool 2116 in FIG.21A and as elements 2152a-2152b, 2154, 2156a-2156b, and 2158 in FIG.21B. , Two data FIFOs and one header FIFO. In one aspect, the sideband information is stored in header A or B, respectively. 32 bytes of data are stored in a ping-pong manner in one or both of the two data FIFOs A1, A2 or B1, B2. Ping-pong systems are known in the art and include alternating systems.
[0170]
In one aspect, cell encoder 2160 merges the data from each packet decoder 2150a-2150b into one 10 Gbps data stream to the interface adapter. Cell encoder 2160 merges the data by interleaving at each cell boundary. Each cell boundary is determined by a special K character.
[0171]
According to one aspect, the received packets are 32-bit aligned, while the parallel interface of the SERDES element is 64 bits wide.
[0172]
In practice, it may be difficult to achieve a line speed for an arbitrary packet length. Line speed refers to maintaining the same output speed in the cell as the speed at which packets are received. A packet may have a 4-byte header overhead (SOP) and a 4-byte tail overhead (EOP). Therefore, the bus translator 2102 must parse the packet without the delay of typical parsing and routing components. Specifically, the bus translator 2102 converts the status information and slot information in-band (along with control information) using special K characters to convert to parallel data input cell format, as described in more detail below. Merge with the data stream. Thus, in one aspect, each 32 bytes of cell data is accompanied by a 4-byte header.
[0173]
FIG. 21C is a functional block diagram of a data path having a transmitting component of a bus translator according to one aspect of the present invention. Cell decoder 2174 receives cells from the SERDES circuit. The functional components of the SERDES circuit include elements 2170 and 2172a-2172b. Control information and data are obtained by analyzing the cells and transferred to a memory pool. In one aspect, the FIFOs are maintained as pairs, shown as elements 2176a-2176b and 2176c-2176d. Each pair transfers control information and data to packet encoders 2178a-2178b.
[0174]
FIG. 21D is a functional block diagram of a data path having a native mode receiving component of a bus translator according to one aspect of the present invention. In one aspect, the bus translator 2102 can be configured in native mode. Native mode may include when a total of 10 Gbps connections are maintained at the parallel end of bus translator 2102 (indicated by CMOS I / O 2112). In one aspect, due to increased bandwidth requirements (8 Gbps to 10 Gbps), the cell format length is no longer fixed at 32 bytes. In an embodiment in which 10 Gbps traffic is sent via the bus translator 2102, control information is added when the bus translator 2102 receives an SOP from a device on the 10 Gbps link. In another aspect, the bus translator 2102 first detects a data transfer and thus adds control information when going from an idle state to an active state.
[0175]
In another aspect, as shown in FIG. 21D, the uplinking data is temporarily buffered using two separate data FIFOs, thus eliminating the need for an existing timing path.
[0176]
Although a separate native mode data path for cell-to-packet conversion is not shown, one of ordinary skill in the art should understand how to achieve this, at least based on the disclosure provided herein. You will be recognized. For example, two FIFOs can be configured exclusively for storing 10 Gbps link information. However, in one aspect, bus translator 2102 processes native mode data paths and non-native mode data paths in a shared operation, as shown in FIGS. 19, 20, and 21. I do. The header and idle bytes are removed from the data stream by cell decoders such as decoder 2103 and decoder 2174. Valid data is parsed, stored, and transferred to the parallel interface as described above.
[0177]
In other embodiments where the zero body cell format is received by the interface adapter or BIA, the IBT 304 retains the previous one data transfer for each source slot. When the IBT 304 receives an EOP having a zero body cell format, the previous one or two transfers are released and transmitted from the parallel interface.
[0178]
S. Narrow cell and packet coding process
FIG. 21E is a block diagram of a cell format according to an aspect of the present invention. FIG. 21E illustrates both an example packet and a cell according to aspects described herein. The example packet shows a beginning 2190a of the packet, a payload 2190b containing data, an end 2190c of the packet, and an inter-packet gap 2190c.
[0179]
According to one aspect of the invention, the cell includes the special character K0 2190 and control information 2194, optionally including one or more reserved bits 2196a-2196b, and finally including data 2198a-2198n. In other aspects, the data 2198a-2198n may include more data than D0-D31.
[0180]
In one aspect, the four rows or slots shown in FIG. 21E indicate the four lanes of the serial link from which cells are transmitted and / or received.
[0181]
As already described herein, the IBT 304 sends cells to and receives cells from the BIA 302 via the XAUI interface. IBT 304 sends and receives packets to and from the IPC / IGC component and other controller components (ie, a 10GE packet processor) via a parallel interface. The packet is segmented into cells consisting of 4 bytes followed by 32 bytes of data. The end of the packet is indicated by a K1 special character on any invalid data in the 4-byte transfer or four K1s on all XAUI lanes. In one aspect, each byte is serialized on one XAUI lane. The following table illustrates the right-left configuration of a byte representation of a cell according to one aspect of the present invention.
[0182]

[0183]
Packets are formatted into cells consisting of a header and a data payload. A 4-byte header requires one cycle or row on four XAUI lanes. The header has a K0 special character on lane 0 indicating that the header is currently being transferred. The control information starts on lane 1 of the header.
[0184]
In one aspect, IBT 304 accepts two IPC / IGC backplane buses and converts them into one 10 Gbps serial stream.
[0185]
FIG. 22 shows a flowchart of an encoding process for a bus translator according to one aspect of the present invention. The process starts at step 2202 and proceeds immediately to step 2204.
[0186]
At step 2204, IBT 304 determines the type of port on which it receives packets. In one aspect, each port is configured for 4 Gbps traffic from IPC / IGC components. The process proceeds immediately to step 2206.
[0187]
At step 2206, IBT 304 selects a cell format type based on the type of traffic it handles. In one aspect, the IBT 304 selects a cell format type based in part on the determination of the port type in step 2204. The process proceeds immediately to step 2208.
[0188]
At step 2208, IBT 304 receives one or more packets from the interface connection via its port, as described above. The rate at which packets are delivered depends on the component sending the packets. The process proceeds immediately to step 2210.
[0189]
At step 2210, the IBT 304 analyzes the one or more packets received at step 2208 to obtain information included therein. In one aspect, the packet decoder of IBT 304 parses the packet to obtain information contained within the payload portion of the packet and control or routing information included with each given packet header. The process proceeds immediately to step 2212.
[0190]
In step 2212, the IBT 304 optionally stores information obtained by the analysis in step 2210. In one aspect, information is stored using a memory pool of the IBT 304. The process proceeds immediately to step 2214.
[0191]
At step 2214, IBT 304 formats the information into one or more cells. In one aspect, the cell encoder of IBT 304 accesses information obtained from the analysis of one or more packets. This information includes the data being transmitted and slot and status information (ie, control information) as to where the data is being transmitted. As described above, the cell format includes special characters added to information. The process proceeds immediately to step 2216.
[0192]
In step 2216, the IBT 304 transfers the formatted cell. In one aspect, the SERDES of the IBT 304 receives the formatted cells and serializes them for transfer to the BIA 302 of the present invention. The process proceeds unless otherwise indicated.
[0193]
23A-23B, a detailed flowchart illustrates the encoding process of a bus translator according to one aspect of the present invention. The process of FIGS. 23A-23B begins at step 2302 and proceeds immediately to step 2304.
[0194]
At step 2304, the IBT 304 determines the type of port on which it receives packets. The process proceeds immediately to step 2306.
[0195]
At step 2306, the IBT 304 determines whether the type of port is above a sustainable threshold, whether it is an individual type or a combination of several types. In other words, the IBT 304 checks whether it can match the line rate of the incoming packet without reaching the internal rate maximum. If a match can be made, the process proceeds to step 2310. If not, the process proceeds to step 2308.
[0196]
Assuming in step 2308 that IBT 304 has determined to operate at its highest level, IBT 304 is a variable cell cell that allows IBT 304 to reduce the number of cells that are formatted and transferred at a later stage in the process. Choose a size. In one aspect, the cell format provides an integer multiple of each of the one or more received packets. In another aspect, IBT 304 selects a cell format that provides a variable cell size that allows a maximum length of cells to be supplied until the packet is completed. For example, if a given packet is 2.3 cells long, three cells will be formatted, while the third cell is one-third the size of the previous two cells. The process proceeds immediately to step 2312.
[0197]
If the IBT 304 determines in step 2310 that it does not operate at its highest level, it selects a certain cell size that allows the IBT 304 to process the information with lower processing overhead. The process proceeds immediately to step 2312.
[0198]
At step 2312, IBT 304 receives one or more packets. The process proceeds immediately to step 2314.
[0199]
In step 2314, the IBT 304 analyzes control information of each of the one or more packets. The process proceeds immediately to step 2316.
[0200]
At step 2316, the IBT 304 determines slot and status information for each of the one or more packets. In one aspect, the slot / state information is determined in part from control information, ie, control information obtained by analyzing each of the one or more packets. The process proceeds immediately to step 2318.
[0201]
In step 2318, the IBT 304 stores the slot / state information. The process proceeds immediately to step 2320.
[0202]
At step 2320, the IBT 304 analyzes the payload of each packet of the one or more packets to obtain the data contained therein. The process proceeds immediately to step 2322.
[0203]
At step 2322, IBT 304 stores the data obtained by analyzing each of the one or more packets. The process proceeds immediately to step 2324.
[0204]
At step 2324, the IBT 304 accesses the control information. In one aspect, the IBT 304 cell encoder accesses the IBT 304 memory pool to obtain control information. The process proceeds immediately to step 2326.
[0205]
At step 2326, the IBT 304 accesses data obtained by parsing each of the one or more packets. In one aspect, the cell encoder of IBT 304 accesses the memory pool of IBT 304 to obtain this information. The process proceeds immediately to step 2328.
[0206]
In step 2328, IBT 304 builds each cell by inserting a special character at the beginning of the currently built cell. In one aspect, the special character is K0. The process proceeds immediately to step 2330.
[0207]
At step 2330, IBT 304 inserts slot information. In one aspect, IBT 304 inserts slot information into the next lane, such as space 2194. The process proceeds immediately to step 2332.
[0208]
At step 2332, IBT 304 inserts state information. In one aspect, the IBT 304 inserts state information into the lane next to the lane used for slot information, such as reserved bits 2196a. The process proceeds immediately to step 2334.
[0209]
In step 2334, the IBT 304 inserts data. The process proceeds immediately to step 2336.
[0210]
At step 2336, the IBT 304 determines whether there is additional data to format. For example, assume that a given packet has remaining data. In this case, the process returns to step 2328. If there is no remaining data, the process proceeds immediately to step 2338.
[0211]
At step 2338, the IBT 304 inserts a special character indicating the end of the cell transmission (of one or more cells). In one aspect, the special character when the last cell was transmitted is K1. The process proceeds immediately to step 2340.
[0212]
At step 2340, IBT 304 transfers the cell. The process proceeds unless otherwise indicated.
[0213]
In FIG. 24, a flowchart illustrates the decoding process of a bus translator according to one aspect of the present invention. The process of FIG. 24 begins at step 2402 and proceeds immediately to step 2404.
[0214]
At step 2404, IBT 304 receives one or more cells. In one aspect, the cells are received by the IBT 304 SERDES and transferred to the IBT 304 cell decoder. In another aspect, the SERDES of the IBT 304 transfers the cells to a synchronization buffer or queue that temporarily holds the cells so that the proper order of the cells can be maintained. These steps are described below with respect to steps 2406 and 2408. The process proceeds immediately to step 2406.
[0215]
At step 2406, IBT 304 synchronizes one or more cells in an appropriate order. The process proceeds immediately to step 2408.
[0216]
At step 2408, the IBT 304 optionally checks one or more cells to determine if these cells are in their proper order.
[0219]
In one aspect, steps 2506, 2508, and 2510 are performed by a synchronous FIFO. The process proceeds immediately to step 2410.
[0218]
At step 2410, the process by which the IBT 304 analyzes one or more cells to obtain control information and payload data proceeds immediately to step 2412.
[0219]
At step 2412, IBT 304 stores control information and payload data. The process proceeds immediately to step 2414.
[0220]
At step 2414, IBT 304 formats the information into one or more packets. The process proceeds immediately to step 2416.
[0221]
At step 2416, IBT 304 forwards the one or more packets. The process proceeds unless otherwise indicated.
[0222]
25A-25B illustrate a detailed flow chart of the decoding process of a bus translator according to one aspect of the present invention. The process of FIGS. 25A-25B begins at step 2502 and proceeds immediately to step 2504.
[0223]
At step 2504, IBT 304 receives one or more cells. The process proceeds immediately to step 2506.
[0224]
At step 2506, the IBT 304 optionally queues one or more cells. The process proceeds immediately to step 2508.
[0225]
At step 2508, the IBT 304 optionally determines whether the cells have arrived in an appropriate order. If so, the process proceeds immediately to step 2512. If they have not arrived in the proper order, the process proceeds immediately to step 2510.
[0226]
At step 2510, the IBT 304 holds one or more of the one or more cells until the proper order is restored. In one aspect, if a cell is lost, the IBT 304 performs an error control function as described herein, interrupting the transfer and / or resuming the transfer. The process proceeds immediately to step 2514.
[0227]
In step 2512, the IBT 304 analyzes the cell to obtain control information. The process proceeds immediately to step 2514.
[0228]
At step 2514, the IBT 304 determines slot / status information. The process proceeds immediately to step 2516.
[0229]
At step 2516, the IBT 304 stores the slot / state information. The process proceeds immediately to step 2518.
[0230]
In one aspect, the state / slot information includes configuration information as shown in the table below.

[0231]
In one aspect, IBT 304 has a configuration register. Configuration registers are used to enable the backplane and IPC / IGC destination slots.
[0232]
At step 2518, the IBT 304 analyzes the cell to obtain data. The process proceeds immediately to step 2520.
[0233]
At step 2520, IBT 304 stores the data obtained from the analysis of each of the one or more cells. The process proceeds immediately to step 2522.
[0234]
At step 2522, IBT 304 accesses control information. The process proceeds immediately to step 2524.
[0235]
At step 2524, IBT 304 accesses the data. The process proceeds immediately to step 2526.
[0236]
At step 2526, IBT 304 forms one or more packets. The process proceeds immediately to step 2528.
[0237]
At step 2528, the IBT 304 transfers one or more packets. The process proceeds unless otherwise indicated.
[0238]
T. Management process and error control
This section describes possible error conditions on serial links and cross-point switches in the backplane and various error control aspects of the present invention. Various recovery and reset routines of the present invention are also described.
[0239]
The routines described herein are generally configured to detect, prevent, and recover from errors having the following properties:
[0240]
1) Link errors: Link errors occur as a result of bit errors or byte alignment problems in SERDES. As the clock is recovered from the data stream, byte alignment problems can occur if there are not enough data transitions. Bit errors can occur as a result of external noise on the line. SERDES can also detect exceptional conditions such as SOP characters in lane 1, and can mark such conditions as link errors.
[0241]
2) Lane synchronization error: A lane is defined as one serial link between the four serial links that make up a 10Gbps SERDES. As described elsewhere herein, four deep FIFOs in the SERDES core are provided to compensate for transmission line skew and synchronize each lane so that the integrated 10 Gbps stream is provided to the core logic. is there. The FIFO can overflow or underflow, resulting in lane synchronization errors. Lane synchronization sequences can also cause alignment problems.
[0242]
3) Stripe synchronization error: A stripe synchronization error refers to an error in the wide cell flow of data transmitted over multiple stripes over the switching fabric according to the present invention. Such a stripe synchronization error (also referred to as a stripe synchronization error condition or simply an error condition) is caused by a link error in the serial pipe to or from the cross point or an error in the cross point itself. there is a possibility.
[0243]
In one aspect, the receiving BIA includes a deep FIFO (such as 56 FIFOs or 64 FIFOs) that is sorted according to source and stripe. Stripe synchronization errors can be detected by monitoring the FIFO and detecting overflow and / or underflow of one or more FIFOs in the striped data path. In other situations, each stripe may be out of sync at all. In one recovery aspect, some or all XPNT modules arbitrate independently, i.e., each XPNT module operates independently and clears the affected FIFO as described elsewhere herein. To recover from a known state.
[0244]
Other error conditions and combinations of error conditions are possible, as will be apparent to those skilled in the art based at least on the disclosure herein.
[0245]
Routines for detecting and preventing these error conditions are described generally below, and then with respect to the detailed aspects of the present invention.
[0246]
In general, the present invention can manage a bus translator as shown in FIG. Referring to FIG. 26, a flowchart illustrates a bus translator management process according to one aspect of the present invention. The process of FIG. 26 begins at step 2602 and proceeds immediately to step 2604.
[0247]
At step 2604, the IBT 304 determines the status of the internal component. The process proceeds immediately to step 2606.
[0248]
At step 2606, the IBT 304 determines the status of the link with the external component. The process proceeds immediately to step 2608.
[0249]
At step 2608, the IBT 304 monitors the operation of the internal and external components. The process proceeds immediately to step 2610.
[0250]
At step 2610, the IBT 304 monitors a register for a management command. The process proceeds immediately to step 2612.
[0251]
At step 2612, IBT 304 performs a reset of the given component in response to the instruction. The process proceeds immediately to step 2614.
[0252]
At step 2614, IBT 304 configures the operation of the given component. The process proceeds unless otherwise indicated.
[0253]
In one aspect, any errors detected at the receiving end of BIA 302 are handled in the same manner as the error control methods described herein with respect to errors received on XPNT 202 from BIA 302. In an operation mode in which the BIA 302 cannot know the destination slot under certain conditions, the following process is executed by the BIA 302.
[0254]
a. Send a packet abort (AOP) signal to all slots.
[0255]
b. Wait for the error to clear, that is, to clear or flush the buffer.
[0256]
c. After the buffer is cleared, the SOP starts accepting data in synchronization with the first K0 token.
[0257]
If an error is detected at the receiving end of the IBT 304, the error is handled as if it were seen by the BIA 302 from the IBT 304. The following process is used.
[0258]
a. Send AOP to all downstream IPC / IGC slots and end any ongoing packets.
[0259]
b. Wait for the buffer to fill and clear the data that caused the error.
[0260]
c. After the error is resolved (after the buffer is flushed), data reception starts in synchronization with the K0 token.
[0261]
(1) BIA management module
In one aspect, the management module 676 of FIG. 6 performs the monitoring / detection / correction functions of the present invention. In particular, management module 676 handles stripe synchronization errors. As shown in FIG. 28A, the management module 676 may include a level monitor 2806, a stripe synchronization error detector 2808, a control character (K2) presence tracker 2810, and a flow controller 2812. The level monitor 2806 checks the FIFOs and the amount of data in each FIFO and / or the group FIFO associated with a particular stripe and source (such as a slot or a particular source packet processor of a slot). Is determined.
[0262]
The stripe synchronization error detector 2808 detects a stripe synchronization error based on the state of the FIFO monitored by the level monitor 2806. A stripe synchronization error may be any error in the wide cell flow of data transmitted over multiple stripes over the switching fabric according to the present invention. Such a stripe synchronization error may be a link error in the serial pipe to the cross point or a serial pipe from the cross point, or an error due to an error in the cross point itself. For clarity, the serial pipe link error from the sending BIA to the cross point is called the "incoming link error" and the serial pipe link error from the cross point to the receiving BIA. Is called an "outgoing link error." When a stripe synchronization error is detected, the stripe synchronization error detector 2808 sends a signal to the flow controller 2812. Flow controller 2812 then initiates the appropriate recovery routine to resynchronize the data flow across each stripe in the switching fabric. In particular, such a recovery routine may include transmitting control characters (such as special K2 characters) across each stripe in the switching fabric. The control character (K2) presence tracker 2810 monitors special K2 characters received in the data flow in BIA. The flow controller 2812 also constitutes the control logic of the management module 676 and each module in the management module. The flow controller 2812 allows each module of the management module 676 to send and receive information regarding the status of various FIFOs, BIAs, XPNTs, and other components of the present invention, thereby enabling the functions of each module described herein. Can be performed. In the following, examples of detecting and recovering from a stripe synchronization error will be further described with reference to FIG. 28B.
[0263]
FIG. 28B illustrates a switch 2800B having slots 2852, 2854 coupled to slot 2852 via five cross points (sXPNT) 2856A-2856E according to the present invention. Slot 2852 contains a set of synchronous receive queues or FIFOs 2860. Serial link 2853 connects slot 2852 with cross point 2856A. Serial link 2857 couples cross point 2856A and slot 2858. Slots 2852 and 2854 are also referred to as slot 0 and slot 1, respectively, and slot 2858 is also referred to as slot 2. For clarity, only two slots are shown in this example, but other slots can be added.
[0264]
Consider the example where a wide cell of data is transmitted from slot 0 and 1 to slot 2858 over stripes 0-4 via respective cross points 2856A-2856E. Certain errors can occur when the link between slot 0 2852 and xpnt0 2856A is broken. In such a case, xpnt0 2856A detects a broken link that causes an error signal to be sent back to source slot 0 2852. This causes slot 0 2852 to stop transmitting traffic and send out a K2 sequence. The xpnt0 2856A can send abort cells (AOPs) to all destinations and notify these destinations that an error has occurred. In one aspect, this occurs immediately after the error is detected.
[0265]
In other embodiments, xpnt1 2856B to xpnt4 2856E still transmit data from slot 0 2852 and slot 1 2854 to slot 2 2858, while xpnt0 2856A because link 2853 is broken between slot 0 2852 and xpnt0 2856A. There is a momentary situation in which only transmits data from slot 1 2854. For this reason, the synchronization queue in slot 2 2858 corresponding to stripe 0 / slot 1 link may overflow because it receives more data from slot 1 2854 than other stripes. The queue in the corresponding slot 22858 may underflow because this link is broken. FIG. 31 shows how obvious such an error condition in the incoming link 2853 is at each level of data present in the FIFO 2862 in slot 2. FIG. 31 shows ten FIFOs 2862 sorted by stripe and source slot. In this example, five stripes 0-4 and two slots 0 and 1 are shown. As shown in FIG. 31, due to an incoming link error, the synchronization queue in slot 2 2858 corresponding to stripe 0 / slot 1 link receives more data from slot 1 2854 than the other stripes. There is a risk of overflow and the queue in slot 2 2858 corresponding to stripe 0 / slot 0 2852 may underflow because link 2853 is broken.
[0266]
The management module 676 can detect such a strip synchronization error condition as follows. The level monitor 2806 monitors the level of each FIFO 2862. Stripe synchronization error detector 2808 then detects the presence of an overflow and / or underflow condition at the level of the stored FIFO. In this example of an incoming link error, the stripe synchronization error detector 2808 detects the occurrence of an underflow condition in the FIFO for stripe 0 / slot 0 and an overflow condition in the FIFO for stripe 0 / slot 1. Stripe synchronization error detector 2808 sends a signal to flow controller 2812. Flow controller 2812 then initiates the appropriate recovery routine to resynchronize the data flow across each stripe in the switching fabric. In particular, such a recovery routine may include transmitting a control character (eg, a special K2 character) from slot 0 across each stripe in the switching fabric. The control character (K2) presence tracker 2810 monitors special K2 characters received in the data flow in BIA.
[0267]
In the above example, slot 0 2852 sends a K2 sequence when it can send a K2 sequence that allows each queue to synchronize. Synchronization is performed on the first K0 character transmitted from slot 0 2852 with the SOP, in other words, synchronization is performed on the first new packet after K2. Since the synchronization queue corresponding to slot 1 / stripe 0 in slot 2 2858 can overflow, it stops transmitting data from slot 1 2854 and therefore slot 1 2852 as a result of link failure. A flow control event is sent from slot 22858 to xpnt0 2856A that prevents traffic from 2854 and keeps the data synchronized from slot 1 2854.
[0268]
In another example, XPNT0 2856A stops working and can no longer work. In such a case, the switch shown in FIG. 28B fails. As described below, the entire system will still function due to the presence of the redundant switch fabric and redundant fabric transceiver (RFT) of the present invention. In such a case, the RFT can detect a link failure and switch to the fabric of another switch according to the steps outlined below.
[0269]
In another example, link 2857 between xpnt0 2856A and slot 2 2858 is broken. In such a case, the BIA in slot 2 detects the destruction. In one aspect, the BIA RFT detects disruption, as described below with respect to aspects of the invention. The BIA's flow controller 2812 sends a flow control event / signal back to xpnt0 2856A, which propagates to slot 0 2852, slot 1 2854, and any slots present in the system. This allows the source slot to stop transmitting traffic to slot 22858. These slots can still send traffic to other destination slots similar to slot 22858. On the other hand, the BIA interrupts the partial packet it is receiving and waits for the K2 sequence to recover the link. As described herein, the BIA synchronizes with the first SOP following K2. The presence of the first SOP following K2 can be detected by the control character presence tracker 2810.
[0270]
The function of the management module 676 will be further described with reference to FIG. In FIG. 29, a flowchart illustrating a routine for maintaining synchronization of striped cell traffic is described.
[0271]
At step 2902, module 676 transmits a common control character in the striped cells in all lanes for a predetermined number of cycles. In one aspect, some common control characters are transmitted through the system.
[0272]
At step 2904, module 676 evaluates the common control characters received on the stripe receive synchronization queue. Module 676 evaluates the received common control characters and determines whether to resynchronize the system.
[0273]
At step 2906, module 676 determines a resynchronization condition. If the system is resynchronizing, the routine proceeds to step 2910. If the system has not resynchronized, the system proceeds to step 2908. In one aspect, module 676 determines whether the FIFOs are all empty or cleared at the same time. In another aspect, module 676 checks the status bits of each FIFO.
[0274]
At step 2908, module 676 generates an error message or other management signal. In one aspect, module 676 generates an error message so that other components of the system can initiate a new recovery action.
[0275]
At step 2910, the module 676 returns to step 2902 and waits to receive an error condition or a management command to start the routine 2900.
[0276]
Another routine for module 676 is shown in FIG. In FIG. 30, a flow chart (routine) 3000 illustrates a routine for asynchronous traffic flow through a cross point switch in a backplane switching fabric. In one aspect, the routine 3000 causes the module 676 to determine when the routine 2900 is needed.
[0277]
At step 3002, module 676 monitors the level of the stripe receive synchronization queue. In one aspect, level monitor 2806 performs this function within module 676.
[0278]
At step 3004, module 676 determines whether an asynchronous queue threshold, such as an overflow and / or underflow condition, has been detected. In one aspect, stripe synchronization error detector 2808 performs this function within module 676. If an asynchronous queue threshold is detected, the process proceeds to step 3006. If no asynchronous queue threshold is detected, the process proceeds to step 3002. In one aspect, module 676 does not transmit error messages or signals that can be received by other systems and recorded for future reference.
[0279]
At step 3006, module 676 generates an asynchronous message or other management signal that signals other components of the present invention that synchronization has been lost. In one aspect, the flow controller 2812 sends a signal back to the sending SXPNT, which is further sent back to the RFT, which instantiates the K2 sequence of the present invention as described elsewhere herein. be able to.
[0280]
At step 3008, module 676 initiates a resynchronization routine for striped cell traffic across all lanes. In one aspect, module 676 initiates the routine of FIG.
[0281]
Implements management module 676 and any of level monitor 2806, stripe management error detector 2808, control character (K2) presence tracker 2810, and flow controller 2812 in software, firmware, hardware, or a combination thereof can do. Further, the functions performed by the management module 676 and each of the level monitor 2806, the stripe management error detector 2808, the control character (K2) presence tracker 2810, and the flow controller 2812 are described in terms of modules or blocks for convenience. . However, such module boundaries and distribution of functions between modules are exemplary and not limiting. The functions of the management module 676 and each of the level monitor 2806, the stripe management error detector 2808, the control character (K2) presence tracker 2810, and the flow controller 2812 may be combined as a single module or in any combination of modules. It can be dispersed.
[0282]
(2) Redundant fabric transceiver
In the following, other detailed aspects of the present invention are described with respect to one or more redundant fabric transceiver (RFT) implementations that implement the functionality of module 676.
[0283]
According to an aspect of the present invention, an RFT ASIC is provided between one SBIA ASIC and two switching fabric modules (SFM) to provide switching redundancy in the switching system described herein.
[0284]
32A-32B show the basic connections of the switch fabric. In FIG. 32A, FIG. 3200A shows a non-redundant switching system. Blade A 3202 communicates with blade A 3206 via switch A 3204. Both blade A and blade B handle incoming and outgoing traffic. In FIG. 32B, FIG. 3200B shows a redundant switching system. Blade A 3202 communicates with blade B 3206 via two switches A 3204 and B 3205, respectively. A multiplexer (MUX) 3208 selects one of the two signals from the switches 3204 and 3205.
[0285]
For the redundancy switch of FIG. 32B, fabric active 3210 feeds all slave modules (in / out). In one aspect, a point-to-point serial link on the backplane is used. This redundant approach uses twice as many serial links as the non-redundant approach. Thus, the ingress module 3202 sends incoming traffic to the active SFM and sends idle traffic patterns to the standby SFM. In one aspect, the active SFM is switch 3204 and the standby SFM is switch 3205. Egress blade 3206 receives two data paths of traffic from these SFMs. Outgoing blade 3206 selects an active signal in response to an indication of fabric active 3210.
[0286]
Thus, the RFT of the present invention performs redundant switching and converts the encoded source / destination slot information to address the following tasks: i) operation as a multiplexer and demultiplexer; ii) flow control. Iii) flow control generation, iv) SERDES, and v) error handling. Thus, RFT is an implementation of the present invention that performs the functions already described herein with respect to module 676.
[0287]
FIG. 33A is a detailed diagram 3300A showing one aspect in which RFT is implemented in a redundant system. As shown, switching blade (SFM-A) 3302 and switching blade (SFM-B) 3304 are coupled to a backplane 3306 that is coupled to an input / output blade (slave module) 3308. Blades 3302 and 3304 each include an SXPNT that sends and receives data over a data path. As shown in FIG. 33A, blade 3302 includes SXPNT 3310A-3310E and blade 3304 includes SXPNT 3312A-3312E. Each group of SXPNTs 3310A-3310E and 3312A-3312E are coupled to data paths 3311A-3311E and 3313A-3313E, respectively, and to one or more RFTs 3316A-3316E in blade 3308 via backplane connection 3306. Have been.
[0288]
Within blade 3308, in one aspect, there is one RFT for each stripe received. RFTs 3316A to 3316E transfer the received data to SBIA3320. In another aspect, one RFT forms a bridge of XAUI links (eg, 15 links, 10 links from switching blades, 5 links from SBIA). Since some reliable aspects require four SERDES for each XAUI link, such implementations are likely to require tens of SERDES. Furthermore, if one RFT is used, this one RFT handles all traffic, which may introduce valnulability into the system. Thus, in the illustrated embodiment of the five RFT modules, the processing workload is logically divided.
[0289]
FIG. 33B is a diagram 3300B of an RFT according to one embodiment of the present invention. FIG. 33B shows that RFT 3300B is implemented in the same way that RFT 3316A is implemented for stripe 0 traffic from SXPNTs 3310A and 3312A. As described elsewhere herein, SERDES 3350 and 3352 form a data interface and route traffic to SYNCHQ FIFOs 3354 and 3356, respectively, as shown in FIG. 33B.
[0290]
In one aspect, the received serial data is converted to parallel data by SERDES, as described elsewhere herein. With this data, the clock can be recovered from the incoming data stream. Thus, each SERDES generates a clock recovered from the data. In one aspect, FIFOs 3354 and 3356 provide clock compensation for data transmission and reception by adding and / or removing idle characters from the FIFO data stream. Both FIFO 3354 and FIFO 3356 supply data to MUX 3358. MUX 3358 combines incoming traffic, splits outgoing traffic, and provides both data / control and flow control signals to redundant stripes.
[0291]
In one aspect, all traffic is routed to a symmetric architecture for uplink / downlink logic. This architecture is illustrated in FIG. 33B by components 3360, 3362, and 3364, and components 3366, 3368, and 3370. BIA_RX3370 and BP_RX3360 receive deserialized and synchronized packet data from the FIFO. The SYNCQ FIFO 3372 performs the same function as the FIFOs 3354 and 3356 described above, but for the SERDES 3374, the BIA_RX 3370 sorts the data into seven logical data queues in the UPLINK_RAM 3368 based on the encoded destination slot number ( For example, seven queues are used to sort packets with different destinations). Similarly, BP_PX sorts the data into DOWNLINK_RAM3362 based on the encoded source slot number.
[0292]
In one aspect, paging times in SERDES 3350, 3352, and 3374 are compensated by slowing down traffic on the seven logical data queues described above.
[0293]
Both the BIA_TX3364 and BP_TX3366 modules arbitrate read operations from the downlink / uplink RAMs 3362 and 3368, respectively, and constitute the data to be transmitted.
[0294]
The RFT register 3376 has access to internal registers that can be managed from the module 676. The operation of each module of the RFT 3300B depends on the parameters set in each register of the module 3376. In one aspect, module 3376 provides module 676 with information regarding the status of each module of RFT 3300B.
[0295]
As described above with respect to FIG. 33A, the backplane establishes a connection between the switching fabric module and the slave module. In one aspect, the connections include, but are not limited to, i) serial TX and serial RX pairs, ii) flow control data and synchronization, iii) cross point error signals, intercept signals, fabric active signals, and the like. And iv) clock distribution signals.
[0296]
The packet encoding scheme has been described in detail with respect to sections I and J above, and the striping scheme has been illustrated with respect to FIG. With particular attention to the RFT, the processes of FIGS. 26, 29, and 30 have been described with respect to the RFT of the present invention.
[0297]
In one aspect, the maximum size of the payload transferred on the backplane is 160 bytes (148 bytes data max, 10 bytes "Start of Cell" (SOC) control information, and two reserved bytes. ). In this embodiment, a complete 160 byte transfer is referred to as a "cell." The cells are not limited by this aspect, as described elsewhere herein. Thus, one cycle is a single 3.2 ns clock pulse (ie, 312.5 MHz). Cell transfers can occur in 20 byte "blocks" in eight consecutive cycles (as shown in FIG. 15A).
[0298]
The "status" byte can be assigned as shown in the table below.

[0299]
Note that the information in this table is similar to the information already described with respect to FIGS. 25A-25B for IBT to BIA. Here, we discuss XPNT from BIA. In each aspect, there may be three special K characters for the encoding scheme: K0 (SOC), K1 (EOP), and K2 (stripe synchronization).
[0300]
K0 indicates "beginning of cell" which is the first block of cells across all five stripes.
[0301]
K1 indicates "end of packet" that can appear in any block of the cell. It is transparent to RFT and SXPNT.
[0302]
K2 is used to encode the stripe synchronization sequence. Stripe synchronization requires sending K2 characters across all lanes and all stripes. In one aspect, the special character is transmitted 112 times. Thereafter, all stripes in the sync queue are marked "in sync". The number 112 was chosen because it matches the depth of the synchronization queue in this embodiment, and therefore, if there is no data remaining in the queue after the last K2 was detected, this is considered a stripe synchronization error. Because they can be considered. The invention is not limited by this aspect, and the synchronization queues may have different depths.
[0303]
As will be appreciated by those skilled in the art based on the disclosure set forth herein, the function of implementing special characters is filling / flushing the synchronization queue. In one aspect, the SBIA transmits the pattern shown in FIG. 34A 112 times.
[0304]
In one aspect, the status field is encoded with the source slot number and one bit is used to indicate whether the cell is near the beginning or end of the sequence. For example, the status field can be encoded with the source slot number and whether the cell is in the middle of the first 96 transfers (of 112) in the stripe sequence, or if this is (112 The last 16 K2 transfers, of which one bit is used to indicate whether valid data is transmitted.
[0305]
The K2 sequence synchronization routine is shown in flowchart 3450 of FIG. 34B. The K2 sequence needs to arrive in consecutive cycles to synchronize the five stripes in SBIA. To ensure this, the following routine is started.
[0306]
At step 3452, the source SBIA checks for the ready state of the RFT / SXPNT.
[0307]
In step 3454, the RFT / SXPNT returns its status. If the RFT / SXPNT is ready, the routine proceeds to step 3456. If the RFT / SXPNT is not ready, the routine returns to step 3452. In one aspect, the source SBIA may recheck after a predetermined period.
[0308]
In step 3456, the source SBIA sends an idle character to RFT / SXPNT. In one aspect, the source SBIA sends enough idle characters to give the destination SBIA enough time to pull the remaining data from the destination SBIA buffer. In one aspect, the source SBIA transmits 768x2 idle characters.
[0309]
In step 3458, the source SBIA sends a special character (K2) to RFT / SXPNT. In one aspect, the FIFO in the RFT / SXPNT for the source slot should be empty by the time K2 is transmitted. If the FIFO is not empty when the RFT / SXPNT receives the K2 sequence, it regards this sequence as an error in the data received by the SBIA. When the RFT successfully receives the data, it checks if the SXPNT is ready to receive the data before sending the K2 sequence. In one aspect, the K2 sequence, once transmitted from RFT to SXPNT, does not stop until the entire sequence has been transmitted. In one aspect, 112 K2 characters are transmitted.
[0310]
Steps 3460, 3462, and 3464 illustrate the situation described above.
[0311]
At step 3466, the source SBIA sends more idle characters to RFT / SXPNT and clears the remaining K2 characters from the buffer. In one aspect, the source SBIA transmits 512x2 idle characters.
[0312]
In one aspect, routine 3450 is periodically executed by module 676 to clear the FIFO and resynchronize the system of the present invention.
[0313]
The discussion of FIG. 34B emphasizes the importance of the SXPNT and SBIA clocks. This is because this clock should maintain stringent jitter and rise time requirements for the proper execution of routine 3450. In addition, due to the striping nature of RFT and SXPNT, it is necessary to maintain synchronization at all times. Thus, the various aspects of the routines described herein, and of these routines for error detection and recovery, are of particular importance.
[0314]
Embodiments of the present invention can implement both synchronous and asynchronous systems. In an asynchronous system, all blades, including the fabric, use the same clock source. The clock source can be located on the fabric and distributed to each slave module across the backplane so that the backplane acts as a purely passive component.
[0315]
In one aspect of a redundant switch fabric system, two system clocks can be sent from two switch fabric modules to one slave module. The circuit on the slave module works as the master clock. If the master clock fails in the event of a failover, the other clock becomes the master clock and the switching should be transparent to the components on the slave module.
[0316]
In asynchronous systems, the system decouples clock domains between blades. This means that every blade now has its own clock source. The purpose of configuring an asynchronous system is to eliminate the stringent jitter requirements imposed by the clock signal provided by the MUX. However, this system raises new problems with resynchronization of the interface signals at both ends (at the slave module).
[0317]
In the case of the SERDES signal, as already explained above, there is some built-in function to provide RX clock compensation when TX and RX use different clock sources. However, enabling RX compensation increases the ring time inside the SERDES.
[0318]
With respect to the flow control signals described above, the system implements control logic on the fabric and decodes time division multiplexed (TDM) signals into parallel signals, eliminating the need for a central ready synchronization signal. Detailed embodiments will be described below.
[0319]
In the case of synchronous flow control implementation, the flow control information passing between SXPNT and RFT is TDM, and the start of the time slot needs to be defined by the common synchronization signal. A central synchronization signal that tracks clock distribution increases the robustness of the system.
[0320]
FIG. 35 is a block diagram 3500 of the synchronous flow control mode including the RFT. Blade module 3502 includes five SXPNTs 3508A-3508E. The flow controller module 3506 generates various signals as described herein. In one aspect, module 3506 provides a clock signal to each component of the system. Blade module 3504 receives signals across the backplane connection to RFTs 3510A-3510E. The RFT sends and receives signals to and from the SBIA3512. A flow controller module 3504 is coupled across the backplane to each of the RFTs 3510A-3510E and the SBIA 3512.
[0321]
In one aspect, there are two sets of flow control signals across the backplane. In other aspects, more than two signals are used for flow control. In the former mode, the following ready signal is implemented.
[0322]
a) Ready to receive: Each SBIA 3512 has a dedicated 1-bit ready signal for each RFT 3510A to 3510E that stops transmitting packets from each specific slot to a specific stripe. Each RFT 3510A-3510E also transmits a dedicated 1-bit ready signal that controls the reception of packets from a particular source SXPNT 3508A-3508E based on available space in an internal receive FIFO (eg, downlink RAM).
[0323]
b) Transmission ready: Each SXPNT has a dedicated 2-bit ready signal for each RFT 3510A-3510E that signals the congestion status at the destination slot. Every SBIA 3512 receives a 2-bit ready signal from each RFT 3510A-RFT 3510E that stops traffic for the destination slot.
[0324]
In one aspect, a common synchronization signal is used to synchronize all transmit ready and receive ready signals between RFT / SXPNT and RFT / SBIA. For example, and not by way of limitation, the ready-to-transmit signal encodes seven states in four slots (8 cycles) using two bits, and the ready-to-receive signal uses seven bits (14 Encode the seven states in the cycle). The common sync may be a sync pulse every 56 cycles, which is the least common multiple of 8 and 14. Of course, the invention is not limited to these cycle numbers, and those skilled in the art will recognize that different durations can be implemented.
[0325]
In one aspect, the time slot for each state can be set to 78.125 MHz if one-half of the core frequency is 78.125 MHz, ie, if the core frequency is 156.25 MHz. The reason for using the two-cycle approach to time slots is to provide a two-cycle margin for the wire / cell delay between the SBIA ready register and the SXPNT ready register.
[0326]
FIG. 36 is a time flow diagram of how SBIA interprets the ready signal from SXPNT. A sync pulse is used to reset both SBIA and SXPNT internal counters. When the value of the counter is 55 or 0, as shown in FIG. 36 for illustration, the SXPNT internally sends a ready state corresponding to slots 1 and 0. When the counter is equal to 1 or 2, SXPNT encodes the slot 2 ready signal and the slot 3 ready signal, and so on. This pattern repeats every eight cycles. In other words, every slot is encoded seven times between two sync pulses.
[0327]
In a detailed embodiment, after three cycles, the ready status signal crosses the backplane. The SBIA then adds another two cycles of call time to the ready signal. Thus, when the count is equal to 5, the ready signal is latched inside the SBIA. This makes the path a true multi-cycle path from SXPNT to SBIA.
[0328]
When the RFT is placed between SBIA and SXPNT, the flow control operation is executed as it is. However, the SBIA / RFT and SXPNT / RFT call times are programmable to leave extra margin in the hardware trace. Thus, in aspects of the present invention, the paging time level of the system can be predetermined and thus an offset introduced to better predict the operating parameters of the system.
[0329]
Like FIG. 35, FIG. 37 shows the switching system of the present invention with asynchronous flow control. System 3700 includes a blade module 3702 having SXPNTs 3708A-3708E and a blade module having RFTs 3714A-3714E. In one aspect, similar to FIG. 35, the flow controller modules 3706 and 3707 can provide clock signals to components of the system.
[0330]
Flow control between SXPNTs 3708A-3708E and RFTs 3714A-3714E can be changed asynchronously via control logic module 3710 in blade 3702 and module 3712 in blade 3704. In one aspect, the control logic module 3710 is located on the fabric and serves as a synchronous flow control interface for the SXPNTs 3708A-3708E. Control logic module 3710 can receive, interpret, and transmit various signals. In one aspect, module 3710 performs the following operations.
[0331]
a) Decode the 2-bit transmission ready signal as a 7-bit ready signal from each SXPNT 3708A-3708E, and combine these ready signals to generate a 7-bit transmit slot ready signal to each of the RFTs 3714A-3714E.
[0332]
"Merge" means that if there is an SXPNT that is not ready for a particular slot, no RFT is allowed to send packets for that slot. This is different from synchronous systems that have independent flow control between stripes.
[0333]
b) Receive from the RFT a 7-bit receive slot ready signal, which is also a combination ready signal from five stripes, encoded in five 1-bit receive ready signals for SXPNT.
[0334]
With respect to the RFT aspects described herein, potential error conditions on the serial link and backplane, and preventive and remedial measures are described. Further, an aspect of a failover procedure for changing from one switch blade to another switch blade will be described.
[0335]
The RFT module of the present invention may be located on the receiving side of the above error. The types of errors that can be detected by the RFT chip include:
[0336]
a) Link error: This can occur as a result of a bit error or a byte alignment error. In one aspect, the SERDES should send a "/ E" special character (error notification character) indicating a link error on the parallel data path.
[0337]
b) Lane synchronization error: This is a synchronous FIFO overflow / underflow. In one aspect, the SERDES should send a "GLINK" signal indicating a receiving lane synchronization error.
[0338]
c) Format error: This occurs because the cell format is incorrect. In one aspect, the "/ K0" special character that appears in lanes other than lane 0 indicates a format error.
[0339]
d) XPNT error: This is a wire or signal from five SXPNT chips. In one aspect, this signal indicates an error in the SXPNT or a problem with the received data.
[0340]
The RFT error handling routine conforms to the previously described routines (eg, the routines of FIGS. 29, 30, and 34B).
[0341]
In one aspect, in transmission from the SBIA to the RFT, the RFT detects an error in data received from the SBIA. This error may include a link error, a lane synchronization error, and a format error. After an error is detected, the following procedure (steps 1-4) can be applied to recover from the error.
[0342]
1) Send an RFT error signal to SBIA. SBIA stops transmitting data at the cell boundary and repeats the lane synchronization sequence until the RFT deasserts the RFT error. In one aspect, after deassertion, a stripe synchronization sequence is sent for all slots (eg, as described with respect to FIG. 34B).
[0343]
2) Send AOP to all slots and flush uplink RAM. If an error is detected in the received data, the encoded destination slot may be malfunctioning. Therefore, an abort signal is transmitted to all destination slots, and the already transmitted packet is discarded.
[0344]
3) Wait for the buffer to be cleared, thus clearing the error.
[0345]
4) Wait for stripe sync sequence and SOP to start accepting data.
[0346]
In one aspect, in a transmission from the SXPNT to the RFT, the RFT detects an error in data received from one of the SXPNTs to which it is connected. This error may include a link error, a lane synchronization error, and a format error. After one or more errors are detected, the following procedure can be applied to recover from the errors.
[0347]
1) Stop SXPNT from receiving more data in this slot.
[0348]
2) Send AOP to SBIA for all slots and flush downlink RAM.
[0349]
3) Wait for the buffer to be cleared, thus clearing the error.
[0350]
4) Wait for stripe sync sequence and SOP to start accepting data.
[0351]
In an aspect of the invention, the RFT error signal notifies the SBIA that the RFT is in error so that the SBIA stops transmitting packets to the RFT. This signal includes the following error notification.
[0352]
a) Cross point error: This is a wire or result from five SXPNTs on the active switching module.
[0353]
b) Fabric Active Error: This error occurs when the "Fabric" Active "signal becomes active or inactive on both sides simultaneously.
[0354]
c) Detected link error, lane synchronization error, or format error in data received from SBIA.
[0355]
If an error is detected at the switching module or deemed to be related to the switching module, module 676 disables the current switching module and allows the spare switching module to keep the system processes active. Has a function.
[0356]
In one aspect, the RFT, upon detecting an error in the data received from SXPNT, can generate an interrupt signal that interrupts flow control being performed within module 676. Module 676 then reads the status registers in the SXPNT and RFT to determine what kind of error has occurred and what routine should be instantiated to correct the error.
[0357]
The errors that can generate an interrupt signal can be predetermined by programming the interrupt mask register in the RFT. These errors include: a) Synchronous FIFO overflow from core to SERDES, b) Synchronous FIFO overflow from SERDES to core, c) Link inoperability, e) Code error and / or format error, and f) XPNT Errors may be included, but are not limited to these. Other errors can be monitored and predetermined, as will be appreciated by those skilled in the art based at least on the disclosure provided herein.
[0358]
Module 676 collects interrupt signals from all slave modules and, in one aspect, also collects the other two-bit “fabric present” signal and initiates module 676's failover decision procedure. A "fabric present" signal may indicate that the corresponding switching module is in place. For example, if a user removes a switching module, the corresponding "fabric present" signal is deasserted.
[0359]
Module 676 uses a 2-bit "fabric active" signal to inform all slave modules which switch module is sending traffic. In one aspect, module 676 first resets the spare switch module and inverts the 2-bit signal to initiate a failover procedure.
[0360]
In a redundant switching mode, the network switch has one active / active switching blade and one idle / spare switching blade. According to these aspects, the RFT can send packets to the active blade and send idle characters to the idle blade. When the module 676 detects that the switchover blade has failed or has been removed, the RFT is notified of the failover condition by the system using a 2-bit "fabric active" signal. When a failover occurs, the new switching blade is assumed to be in the initial state after reset. Module 676 checks the status of the new switching blade before issuing the failover command.
[0361]
The RFT always sends a lane synchronization sequence to the standby switching blade to maintain a normal link. Therefore, when a failover occurs, no time is required to activate the spare switching blade.
[0362]
When a failover occurs, a failover procedure can be performed to ensure a safe transition to another switching blade. The following are two example routines that elaborate on certain aspects of the routines described herein.
[0363]
In one aspect, in transmission from the SBIA to the RFT, the RFT detects failover by monitoring a "fabric active" signal.
[0364]
1) Send an RFT error signal to SBIA. SBIA stops transmitting data at cell boundaries and repeats the lane synchronization sequence until the RFT error signal is deasserted. After being deasserted, a stripe synchronization sequence is sent for all slots.
[0365]
2) Flush the uplink RAM.
[0366]
3) Wait for the buffer to be cleared, thus clearing the error.
[0367]
4) Wait for stripe sync sequence and SOP to start accepting data.
[0368]
In one aspect, in the transmission from the SXPNT to the RFT, the RFT detects a failover by monitoring a "fabric active" signal.
[0369]
1) Send AOP to SBIA for all slots and flush downlink RAM. When the SBIA receives the AOP, it discards the received data before stripe synchronization.
[0370]
2) Wait for the buffer to be cleared, thus clearing the error.
[0371]
3) Wait for stripe sync sequence and SOP to start accepting data.
[0372]
According to a feature of the present invention, hitless switching of each blade of the system is possible. The term "hitless" means that there is no packet loss due to fabric changes. Under normal circumstances, a user may nevertheless want to change the fabric to increase performance or to make it more stable. In this case, the user wants to avoid unnecessary dropping of the packet. Further, another reason to use the upgrade procedure is to test the fabric. Switching can be performed using at least two procedures: debug and create.
[0373]
In one aspect, the first procedure allows module 676 to control the switching event by programming registers.
[0374]
1) First, the module 676 sets the “Fabric Enable Mode” and “Hitless Enable Mode” bits in the configuration register to “1”. This allows module 676 to enable the new fabric and hitless mode by programming the registers.
[0375]
2) Module 676 sets the "hitless enable" bit in the "configuration" register. This places the RFT in a mode that performs lossless switching.
[0376]
3) Module 676 then disables the BIA receiver, for example, by setting the corresponding bit in the RFT register. This suppresses SBIA and prevents the SBIA from sending more cells to the RFT.
[0377]
4) Some time (sufficient time to send out all the packets in the SXPNT and RFT buffers; module 676 can determine this duration as already described herein). After expiration, module 676 selects a new fabric by setting the "fabric active" bit in the RFT register.
[0378]
5) Module 676 then clears each bit so that the SBIA can continue to transmit new cells to the RFT (set to be enabled). RFT transfers cells to a new fabric without discarding data.
[0379]
6) Module 676 clears the "hitless enable" bit and places the RFT in failover mode.
[0380]
In another embodiment, the following routine is used as the second procedure. In one aspect, the switching timer that sends out the packet in the RFT / SXPNT buffer is located in the RFT, and SBIA traffic deceleration is performed automatically as described above. In this aspect, module 676 does not need to intervene.
[0381]
1) First, in one hardware embodiment of the present invention, the command input pin can be driven high to enable hitless switching. It should also be noted that in one software aspect, the "hitless enable mode" bit and / or the "switch delay enable" bit may be set to enable hitless switching.
[0382]
2) The module 676 can determine the value of the "switch delay counter" register before deceleration. This is used to program the switch timer when the "fabric active" signal is toggled.
[0383]
3) The "fabric active" input pin is toggled on all RFTs, each RFT slows down SBIA traffic and keeps sending packets to the old switch fabric until the switch timer expires.
[0384]
4) When the timer expires, both RFT and SXPNT should have sent all packets in the internal buffer. The RFT activates the new fabric and starts sending and receiving packets to and from the new switching fabric.
[0385]
5) In the above embodiment, the command input pin is driven low and hitless switching is disabled.
[0386]
Note that in both cases of failover and switching, module 676 is suggested to reset the new fabric first before replacement. Since SXPNT generates AOP for all slots after reset (because the link becomes inoperable), module 676 is given sufficient time before switching the switch fabric.
[0387]
U. Reset and recovery procedures
Follow the reset procedure below when synchronizing SERDES. When a reset is applied to the core, an external reset is asserted for SERDES. The reset pulse duration for SERDES may be less than 10 cycles. After the reset pulse, the SERDES transmitter and receiver synchronize with each other according to a prescribed procedure. SERDES assumes that the core synchronizes after being released from reset. For this reason, the reset pulse for the core must be much larger than the reset pulse for the SERDES core.
[0388]
The core relies on software interaction to synchronize the core. The BIA 302, 600, IBT 304, and XPNT 202 continuously transmit the lane synchronization sequence after being released from the reset. The receiver sets a software visible bit indicating that the lane is synchronized. If the software determines that each lane is synchronized, it attempts to synchronize each stripe. This is done by software that enables continuous transmission of the stripe synchronization sequence. Again, the receiving side of the BIA 302 sets a bit indicating that it is synchronized with a particular source slot. When the software determines this, it enables transmission to BIA 302, XPNT 202, and IBT 304.
[0389]
Management software residing on the management blade is responsible for system maintenance work. According to aspects of the invention, module 676 provides instantiation and access for management software. In another aspect, the management blade includes a dedicated reset signal for each slave module and switching module.
[0390]
In one aspect, the following reset procedure can be performed upon a system reboot.
[0391]
1) When a reset is applied to the core, an external reset is asserted for SERDES. The reset pulse duration for SERDES must be longer than 32 cycles (for a 156 MHz clock).
[0392]
2) After the reset pulse, the SERDES transmitter and receiver synchronize with each other according to a prescribed procedure. SERDES can be assumed to synchronize after the core is released from reset. . For this reason, the reset pulse for the core must be much larger than the reset pulse for the SERDES core.
[0393]
3) The core relies on interaction with module 676 to synchronize the core. The BIA, IBT, and XPNT continuously transmit a lane synchronization sequence after being released from reset.
[0394]
4) SERDES makes lane synchronization status visible to module 676.
[0395]
5) If the module 676 determines that each lane is synchronized, it attempts to synchronize each stripe. This is done by software that enables continuous transmission of the stripe synchronization sequence.
[0396]
6) Again, the BIA receiver sets a bit indicating that it is synchronized with the particular source slot.
[0397]
7) Upon determining this, module 676 enables transmission for BIA, XPNT, and IBT.
[0398]
Similar to the SBIA / SXPNT reset procedure, the RFT allows module 676 to reset each of its three 10Gbps SERDES individually. When SERDES is reset, the link becomes inoperable and data received from SERDES is destroyed. The error recovery process may be the same as the link error handling described above.
[0399]
The following procedure is applied to reduce packet loss due to reset.
[0400]
a) Stop transmitting data to the transmitting SERDES at the cell boundary.
[0401]
b) Send lane synchronization sequence during SERDES reset.
[0402]
c) Start data transmission (SERDES is released from reset state).
[0403]
Although the RFT has three SERDES, in one aspect only two SERDES transfer packets and one SERDES is in standby mode. If the user installs only one switching fabric in the body, there is no corresponding SERDES transceiver for redundant SERDES. Therefore, the link for the redundant SERDES is always disabled. If the user does not want to install the switching fabric in the body, the redundant SERDES can be powered down to save energy and cycles and reduce processing overhead. To this end, the module 676 can access a “power control” register among the registers of the RFT.
[0404]
IV. Control logic
The functions described above with respect to the operation of switch 100 can be implemented with control logic. Such control logic may be implemented in software, firmware, hardware, or any combination thereof.
[0405]
V. Conclusion
While certain aspects of the invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Those skilled in the art will appreciate that various changes may be made in the form and details of these embodiments without departing from the spirit and scope of the invention as defined in the appended claims. Therefore, the scope of the present invention should not be limited by the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
[Brief description of the drawings]
[0406]
FIG. 1 is a diagram of a high performance network switch according to aspects of the present invention.
FIG. 2 is a diagram of a high performance network switch showing a switching fabric having cross point switches coupled to blades according to aspects of the present invention.
3A is a diagram of a blade used in the high performance network switch of FIG. 1 in accordance with an aspect of the present invention.
FIG. 3B is a diagram showing a configuration of a blade according to another aspect of the present invention.
FIG. 4 is an architecture diagram of a cross-point switch with port slices according to aspects of the invention.
FIG. 5 is a diagram of the architecture of a port slice according to an aspect of the present invention.
FIG. 6 is a diagram of a backplane interface adapter according to aspects of the invention.
FIG. 7 illustrates a traffic processing path for local serial traffic received at a backplane interface adapter according to aspects of the present invention.
FIG. 8 is an illustration of an example switching fabric coupled to a backplane interface adapter, in accordance with aspects of the present invention.
FIG. 9 illustrates a traffic processing path for backplane serial traffic received at a backplane interface adapter, in accordance with an aspect of the present invention.
FIG. 10 is a flowchart of operational steps performed along a traffic processing path for local serial traffic received at a backplane interface adapter, in accordance with aspects of the present invention.
FIG. 11 is a flowchart of operational steps performed along a traffic processing path for backplane serial traffic received at a backplane interface adapter, in accordance with aspects of the present invention.
FIG. 12 is a flowchart of a routine for generating a wide striped cell according to an aspect of the present invention.
FIG. 13 is a diagram illustrating narrow cell and state information used in narrow cells according to aspects of the present invention.
FIG. 14 is a flowchart of a routine for encoding a wide striped cell according to an aspect of the present invention.
FIG. 15A illustrates the steps of encoding a wide striped cell according to aspects of the present invention.
FIG. 15B illustrates state information used in a wide striped cell according to aspects of the invention.
FIG. 15C illustrates end-of-packet encoding information used in a wide striped cell, in accordance with an aspect of the present invention.
FIG. 15D is a diagram illustrating an example of cell boundary alignment conditions when transmitting a wide striped cell in a plurality of stripes according to an aspect of the present invention.
FIG. 16 is a diagram illustrating an example of packet boundary alignment conditions when transmitting a wide striped cell in a plurality of stripes according to an aspect of the present invention.
FIG. 17 shows a block diagram of a bus translator according to one aspect of the present invention.
FIG. 18 shows a block diagram of a receiving component according to one aspect of the present invention.
FIG. 19 shows a block diagram of a transmission component according to one aspect of the present invention.
FIG. 20 shows a detailed block diagram of a bus translator according to one aspect of the present invention.
FIG. 21A shows a detailed block diagram of a bus translator according to another aspect of the present invention.
FIG. 21B shows a functional block diagram of a data path having a receiving component of a bus translator, according to one aspect of the present invention.
FIG. 21C shows a functional block diagram of a data path having a transmitting component of a bus translator, according to one aspect of the present invention.
FIG. 21D shows a functional block diagram of a data path having a native mode receiving component of a bus translator, according to one aspect of the present invention.
FIG. 21E shows a block diagram of a cell format according to one aspect of the present invention.
FIG. 22 shows a flowchart of an encoding process for a bus translator according to one aspect of the present invention.
23A-23B illustrate detailed flowcharts of a bus translator encoding process according to one aspect of the present invention.
FIG. 24 shows a flowchart of a decoding process for a bus translator according to one aspect of the present invention.
25A-25B illustrate a detailed flow chart of a bus translator decoding process according to one aspect of the present invention.
FIG. 26 illustrates a flowchart of a bus translator management process according to one aspect of the present invention.
27A-27E illustrate a routine for processing data in a port slice based on wide cell coding and flow control conditions, according to one aspect of the present invention.
FIG. 28A shows a block diagram of a management module according to one aspect of the present invention.
FIG. 28B shows a block diagram of a cross-point architecture according to one aspect of the present invention.
FIG. 29 illustrates a routine for keeping striped cell traffic synchronized in accordance with one aspect of the present invention.
FIG. 30 illustrates a routine for detecting asynchronous traffic flow through a cross-point switch having a backplane switching fabric according to one aspect of the present invention.
FIG. 31 illustrates an example of how obvious an error condition on an incoming link is at the level of data present in the receiving blade synchronization queue sorted by stripe and source, according to an aspect of the invention.
32A-32B show block diagrams of example architectures according to aspects of the present invention.
FIG. 33A shows a block diagram of a blade module enabled by a redundant fabric transceiver, according to one aspect of the present invention.
FIG. 33B shows a block diagram of a redundant fabric transceiver according to one aspect of the present invention.
FIG. 34A shows a table showing cell characters across five stripes according to one embodiment of the present invention.
FIG. 34B shows a routine for a K2 (Special Character) synchronization sequence according to one aspect of the present invention.
FIG. 35 illustrates a block diagram of a synchronous flow control implementation of a redundant fabric transceiver according to one aspect of the present invention.
FIG. 36 shows a timing diagram of time domain multiplexing of a synchronous flow control implementation according to one aspect of the present invention.
FIG. 37 shows a block diagram of an asynchronous flow control implementation of a redundant fabric transceiver according to one aspect of the present invention.

Claims (137)

Switching fabric,
A plurality of blades coupled to the switching fabric via a serial pipe;
A digital switch wherein each blade outputs a serial data stream to the switching fabric in a plurality of stripes along with in-band control information. The digital switch of claim 1, wherein the switching fabric includes a plurality of cross points corresponding to a plurality of stripes. The digital switch of claim 2, wherein each cross point includes a plurality of port slices coupled to a plurality of blades. The plurality of stripes includes five stripes, and the serial data stream having in-band control information includes five serial data streams of a wide striped cell for transmitting data packets, and the wide striped cell. 3. The digital switch according to claim 2, wherein the digital switch comprises in-band control information. The digital switch of claim 4, wherein the plurality of cross points includes five cross points, and each blade has five serial links coupled to each of the five cross points. Each blade generates a wide striped cell having blocks across a plurality of stripes, each block comprising a plurality of sub-blocks corresponding to the respective plurality of stripes, and a serial data stream having in-band control information is 2. The digital switch according to claim 1, comprising the sub-block corresponding to each of the plurality of stripes. 7. The digital switch of claim 6, wherein the wide striped cell has a size of 160 bytes or less and transfers a payload of data of 148 bytes or less. The digital switch of claim 1, wherein each blade includes a backplane interface adapter and at least one packet processor. The digital switch of claim 1, wherein each blade includes a backplane interface adapter, an integrated bus translator, and at least one packet processor. The digital switch of claim 1, wherein the serial data stream output by each blade represents a collection of input serial data streams provided to each blade via a physical port. Switching fabric,
A plurality of blades coupled to the switching fabric via a serial pipe;
Each blade outputs a serial data stream representing a set of input serial data streams supplied to each blade via a port in a plurality of stripes together with in-band control information;
A digital switch, wherein the switching fabric switches the collective serial data output as a plurality of stripes. At least one receiver for receiving a narrow input cell for transferring data packets;
At least one wide cell generator for generating wide striped cells including data packets from narrow input cells;
A backplane interface adapter, comprising: at least one transmitter for transmitting the generated wide striped cells to the switching fabric in a plurality of stripes. A backplane interface adapter, wherein each narrow input cell includes a destination slot identifier identifying a slot in the switching fabric over which the respective narrow input cell is transmitted,
The traffic sorter further coupled between the at least one receiver and the at least one wide cell generator, wherein the traffic sorter sorts received narrow input cells based on a destination slot identifier. The backplane interface adapter according to item 12. Global / traffic sorting a received narrow input cell having a destination slot identifier identifying a local destination slot from a received narrow input cell having a destination slot identifier identifying a global destination slot across the switching fabric. 14. The backplane interface adapter of claim 13, including a sorter. The traffic sorter further includes a backplane sorter coupled to the global / traffic sorter, wherein the backplane sorter has a destination slot identifier that identifies a global destination slot as a group based on the destination slot identifier. 15. The backplane interface adapter of claim 14, wherein the backplane interface adapter sorts narrow input cells. The apparatus further includes a plurality of stripe transmit queues coupled between the at least one wide cell generator and the at least one transmitter, the at least one wide cell generator storing the generated wide striped cells. 13. The backplane interface adapter according to claim 12, wherein the adapter is stored in the plurality of stripe transmission queues. 17. The backplane interface adapter of claim 16, further comprising a switched fabric transmit arbitrator that arbitrates the order in which data stored in the striped transmit queue is transmitted by at least one transmitter to the switched fabric. The backplane interface adapter of claim 17, wherein each stripe transmit queue stores a respective set of wide striped cells corresponding to a respective source packet processor and destination slot identifier. Each wide striped cell has one or more blocks spanning multiple stripes, and during a cycle, a switched fabric transmit arbitrator selects a stripe transmit queue and transmits at least one next available block. 20. The backplane interface adapter of claim 18, wherein said adapter pushes to a machine. Each wide striped cell has one or more blocks spanning multiple stripes, and during a cycle, a switched fabric transmit arbitrator selects a stripe transmit queue and transmits at least one next available block. 20. The backplane interface adapter of claim 18, wherein said adapter pushes to a machine. At least one receiver includes four deserializer receivers that receive narrow input cells transmitting data packets in four serial data streams from four corresponding input serial pipes;
Multiple stripes include five stripes,
At least one transmitter includes five serializer transmitters,
13. The input serializer transmitter transmits a respective stripe of data of the generated block of wide striped cells to a respective cross point switch in the switching fabric over a backplane serial pipe. Backplane interface adapter as described. 22. The backplane interface adapter of claim 21, wherein each serial pipe comprises a 10 Gbit / s serial pipe, and wherein the backplane serial pipe comprises a 50 Gbit / s serial pipe. Each wide cell generator parses each narrow input cell, checks for control information indicating the beginning of the packet, and distributes data for all narrow input cells of the packet across one or more new wide striped cells 13. The backplane interface adapter of claim 12, wherein the backplane interface adapter encodes one or more new wide-striped cells until writing the one or more new wide-striped cells to a plurality of transmit queues. 13. The backplane interface adapter of claim 12, wherein each wide cell generator encodes one or more new wide striped cells. 13. The backplane interface adapter of claim 12, wherein each wide cell generator encodes an initial block of starting wide striped cells with initial cell coding information. The initial cell coding information includes control information and state information, and the initial block of the starting wide striped cell includes five sub-blocks corresponding to five stripes, each sub-block having the same control information and the same 26. The backplane interface adapter of claim 25, comprising status information of: 26. The backplane interface adapter of claim 25, wherein each wide cell generator further distributes an initial byte of packet data over available space within an initial block of the first wide striped cell. Each wide cell generator spreads the remaining bytes of packet data over one or more blocks in the first wide striped cell until the end-of-packet condition is reached or the maximum cell size is reached. 28. The backplane interface adapter of claim 27, wherein the adapter is distributed. Each wide cell generator has a set of end-of-packet conditions, including whether the end of the packet occurs at the end of the initial block, in a subsequent block, at a block boundary, or at a cell boundary. 29. The backplane interface adapter of claim 28, further encoding the ending wide striped cell with different end-of-packet information depending on. Each wide cell generator encodes at the beginning of a packet an initial 20 byte block of a starting wide striped cell having 20 bytes of data distributed over 5 stripes as follows:

Here, K0 is 1 byte representing a special control character indicating the beginning of a cell, the status is 1 byte of status information, data 0 to data 7 represent 8 bytes of payload data, and reserved is 1 reserved byte. 13. The backplane interface adapter of claim 12, wherein: 15. Each wide cell generator further encodes an ending wide striped cell with different end-of-packet information depending on the degree to which the wide striped cell is filled with data as described in FIG.15C. Backplane interface adapter as described. 13. The backplane interface adapter of claim 12, wherein each wide cell generator generates a wide striped cell that transfers 148 bytes or less of payload data. At least one receiver for receiving wide striped cells for transferring data packets from the switching fabric in a plurality of stripes;
A translator for converting the received wide striped cells into narrow input cells for forwarding data packets;
13. The backplane interface adapter of claim 12, further comprising: at least one transmitter for transmitting the narrow input cell to a corresponding source packet processor. Wide striped cell transfers data packets across multiple stripes and receives wide striped cell sub-blocks containing source packet processor identifier and source slot identifier information in multiple stripes from switching fabric At least one wide striped cell receiver,
A stripe interface coupled to the at least one wide striped cell receiver;
A plurality of stripe receive synchronization queues coupled to the stripe interface, the stripe interface sorting the received sub-blocks in each stripe based on source slot identifier information; 13. The backplane interface adapter of claim 12, wherein the received sub-blocks are stored in the stripe receive synchronization queue. An arbitrator,
A wide striped cell coupled to the arbitrator for arbitrating the order in which data stored in the stripe receive synchronization queue is transmitted to the stripe-based wide cell assembler and based on the received data sub-block. And a stripe-based wide cell assembler that assembles
A translator coupled to the stripe-based wide cell assembler and for converting arbitrated received wide striped cells to narrow input cells for forwarding data packets;
A plurality of destination queues for storing the narrow cells transmitted by the local traffic sorter and the narrow cells transformed by the translator;
A local destination transmission arbitrator for arbitrating the order in which the data stored in the plurality of destination queues is transmitted to at least one transmitter;
35. The backplane interface adapter of claim 34, further comprising: at least one transmitter for transmitting the narrow input cell to a corresponding source packet processor. 13. The backplane interface adapter of claim 12, wherein at least one receiver includes at least one deserializer receiver and at least one transmitter includes at least one serializer transmitter. Wide striped cell transfers data packets across multiple stripes and receives wide striped cell sub-blocks containing source packet processor identifier and source slot identifier information in multiple stripes from switching fabric At least one receiver to
A stripe interface coupled to the at least one receiver;
A stripe interface for sorting the received sub-blocks in each stripe based on source packet processor identifier and source slot identifier information and storing the sorted received sub-blocks in the stripe receive synchronization queue Backplane interface adapter that contains multiple striped receive synchronization queues coupled to the An arbitrator,
A stripe-based wide cell assembler coupled to the arbitrator;
The arbitrator arbitrates the order in which data stored in the stripe receive synchronization queue is sent to the stripe-based wide cell assembler, and the stripe-based wide cell assembler transmits the received data to the stripe-based wide cell assembler. 38. The backplane interface adapter of claim 37, wherein the backplane interface adapter assembles wide striped cells based on sub-blocks. A translator coupled to the stripe-based wide cell assembler for converting the arbitrated received wide striped cells to narrow input cells for forwarding data packets;
39. The backplane interface adapter of claim 38, further comprising: at least one transmitter for transmitting the narrow input cell to a corresponding source packet processor. A plurality of destination queues for storing narrow cells transmitted by the local traffic sorter and narrow cells translated by the translator;
40. The backplane interface adapter of claim 39, further comprising: a local destination transmit arbitrator for arbitrating the order in which data stored in the plurality of destination queues is transmitted to at least one transmitter. 38. The backplane interface adapter of claim 37, wherein at least one receiver includes at least one deserializer receiver and at least one transmitter includes at least one serializer transmitter. At least one deserializer receiver for receiving a narrow input cell for transmitting data packets;
At least one wide cell generator for generating a wide striped cell including a data packet of a narrow input cell;
At least one serializer transmitter for transmitting the generated wide striped cells to the switching fabric in a plurality of stripes,
At least one deserializer receiver for receiving from a fabric switching wide striped cells for transferring data packets in a plurality of stripes;
A translator for converting the received wide striped cells into narrow cells for forwarding data packets;
A backplane interface adapter including at least one narrow cell serializer transmitter for transmitting a narrow input cell to a corresponding source packet processor. A method of interfacing a serial pipe for transferring data packets with narrow input cells and a serial pipe for transferring data packets with wide striped cells,
Receiving a narrow input cell;
Generating a wide striped cell;
Transmitting a block of wide striped cells across a plurality of stripes. 44. The method of claim 43, further comprising, prior to the generating step, sorting received narrow input cells based on a destination slot identifier. 44. The method of claim 43, further comprising storing the generated wide striped cell in a corresponding stripe and queue based on the destination slot identifier and the source packet processor. 46. The method of claim 45, further comprising arbitrating the order in which the stored wide striped cells are selected for transmission in the transmitting step. Multiple stripes include five stripes,
A receiving stage receives narrow input cells transferring data packets in four serial data streams from four corresponding input serial pipes;
44. The method of claim 43, wherein the transmitting step transmits the generated block of wide striped cells in five stripes over a backplane serial pipe. The generation stage is
Analyzing each narrow input cell;
Checking for control information indicating the beginning of the packet;
Encoding one or more new wide-striped cells until the data of all narrow input cells transmitting the packet is distributed among the one or more new wide-striped cells;
Writing one or more new wide-striped cells to a plurality of transmit queues. 49. The method of claim 48, wherein the encoding step comprises encoding an initial block of starting wide striped cells with initial cell encoding information. The initial cell coding information includes control information and state information, and the initial block of the starting wide striped cell includes five sub-blocks corresponding to five stripes, each sub-block having the same control information and the same state. 50. The method of claim 49, comprising information. An encoding step of distributing initial bytes of packet data over available space within an initial block of the first wide striped cell; and utilizing an end of the initial block of the first wide striped cell. Adding reservation information to possible bytes. The encoding stage spreads the remaining bytes of packet data across one or more blocks in the first wide striped cell until the end-of-packet condition is reached or the maximum cell size is reached 52. The method of claim 51, comprising a step. The encoding phase depends on the set of packet ending conditions, including whether the end of the packet occurs at the end of the initial block, in a subsequent block, at a block boundary, or at a cell boundary. 53. The method of claim 52, further comprising encoding an ending wide striped cell with end-of-packet information. The encoding stage encodes at the beginning of the packet an initial 20 byte block of a starting wide striped cell having 20 bytes of data distributed over 5 stripes as follows:

Here, K0 is 1 byte representing a special control character indicating the beginning of a cell, the status is 1 byte of status information, data 0 to data 7 represent 8 bytes of payload data, and reserved is 1 reserved byte. 54. The method of claim 53, wherein 54. The method of claim 53, wherein the encoding step further encodes the ending wide striped cell at the beginning of the packet with different end-of-packet information depending on the degree to which the wide striped cell is filled with data. . Receiving from a switching fabric a plurality of stripes of wide striped cells for transferring data packets;
Converting the received wide striped cells into narrow input cells for forwarding data packets;
Transmitting the narrow input cell to a corresponding source packet processor. Transferring a data packet across a plurality of stripes and receiving a sub-block of wide striped cells including destination slot identifier information from the switching fabric in the plurality of stripes;
Sorting the received sub-blocks in each stripe based on destination slot identifier information;
Storing the sorted received sub-blocks in a stripe receive synchronization queue. Arbitrating the order in which the data stored in the stripe receive synchronization queue is assembled;
Assembling the wide striped cells in the order of the arbitration phase based on the received data sub-blocks;
Converting the arbitrated received wide striped cell to a narrow input cell that forwards the data packet. Storing narrow cells in a plurality of destination queues;
Further arbitrating the order in which the data stored in the plurality of destination queues is transmitted;
Transmitting the narrow input cells to the corresponding source packet processor in the order of the further arbitration steps. 54. The method of claim 53, wherein each receiving step includes deserializing the data and each transmitting step includes serializing the data. A method of encoding a wide striped cell that transfers data packets across a stripe, comprising:
(A) encoding an initial block of the first wide striped cell with initial cell encoding information;
(B) distributing the initial bytes of packet data within the available space within the initial block of the first wide striped cell. The initial cell coding information includes control information and status information, and the initial block of the first wide striped cell includes five sub-blocks corresponding to five stripes, each sub-block having the same control information and the same 62. The method of claim 61, comprising the status information of: 63. The method of claim 61, further comprising adding reservation information to available bytes at the end of an initial block of the first wide striped cell. Further distributing the remaining bytes of the packet data across one or more blocks in the first wide striped cell until an end-of-packet condition is reached or a maximum cell size is reached; 62. The method of claim 61. (C) Different packets depending on the set of packet ending conditions, including whether the end of the packet occurs at the end of the initial block, within a subsequent block, at a block boundary, or at a cell boundary. 63. The method of claim 61, further comprising encoding a first wide striped cell or other wide striped cell with end information of the first wide striped cell. An initial block encoding step (a) encodes at the beginning of the packet an initial 20 byte block of a starting wide striped cell having 20 bytes of data distributed over 5 stripes as follows:

Here, K0 is 1 byte representing a special control character indicating the beginning of a cell, the status is 1 byte of status information, data 0 to data 7 represent 8 bytes of payload data, and reserved is 1 reserved byte. 62. The method of claim 61, wherein The encoding step (c) encodes the first wide striped cell or another wide striped cell with different end-of-packet information depending on the degree to which the wide striped cell is filled with data. 62. The method of claim 61. A system for encoding a wide striped cell that transfers data packets across a stripe, comprising:
(A) means for encoding an initial block of the first wide striped cell with initial cell encoding information;
(B) means for distributing the initial bytes of packet data within the available space within the initial block of the first wide striped cell. The initial cell coding information includes control information and status information, and the initial block of the first wide striped cell includes five sub-blocks corresponding to five stripes, each sub-block having the same control information and the same 70. The system of claim 68, comprising status information of 69. The system of claim 68, further comprising adding reservation information to available bytes at the end of an initial block of the first wide striped cell. Further comprising means for distributing the remaining bytes of the packet data across one or more blocks in the first wide striped cell until an end-of-packet condition is reached or a maximum cell size is reached; 70. The system of claim 68. (C) Different packets depending on the set of packet ending conditions, including whether the end of the packet occurs at the end of the initial block, within a subsequent block, at a block boundary, or at a cell boundary. 69. The system of claim 68, further comprising: means for encoding the first wide striped cell or other wide striped cell with end-of-information. Initial block encoding means (a) encodes, at the beginning of the packet, an initial 20 byte block of a starting wide striped cell having 20 bytes of data distributed over 5 stripes as follows:

Here, K0 is 1 byte representing a special control character indicating the beginning of a cell, the status is 1 byte of status information, data 0 to data 7 represent 8 bytes of payload data, and reserved is 1 reserved byte. 70. The system of claim 68, wherein Encoding means (c) encodes the first wide-striped cell or another wide-striped cell with different end-of-packet information depending on the degree of filling of the wide-striped cell with data. 70. The system of claim 68. A system for translating packets,
A translator that analyzes packets to obtain narrow cells;
A first group of one or more transceivers;
A second group of one or more transceivers, wherein the translator is coupled to the first group of one or more transceivers and a second group of one or more transceivers. 77. The system of claim 75, wherein the translator further analyzes the narrow cells to obtain packets. One or more memory pools for storing one or more packets and narrow cells;
77. The system of claim 75, further comprising one or more reference clocks that synchronize one or more operations of the translator. 77. The system of claim 75, further comprising a management module that allows a user to control one or more operations of the translator. The translator is
One or more packet decoders that parse one or more packets to obtain an information field;
76. The system of claim 75, comprising one or more cell encoders that build one or more narrow cells from the information field. The translator is
One or more cell decoders that parse one or more narrow cells to obtain an information field;
76. The system of claim 75, comprising one or more packet encoders that build one or more packets from the information field. 77. The system of claim 75, wherein the translator operates with packets in a parallel configuration and narrow cells in a serial configuration. A header containing special characters and control information;
Narrow cell format, including a payload containing data. 83. The narrow cell format of claim 82, wherein the control information includes a routing address for the payload. 83. The narrow cell format of claim 82, wherein the header is 4 bytes and the payload is 32 bytes. 83. The cell format of claim 82, wherein the header reserves one or more bytes for additional information. In the bus translator,
Special characters to mark the beginning of the cell,
Control information including slot information and state information in the cell;
Cell format, including payload containing data. A method of converting a packet into cells,
Determining a port type that includes the configuration of the packet processing component;
Selecting a cell format dependent on the port type;
Receiving one or more packets from the port;
Analyzing one or more packets to obtain information;
Formatting the information into one or more cells;
Transferring the one or more cells to an interface. 88. The method of claim 87, further comprising storing the information prior to the formatting step. 91. The method of claim 87, wherein the receiving step comprises packets in a parallel configuration. 88. The method of claim 87, wherein the transferring step comprises cells in a serial configuration. A method of converting cells into packets,
Receiving one or more cells;
Analyzing the one or more cells to obtain information;
Storing the information in one or more packets;
Forwarding the one or more packets. Queuing one or more cells;
92. The method of claim 91, comprising synchronizing the one or more cells, wherein the queue storing and the synchronizing are performed prior to the analyzing. 92. The method of claim 91, wherein the receiving step comprises cells in a serial configuration. 92. The method of claim 91, wherein the transferring comprises packets in a parallel configuration. A switching fabric comprising a plurality of cross points for processing a plurality of stripes of serial data,
A switching fabric where each cross point contains multiple port slices. 97. The switching fabric of claim 95, wherein the plurality of cross points comprises five cross points. Each cross point is
Multiple ports,
97. The switching fabric of claim 95, comprising: a plurality of port slices each coupled to the port. Each port slice is
A plurality of FIFOs coupled to other ones of the port slices;
97. The switching fabric of claim 95, further comprising: a FIFO read arbitrator coupled to each FIFO and arbitrating read requests transmitted by the FIFO. Each port slice is
A multiplexer coupled to the FIFO and the FIFO read arbitrator;
99. The switching fabric of claim 98, further comprising: a dispatcher coupled to an output of the multiplexer. Each port slice is
97. The switching fabric of claim 95, comprising an accumulator that writes received data to an appropriate FIFO in a different port slice. 97. The switching fabric of claim 95, wherein each cross point includes eight ports and eight port slices. A cross point having a stripe of serial data,
Multiple ports,
A cross point comprising a plurality of port slices each coupled to the port. Each port slice is
A plurality of FIFOs coupled to other ones of the port slices;
103. The cross point of claim 102, further comprising: a FIFO read arbitrator coupled to each FIFO and arbitrating read requests transmitted by the FIFO. Each port slice is
A multiplexer coupled to the FIFO and the FIFO read arbitrator;
104. The cross point of claim 103, further comprising: a dispatcher coupled to an output of the multiplexer. Each port slice is
114. The cross point of claim 103, comprising an accumulator that writes received data to an appropriate FIFO in a different port slice. 103. The cross point of claim 102, wherein each cross point includes eight ports and eight port slices. A method of processing stripes of data at cross points,
In a port slice,
Storing data received from other port slices in a plurality of FIFOs;
Arbitrating the reading of the stored data. 108. The method of claim 107, further comprising writing data received from a port to a port slice to an appropriate FIFO in a different port slice. A method of processing data in a port slice based on a wide cell encoding and an external flow control command, the method comprising:
Managing 64-bit entries in the receive synchronization FIFO;
Receiving two 32-bit data chunks from a receive synchronization FIFO;
Detecting K0 in the first byte of the two received 32-bit data chunks;
Extracting the destination slot from the status field in the cell header if K0 is detected. Determining whether the cell header is bottom-ordered or top-ordered;
Writing 64-bit data to the data FIFO corresponding to the destination slot when the cell header is low-order or high-order;
Writing two 64-bit data to two data FIFOs corresponding to the two destination slots when the cell header is low-order or high-order;
Filling the second 32-bit data chunk with idle characters if the cell does not end on a 64-bit boundary and subsequent cells are destined for a different slot. . 1 12. The method of claim 1 10, further comprising performing an early termination on the cell to insert K0 and ABORT status information into the data if an error condition is detected. 112. The method of claim 110, further comprising: stopping a request to the FIFO read arbitrator after the current cell has been completely read from the FIFO RAM if a flow control condition is detected. Providing 64-bit data to the SERDES synchronous FIFO module and transmitter when non-idle data is received from the FIFO read arbitrator;
Inserting a first alignment sequence to be sent to the SERDES synchronous FIFO module and the transmitter when the FIFO read arbitrator indicates that the plurality of FIFO RAMs are empty;
Instructing the FIFO read arbitrator to temporarily stop satisfying the requestor's request until the current pre-scheduled alignment sequence has completely completed. A digital switch is used in a digital switch that includes a plurality of blades coupled to a switching fabric, each blade outputting a serial data stream to the switching fabric in a plurality of stripes with in-band control information. A management module,
A level monitor for monitoring data received by the receiving blade;
A stripe synchronization error detector for detecting a stripe synchronization error based on an amount of data monitored by the level monitor. The management module of claim 114, wherein the data received at the receiving blade is sorted based on stripe / source information, and stored in a set of data structures.
A level monitor monitors the level of data stored in each data structure receiving blade,
A management module, wherein the stripe synchronization error detector detects at least one of an overflow condition and an underflow condition in the amount of data received on each stripe from a particular source. 115. The management module of claim 114, further comprising a flow controller that initiates a recovery routine to resynchronize data across the stripe in response to detecting a stripe synchronization error. 117. The management module of claim 116, wherein the recovery routine includes slowing data flowing through the one or more stripes. 115. The management module of claim 114, further comprising a control character presence tracker that identifies the presence of a K2 character during a recovery routine. 115. The management of claim 114, wherein the stripe synchronization error detector detects the stripe synchronization error in response to one or more of an incoming link error, a cross point failure, and an outgoing link error condition. module. A method for detecting a stripe synchronization error in a network switch, comprising:
(A) sorting the data received at the receiving slot based on the stripe / source information;
(B) storing the sorted data in a set of data structures;
(C) monitoring the level of data stored in each data structure;
(D) detecting at least one of an overflow condition and an underflow condition in the amount of data received on each stripe from a particular source. 121. The method of claim 120, wherein the source information identifies a slot that transmitted data across a switching fabric of a network switch. 121. The method of claim 120, wherein the source information identifies a source packet processor that transmitted data from the slot across the switching fabric of the network switch. A method of keeping striped cell traffic synchronized, comprising:
(A) transmitting a common character in a striped cell in all lanes for a predetermined number of cycles;
(B) evaluating a common control character received at the stripe receive synchronization queue;
(C) detecting, if any, a synchronization condition indicating that the stripe receive synchronization queue has been cleared. A method of managing asynchronous traffic flow via a cross point switch in a switching fabric, comprising:
(A) monitoring the level of the stripe receive synchronization queue;
(B) determining whether an asynchronous condition exists;
(C) initiating a resynchronization routine if the asynchronous condition exists. After the start phase (c),
(D) transmitting a common character in a striped cell in all lanes for a predetermined number of cycles;
(E) evaluating common control characters received in the stripe receive synchronization queue;
125. The method of claim 124, further comprising: (f) detecting a synchronization condition, if any, indicating that the stripe receive synchronization queue has been cleared. Two switching blades, each having a plurality of cross points corresponding to each stripe of the serial data stream;
A redundant switching system comprising at least one blade coupled to each switching blade by a backplane connection.
A redundant switching system, wherein the at least one blade includes a plurality of redundant switching transceivers capable of switching traffic between cross points on the two switching blades. A redundant fabric transceiver coupled to the bus interface adapter,
One or more first ports coupled to at least one or more switching fabric modules and transmitting similar data substantially simultaneously;
A multiplexer that selects transmitted communication data from similar data that may include one version of the communication data;
A downlink transceiver for receiving, conditioning and transmitting the communication data;
One or more second ports for receiving the communication data transmitted from the multiplexer and transferring the communication data to a bus interface adapter. An uplink transceiver for receiving, conditioning, and transmitting the communication data, wherein one or more second ports receive the communication data from the bus interface adapter and one or more second ports. Two ports forward the communication data to the uplink transceiver, the uplink transceiver conditioned and forwards the communication data to the multiplexer, wherein the multiplexer transmits one or more of the first 130. The redundant fabric transceiver of claim 127, wherein the redundant fabric transceiver generates one or more similar data that is forwarded to a port. 129. The redundant fabric transceiver of claim 128, further comprising one or more first queues coupled to the multiplexer for buffering data. 129. The redundant fabric transceiver of claim 128, further comprising one or more second queues coupled to at least one of the downlink transceiver and the uplink transceiver for buffering data. The apparatus further includes a register module including condition information indicating operation of at least one of the downlink transceiver and the uplink transceiver, wherein the condition information includes a configuration setting and a parameter setting regarding reception data and transmission data. 128. A redundant fabric transceiver as described in 128. 129. The redundant fabric transceiver of claim 128, wherein one or more of the first ports is a serializer / deserializer. 129. The redundant fabric transceiver of claim 128, wherein one or more of the second ports is a serializer / deserializer. 129. The redundant fabric transceiver of claim 128, wherein the downlink transceiver comprises a receiver, a random access memory module, and a transmitter. 129. The redundant fabric transceiver of claim 128, wherein the uplink transceiver comprises a receiver, a random access memory module, and a transmitter. 129. The redundant fabric transceiver of claim 128, wherein the one or more first ports can be individually halted in case of an error condition affecting the one or more first ports. 129. The redundant fabric transceiver of claim 128, wherein one or more first ports can be switched without losing data.

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