JP2002184176A - Sdram control circuit and sdram module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module being inexpensive, practical, and large capacity by constituting a memory module (DIMM) using an inexpensive SDRAM put to practical use now. SOLUTION: A control circuit outputting plural new chip selecting signal from an address signal, a clock enable-signal, and a chip selecting signal is formed to a SDRAM module, and the number of SDRAM being controllable is increased. Consequently, four inexpensive 16 Mbit×4 bit.SDRAM can be used instead of expensive 32 Mbit×8 bit.SDRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous dynamic random access memory (Synchr).
onous Dynamic Random Access
The present invention relates to a control circuit and a memory module using the SDRAM.

[0002]

2. Description of the Related Art SDRAMs are used in memory units of computers or communication unit systems such as CPUs and processor modules. SDRAM generally requires a memory capacity suitable for the system, but the access data and communication speed tend to increase year by year.
There is a demand for increased capacity of AM.

FIG. 5 shows a dual in-line memory module (Dual In-Line Memory) having a capacity of 512 Mbytes as an example of an SDRAM module in which a plurality of SDRAMs are combined to increase the capacity.
y Module (hereinafter, DIMM) is shown in a block diagram. In this DIMM, 18 pieces of 32 Mbit ×
In an 8-bit SDRAM (U0 to U17 in the figure, two of which are for check bits), 13 address signals (A0 to A12), a chip select signal (CS0) and a clock enable signal (CKE) are respectively provided.
0 to CKE1) are supplied and controlled one by one.
Further, a clock signal (CLK), a bank address signal (BA0 to BA1), a row address strobe signal (R
AS), a column address strobe signal (CAS), and a write enable signal (WE). As input / output signals, data mask signals (DQM0 to DQM7),
Data signals (DQ00 to DQ63) and check bit signals (CB0 to CB7) are supplied.

[0004]

In order to meet the above-mentioned demand for an increase in the capacity of the SDRAM, it is desirable to develop a SDRAM having a larger capacity and use it in a module form. However, the development of a large-capacity SDRAM has problems such as a huge development cost and a long development period. Furthermore, the resulting system may be expensive and impractical. In addition, it is necessary to develop not only a memory but also an LSI or the like for controlling the memory, and there is a problem that the development period becomes longer and the system becomes more expensive.

An object of the present invention is to provide a memory module (D) using an inexpensive SDRAM that is currently in practical use.
An object of the present invention is to provide an inexpensive and practical large-capacity memory module by configuring an IMM. Specifically, for each SDRAM constituting the DIMM, this SDRAM
It is intended to form a DIMM having the same capacity by using a plurality of SDRAMs having a smaller capacity than the capacity of the DRAM.

[0006]

An SDRAM control circuit according to the present invention is an SDRAM control circuit for controlling an SDRAM module. The first control circuit inputs an address signal and a clock enable signal and outputs a plurality of new clock enable signals. And a second circuit that receives the clock enable signal and the chip select signal output from the first circuit and outputs a plurality of new chip select signals.

[0007] Further, the SDRAM module of the present invention comprises:
A plurality of first SDRAM units, each of which includes a first SDRAM;
The DRAM includes a plurality of SDRAMs having a smaller memory capacity than the SDRAM, and includes an SDRAM control circuit that receives an address signal and outputs a signal for controlling the SDRAM having the smaller memory capacity.

According to the above-mentioned invention, a large-capacity SDRAM module can be constructed using an inexpensive small-capacity SDRAM that is currently available.

[0009]

FIG. 1 is a block diagram showing an example of an SDRAM control circuit and an SDRAM module (specifically, a DIMM) of the present invention. In the DIMM of the present invention shown in FIG. 1, the circuit portion on the right side is 18 pieces of 32 Mbit × 8.
a bit SDRAM (U0 to U17) 1 in which the left circuit portion controls the right SDRAM.
This is a DRAM control circuit. This SDRAM module also
As the input signal for control, a signal similar to the above-described conventional example is used. However, in the present invention, the SDRAMs (U0 to U
17) each have four 16's as shown in FIG.
Mbit × 4bit SDRAM (U0-0 to U0-
3) formed by 2; One 16Mbit ×
The 4-bit SDRAM 2 outputs a chip select signal (C
S) requires one signal and twelve address signals (A0 to A11).

That is, the conventional 32 Mbit × 8 bit
A used in the DIMM using the DRAM 1
The 12 address signal is a signal for designating and controlling the column address number 12, which is 16 Mbit × 4b of the present invention.
This is unnecessary when controlling the it · SDRAM 2. For this reason, in the SDRAM module of the present invention, the conventional DI
The address signal is one signal extra than the MM. Using this extra A12 signal, 4 bits of 16 Mbit × 4 bits
Chip select signal (CSO) for controlling the SDRAMs
0-CSO3) are produced by the SDRAM control circuit.

First, the A12 signal is input to the D-flip-flop circuit (LVC74) together with the clock enable signals (CKE0, CKE1), processed (clear / preset), and processed as a new clock enable signal (CKE).
O0, CKEO1) are output. The clock enable signals (CKEO0, CKEO1) are supplied to the two decoder circuits (LVC1) together with the chip select signal (CS0).
38), are processed (decoded) by the circuit, and new chip select signals (CSO0 to CS0)
O3) are output. The chip select signals (CS0 to CSO3) thus obtained are signals that operate in synchronization with the chip select signal (CS0), the address signal (A12), and the clock enable signal (CKE) input to the module. 16Mbit x 4b
It becomes a chip select signal for it.SDRAM (U0-0 to U0-3) 2, and controls read / write, refresh, and precharge of these SDRAMs. The same applies to the other SDRAMs (U1 to U17) in FIG.
Note that the above-described chip select signals (CSO0 to CSO
The D-flip-flop circuit and the decode circuit that output 3) can be configured with a gate array that is high-speed and has a small output delay.

Therefore, these signals enable 72 1
6 Mbit × 4 bit SDRAM 2 can be controlled, and the capacity is 512 MB which is the same as the module of FIG.
It becomes possible to configure a DIMM of ye.

Next, the operation of the SDRAM module will be described with reference to the timing charts of FIGS. Each signal is controlled in synchronization with the CLK signal.

In FIG. 3A, in the D-flip-flop circuit (LVC 74), when the clock enable signal (CKE) input to the CLR terminal is at a high level,
When the address signal (A12) input to the K terminal goes low, a low-level clock enable signal (CKEO) is output from the output terminal of the circuit. This low level clock enable signal (CKEO) and chip select signal (CS0) are supplied to the decoder circuit (LVC).
138) and the chip select signal (CS0) is at a low level, a low level chip select signal (CS0) synchronized with the CS0 signal is output to the output terminal, and the SDRAM (U0-0) becomes active. Further, the high level chip select signal (CSO2) is continuously output, and the SDRAM (U0-2) enters the standby state.

In FIG. 3B, the clock enable signal (CKE) input to the CLR terminal of the D-flip-flop circuit (LVC74) is at a high level, and the address signal (A12) input to the CLK terminal is at a high level. , A new clock enable signal (CK) output from the circuit until the CKE signal goes low thereafter.
EO) is output at a high level. The high-level clock enable signal (CKEO) and the chip select signal (CS0) are input to the decoder circuit (LVC138), and when the chip select signal (CS0) becomes low level, a new chip select output from the decode circuit is output. The signal (CSO0) continues to be output at a high level,
The RAM (U0-0) enters a standby state, the chip select signal (CSO2) becomes a low level signal synchronized with the CS0 signal, and the SDRAM (U0-2) becomes active.

In FIG. 3C, the input and output signals of the D-flip-flop circuit (LVC 74) are the same as those in FIG. 3A. At this time, the decoding circuit (LVC138)
When the chip select signal (CS0) input to the CSO remains at the high level, the output CSO0 signal and CSO
The SO2 signal remains at high level.

In FIG. 3D, the input signal and the output signal of the D-flip-flop circuit (LVC 74) are the same as in FIG. 3B. At this time, the decoding circuit (LVC138)
When the chip select signal (CS0) input to the CSO remains at the high level, the output CSO0 signal and CSO
The SO2 signal remains at high level.

3 (e) and 3 (f), if the clock enable signal (CKE) input to the D-flip-flop circuit (LVC74) is at a low level, the address signal (A12) is at a low level. Alternatively, even when the signal goes high, the new clock enable signal (CKEO) to be output is low. Similarly, when the chip select signal (CS0) input to the decode circuit (LVC138) remains at the high level, the output CSO0 signal and CSO2 signal remain at the high level. CSO1 and CSO3 output from the other decoding circuit (LVC138) operate in the same manner as in the above-described time chart.

This D-flip-flop circuit (LVC7)
4) and a chip select signal (CSO0 to CS0) generated by a control circuit including a decode circuit (LVC138).
By using CSO3) and combining with control signals normally used in DIMMs, read / write and other control of the SDRAM is performed.

Note that a bank address signal (BA0) can be used as a signal to be input to the D-flip-flop circuit (LVC74) instead of the address signal (A12). FIG. 4 shows the configuration of the control circuit section in this case. Even if BA0 signal is used, new CSO0-C
The SDRAM can be controlled by the SO3 signal, but SDRAM parts without the BA signal can be used.
The range of components that can be used in SDRAM components in M is expanded.

The above 16 Mbit × 4 bit SDRAM
The parts have a CSP (Chip Size Package) structure, and are stacked in four stages to form one SD
A RAM is formed.

[0022]

As described above, according to the present invention, the chip select signal (CS), the clock enable signal (CKE),
The number of controllable SDRAMs is increased by using the address signal (A12) and generating four output control signals called new chip select signals (CSO0 to CSO3).
Can be configured. 32Mbit × 8b
16Mbit x 4bit compared to SDRAM parts
Since four SDRAM parts are quite inexpensive, a large-capacity DIMM can be constructed at low cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an example of a DIMM to which the present invention is applied.

FIG. 2 shows a 32 Mbit × 8 bit configuration of a DIMM.
FIG.

FIG. 3 is a time chart of a control signal of the DIMM.

FIG. 4 is a configuration diagram of a DIMM control unit to which a bank address signal is input.

FIG. 5 is a configuration diagram of a conventional DIMM.

[Explanation of symbols]

 1 32Mbit × 8bit SDRAM 2 16Mbit × 4bit SDRAM

Claims (8)

[Claims] 1. An SDRAM control circuit for generating a control signal for an SDRAM module, comprising: a first circuit for receiving an address signal and a clock enable signal and outputting a plurality of new clock enable signals; A second circuit for receiving a clock enable signal and a chip select signal output from the second circuit and outputting a plurality of new chip select signals.
Control circuit. 2. An SDRAM module, comprising:
A first SDRAM unit, wherein each of the first SDRAM units includes a first SDRAM unit.
2. The SDRAM control circuit according to claim 1, comprising a plurality of second SDRAMs having a smaller memory capacity than the DRAM unit. 3. The SDRAM control circuit according to claim 2, wherein a chip select signal output from a second circuit is input to said second SDRAM. 4. The SDRAM control circuit according to claim 1, wherein the address signal is a bank address signal. 5. An SD comprising a plurality of first SDRAM units
A RAM module, wherein the first SDRAM section has a smaller memory capacity than the SDRAM.
SDRAM configured to receive an address signal and output a signal for controlling the second SDRAM
An SDRAM module comprising a control circuit. 6. The signal output from the SDRAM control circuit is:
6. The SDRAM module according to claim 5, wherein the SDRAM module is a chip select signal for controlling the second SDRAM. 7. An SDRAM control circuit, comprising: a first circuit that receives an address signal and a clock enable signal and outputs a plurality of new clock enable signals; a clock enable signal output from the first circuit and a chip select signal A second circuit for receiving a signal and outputting a plurality of new chip select signals.
M module. 8. The SDRAM module according to claim 1, wherein:
7. An inline memory module.
Or the SDRAM module according to 7.