JP2001308192A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for analog circuit. SOLUTION: The semiconductor device comprises a semiconductor substrate, an MOS transistor provided on the semiconductor substrate and having a gate electrode comprising a polysilicon layer and a metal silicide layer, a capacitor comprising a first polysilicon layer and an interlayer insulation layer forming a lower electrode and a second polysilicon layer forming an upper electrode layer, and a resistor comprising a single polysilicon layer. The first polysilicon layer of the capacitor is formed simultaneously with the polysilicon layer of the resistor. A part of the first polysilicon layer forming the lower electrode of the capacitor is doped lightly as compared with the peripheral part thereof and the sheet resistance is 30-1000 Ω/(square).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for an analog circuit such as a capacitor electrode or a MISFET gate formed of a polycrystalline silicon layer (film). is there.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated devices have been extremely miniaturized. With such miniaturization, the line width of gates and wirings used in devices has been reduced. Japanese Patent Publication No. Sho 62-31506 discloses a method of reducing the short channel effect caused by a reduction in the line width of a gate by CVD (Chemical Vapor Depo) by thermal decomposition of TEOS (tetraethoxysilane).
a so-called LDD (Light), in which an insulating layer is formed by the formation of an insulating layer, sidewalls are formed by anisotropic dry etching, and the source and the drain have a double structure
ly Doped Drain) structure is described.

Further, since the line width of gates and wirings is reduced with miniaturization, there is a problem that the resistance is increased and the signal transmission characteristics are reduced. In order to solve such a problem, U.S. Pat. No. 4,392,299 discloses that a low-resistance gate or wiring is formed by laminating silicide on polycrystalline silicon.

[0004]

However, in an analog circuit, a resistance element and a capacitor are frequently used, and a high-resistance resistance element is formed by wiring having a laminated structure of a low-resistance polycrystalline silicon layer and a silicide layer as described above. If it is formed, it is necessary to lengthen the wiring, and there is a problem that the chip area is increased.

FIG. 2 is a circuit diagram showing a configuration of a general switched capacitor filter (hereinafter abbreviated as SCF). In FIG. 2, C1 and C2 are each configured as an aggregate of a plurality of unit capacitors. An example of a method for manufacturing a semiconductor device having this unit capacitor will be described with reference to FIG.

[0006] First, as shown in FIG.
After forming a field oxide layer 2 on the plate 1,
A first polycrystalline silicon layer (policy)
Recon layer 3 is made of, for example, SiH_Four By thermal decomposition of gas
accumulate. Next, the first polycrystalline silicon is used to reduce the resistance.
POCl for the_Three And other impurities by diffusion method
Is diffused at a high concentration, and the heavy dope layer H₁ Toss
You. Heavy dope layer H ₁ First polycrystalline silicon
On the layer 3, as shown in FIG.
In the formation region A and the capacitor formation region B respectively.
After providing the gate 8, an example is given for the first polycrystalline silicon layer 3.
For example, by photolithography and etching
Gate electrode 3A (H₁ ) And capacitors
Lower electrode 3B (H_Two ) Is formed (see FIG. 3C).
In FIG. 3, reference numeral 10 denotes a gate oxide layer.

Next, as shown in FIG. 3D, an interlayer insulating layer 4 is deposited on the heavy dope layer H ₁ by, for example, thermal oxidation or CVD. A second polycrystalline silicon layer 5 is deposited thereon (see FIG. 3E). Next, phosphorus is diffused into the second polycrystalline silicon layer 5 at a high concentration by the same method as that for doping the first polycrystalline silicon layer 3, and this is also doped with a heavy doped layer H ₂ to reduce the resistance. (See FIG. 3F). Next, FIG.
After the resist 9 was provided on the second polycrystalline silicon layer 5 and the heavily doped layer H ₂ as shown in, subjected to patterning by, for example, photolithography on the second polycrystalline silicon layer 5 (Fig. 3 (H)).

FIG. 4 shows a second polycrystalline silicon layer 5.
After first patterning the first polycrystalline silicon layer 3
This is an example of patterning. In the manufacturing method described above,
In order to reduce the resistance of the gate electrode and the poly resistor (not shown in the figure), the impurity concentration of the first polysilicon layer increases. Therefore, in the capacitor lower electrode formed of the first polycrystalline silicon layer, crystal grains grow inside the layer 3 during the doping or in a subsequent heat step, and irregularities are generated on the layer surface. The unit capacitor formed on the polycrystalline silicon layer having such an uneven surface has a reduced specific accuracy. This ratio accuracy is determined by the capacitor C in FIG.
A ratio of ₁ and C _2, to determine the characteristics of the example integrators,
It also determines the characteristics of the SCF. Therefore, there is an inconvenience that the characteristics of the SCF composed of capacitors having low specific accuracy vary.

In addition, since the gate oxide layer and the interlayer insulating layer of the capacitor are reduced in the breakdown voltage and the like by mixing impurities from silicide or the like, the formation of the gate oxide layer and the interlayer insulating layer of the capacitor must be performed by the metal silicide layer. If performed after formation, there is a problem that reliability is impaired. There is also a demand that the gate oxide layer and the interlayer insulating layer of the capacitor are formed independently, so that an oxidation method suitable for each layer is used.

In view of the above, the present invention has a semiconductor device suitable for an analog circuit, and particularly has a capacitor with high specific accuracy, a low-resistance polycrystalline silicon gate electrode and a resistor,
Another object is to provide a semiconductor device with high mass productivity.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate, a MOS transistor provided on the semiconductor substrate and having a gate electrode composed of a polycrystalline silicon layer and a metal silicide layer, a first polycrystalline silicon layer forming a lower electrode, and an interlayer insulating layer. , A capacitor comprising a second polycrystalline silicon layer forming an upper electrode layer, and a resistor comprising a single polycrystalline silicon layer, wherein the first polycrystalline silicon layer of the capacitor and the resistor The polycrystalline silicon layer is formed at the same time as the first
The portion of the polycrystalline silicon layer where the lower electrode of the capacitor is formed has an impurity concentration relatively lower than that of its peripheral portion and a sheet resistance value of 30 to 1000 Ω /.
□ range.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the above-described semiconductor device, the semiconductor substrate and the capacitor may have the upper electrode layer and side surfaces thereof covered with an insulating layer.

In the above-described semiconductor device, the metal silicide is WSi, MoSi ₂ , TiSi ₂ , TaSi
₂ , or at least one layer selected from CoSi ₂ .

In the above-described semiconductor device, the interlayer insulating layer may be SiO ₂ .

In the above-described semiconductor device, the insulating layer may be SiO ₂ .

In the above-described semiconductor device, the insulating layer may be SiN. In the above-described semiconductor device, the capacitor may be a unit capacitor.

In the above-described semiconductor device, the resistance of the lower electrode layer portion may be higher than the resistance of another polycrystalline silicon layer.

The semiconductor device of the present invention can be manufactured by the following method.

Forming a field oxide layer and a gate oxide layer on a semiconductor substrate, depositing a first polycrystalline silicon layer, forming an insulating layer on the first polycrystalline silicon layer,
Forming a second polycrystalline silicon layer on the insulation, etching the second polycrystalline silicon layer except for a portion to be an upper electrode layer of the capacitor, and forming a first polycrystalline silicon layer covering the upper electrode layer and side surfaces thereof; After selectively applying a mask body and then forming a metal silicide layer, a second mask body is formed at a portion to be a gate electrode of the MOS transistor, and the first polycrystalline silicon layer and the metal silicide are formed. The layers are etched to form a capacitor including a gate electrode having a laminated structure of a polycrystalline silicon layer and a metal silicide layer, an electrode of the polycrystalline silicon layer, and an interlayer insulating layer of a silicon oxide layer.

In the method for manufacturing a semiconductor device described above,
The first mask body may be an insulating layer.

In the method of manufacturing a semiconductor device described above,
The first mask body is made of SiO ₂ formed by CVD.
It may be.

In the method of manufacturing a semiconductor device described above,
The first mask body may be SiN formed by CVD.

In the method of manufacturing a semiconductor device described above,
The first polycrystalline silicon layer has a sheet resistance of 30 to 1;
The impurities may be diffused so as to be 000Ω / □.

The semiconductor device of the present invention may be manufactured by the following method. Forming a field oxide layer and a gate oxide layer on a semiconductor substrate, depositing a first polysilicon layer, forming an insulating layer on the first polysilicon layer, and forming a second A polycrystalline silicon layer is formed, and the second polycrystalline silicon layer is etched except for a portion to be an upper electrode layer of the capacitor, and the upper electrode layer and its side surface and a single layer of the polycrystalline silicon layer become a resistor. A first mask body covering the portion is selectively applied, and then a metal silicide layer is formed. Then, a second mask body is formed on a portion to be a gate electrode of the MOS transistor, and the first mask body is formed.
Etching the polycrystalline silicon layer and the metal silicide layer to form a gate electrode having a laminated structure of the polycrystalline silicon layer and the metal silicide layer, an electrode of the polycrystalline silicon layer, and a capacitor comprising an interlayer insulating layer of a silicon oxide layer. A resistor made of a single crystalline silicon layer is formed.

In the above-described semiconductor manufacturing method, the second polycrystalline silicon layer is etched, the insulating layer on the first polycrystalline silicon layer is etched, and impurities are diffused to form the second polycrystalline silicon layer. The resistance between the polycrystalline silicon layer and the first polycrystalline silicon layer that is not covered by the second polycrystalline silicon layer may be reduced.

The semiconductor device of the present invention may be manufactured by the following method. Forming a first polycrystalline silicon layer on an oxide layer formed on a semiconductor substrate; and diffusing impurities into the first polycrystalline silicon layer to form a sheet of the first polycrystalline silicon layer. A step of controlling the resistance value within a range of 30 to 1000 Ω / □, and a second polycrystalline silicon layer which becomes an upper electrode of a capacitor via an insulating layer on the first polycrystalline silicon layer after the sheet resistance control step Forming a layer;
Patterning the second polycrystalline silicon layer to form an upper electrode of a unit capacitor; and forming the upper part of the first polycrystalline silicon layer using the second polycrystalline silicon layer left by the patterning as a mask. On the other hand, by further diffusing impurities, the first polycrystalline silicon layer below the second polycrystalline silicon layer and excluding the first polycrystalline silicon layer having a controlled sheet resistance value is removed. And a step of patterning the first polycrystalline silicon layer to form a gate and a lower electrode of a unit capacitor.

Further, the semiconductor device of the present invention may be manufactured by the following method. Forming a first polycrystalline silicon layer on an oxide layer formed on a semiconductor substrate; and diffusing impurities into the first polycrystalline silicon layer to form a sheet of the first polycrystalline silicon layer. Resistance value is 30-1000Ω / □
Controlling the first polycrystalline silicon layer to form a lower electrode of a gate and a capacitor; and forming the first polycrystalline silicon layer patterned by the patterning step. Forming an inter-layer insulating layer on the layer, forming a second poly-silicon layer serving as an upper electrode of the capacitor on the inter-layer insulating layer, and patterning the second poly-silicon layer; A first polycrystalline silicon layer below the second polycrystalline silicon layer by diffusing impurities into the second polycrystalline silicon layer, wherein the first polycrystalline silicon layer has a controlled sheet resistance value; Increasing the impurity concentration of the other portion except for the silicon layer.

[0028]

A field oxide layer for element isolation is formed on a semiconductor substrate such as a silicon substrate. A gate oxide layer is formed on a portion of the semiconductor substrate where the field oxide layer is not formed, a first polysilicon layer is formed on the gate oxide layer and the field oxide layer, and, for example, phosphorus is diffused as an impurity. The surface of the first polycrystalline silicon layer is oxidized by, for example, thermal oxidation in an oxidizing atmosphere, or an insulating layer of SiN or SiO ₂ is formed by CVD, and the _second layer is formed on the insulating layer in the same manner. Is formed. For example, phosphorus is diffused as an impurity. For example, the above-mentioned second polycrystalline silicon layer is etched by using a resist while leaving a portion to be the upper electrode of the capacitor, and the above-mentioned upper electrode layer and the first mask body covering the side surface thereof are selectively deposited. I do. As the first mask body, an insulating layer of SiN or SiO ₂ formed by CVD can be used.

Next, after forming a metal silicide layer,
A second mask body such as a resist is formed on a portion to be a gate electrode of the MOS transistor, and the first polycrystalline silicon layer and the metal silicide layer are etched. As the metal silicide, at least one selected from refractory metal silicides such as tungsten silicide (WSi), molybdenum silicide (MoSi ₂ ), titanium silicide (TiSi ₂ ), tantalum silicide (TaSi ₂ ), and cobalt silicide (CoSi ₂ ). A layer composed of the above layers can be used.

In this manner, a laminated structure of polycrystalline silicon and metal silicide (first conductive layer) is formed on the same substrate.
A semiconductor device comprising a MOS transistor having a gate electrode made of and a resistance element having a single-layer structure (second conductive layer) of polycrystalline silicon is obtained.

Similarly, it is possible to obtain a gate electrode having a laminated structure of a polycrystalline silicon layer and a metal silicide layer on the same semiconductor substrate, and a capacitor comprising an electrode of a polycrystalline silicon layer and an interlayer insulating layer of a silicon oxide layer. it can. For this reason, the wiring portion and the gate electrode portion have low resistance, and the capacitor portion has high withstand voltage and high specific accuracy.

When an impurity is diffused into the first polycrystalline silicon layer so that the sheet resistance becomes 30 to 1000 Ω / □, the growth of silicon crystal grains at the electrode portion can be suppressed. Can be reduced. Therefore, the specific accuracy of the unit capacitor is not reduced.

In addition, the upper electrode layer and its side surfaces are covered with the first mask body, and the portion of the polycrystalline silicon layer serving as the resistor is covered, thereby forming a laminated structure of the polycrystalline silicon layer and the metal silicide layer. A capacitor comprising a gate electrode comprising a polycrystalline silicon layer, an electrode comprising a polycrystalline silicon layer and an interlayer insulating layer comprising a silicon oxide layer, and a resistor comprising a single layer of a polycrystalline silicon layer can be formed. Therefore, in addition to the above-described capacitor and gate electrode, a high-resistance element can be formed, and the chip size can be reduced.

Further, the second polycrystalline silicon layer is etched, the insulating layer on the first polycrystalline silicon layer is etched, and impurities are diffused to form the second polycrystalline silicon layer and the second polycrystalline silicon layer. When the second polycrystalline silicon layer is doped by lowering the resistance with the first polycrystalline silicon layer which is not covered with the crystalline silicon layer, the gate electrode and the resistance formed by the first polycrystalline silicon layer are reduced. The body also has low resistance. Therefore, according to the present invention, it is possible to improve the performance of the SCF without lowering the specific accuracy of the unit capacitor while keeping the gate electrode and the like at low resistance.

In addition, the present invention can be carried out while maintaining mass productivity because the doping of the first and second polycrystalline silicon layers is performed by the thermal diffusion method.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals throughout the drawings, and repeated description will be omitted.

Embodiment 1 FIG. 1 is a process chart showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.
This is an example of forming an important capacitor in an S analog circuit. In a CMOS analog circuit, it is desirable to use a capacitor in which polycrystalline silicon having excellent voltage coefficient and temperature coefficient is used for both electrodes and an oxide layer of silicon is used as an interlayer insulating layer. Therefore, the present embodiment provides a method for realizing the above-mentioned interlayer insulating layer on the same substrate as a MOS transistor using a refractory metal silicide layer having excellent high-speed properties as a wiring and a gate material. It should be noted that wiring such as aluminum, a passivation layer, and the like are omitted.

In FIG. 1, 50 is a semiconductor substrate, 51 is a field oxide layer, 55 is a gate oxide layer, 52 is a first polycrystalline silicon layer, 53 is an interlayer insulating layer, 54 is a second polycrystalline silicon layer, Reference numeral 56 denotes a resist, 57 denotes an insulating layer serving as a first mask, 58 denotes a resist for forming the first mask, 59 denotes a metal silicide layer, and 60 denotes a second mask.

Referring to FIG. 1A, a field oxide layer 51 is formed on the surface of a silicon substrate 50 by a known method, and a gate oxide layer 55 is formed as a first insulating layer to a thickness of, for example, 250 ° in an active region. . Further, the polycrystalline silicon layer 52 is formed by LPCVD (Low Pressure).
Chemical Vapor Deposition
n) and the like, for example, to a thickness of 3000 °. The polycrystalline silicon layer 52 serves as a lower electrode of the capacitor, and also serves as a lower side of the laminated structure of the refractory metal silicide layer used for the gate and the wiring and the polycrystalline silicon layer. Next, the polycrystalline silicon layer 52 is doped with phosphorus as an impurity by a vapor phase diffusion method.

Next, the surface of the polycrystalline silicon layer 52 is thermally oxidized in an oxidizing atmosphere to form an interlayer insulating layer 53 as a second insulating layer. The thickness of the interlayer insulating layer 53 is, for example, 450
Å.

Further, a polycrystalline silicon layer 54 is formed on the interlayer insulating layer 53, and is doped with phosphorus. This polycrystalline silicon layer 54 is a portion to be the upper electrode of the capacitor. The formation conditions may be the same as the formation conditions of the polycrystalline silicon layer 52.

Next, as shown in FIG. 1B, a resist 56 is formed on a portion to be an upper electrode of the capacitor.
The polycrystalline silicon layer 54 is etched.

Next, after removing the resist 56, FIG.
As shown in FIG. 2C, the silicon oxide layer 57 formed by thermal decomposition of TEOS (tetraethoxysilane)
A third insulating layer is formed to a thickness of 0 °. The silicon oxide layer 57 as the third insulating layer only needs to have a sufficiently high etching selectivity with respect to the polycrystalline silicon layer 52, and may be, for example, silicon nitride instead of the silicon oxide layer 57.

Further, a resist 58 is formed on a portion of the polycrystalline silicon layer 52 which is to be a lower electrode of the capacitor on the silicon oxide layer 57, and the silicon oxide layer 57 and the interlayer insulating layer 53 are etched.
8 is removed, and a first mask body 57 is formed as shown in FIG. The first mask body 57 is attached so as to cover the upper surface and the side surface of the second polycrystalline silicon layer serving as the upper electrode layer. The second mask body serves as a mask when etching the metal silicide layer as described later, and also prevents contamination due to flying metal particles when etching the metal silicide layer.
Further, it plays a role of preventing a short circuit between the upper electrode and the lower electrode. Although not shown, the first polycrystalline silicon layer 54
Of the first mask body 5
7, that is, by selectively leaving the silicon oxide layer 57, the portion can be made a high resistance element.

Next, as shown in FIG. 1E, a tungsten silicide layer 59 is formed, for example, at 2000.degree.
Further, a resist 60 serving as a second mask body is formed in a portion where a multilayer structure of the polycrystalline silicon layer and the tungsten silicide layer is to be formed, and the tungsten silicide and the polycrystalline silicon are etched using a plasma etching method. At this time, the resist 60 is not etched, and has a laminated structure of a polycrystalline silicon layer and a metal silicide layer. This laminated structure becomes the gate electrode of the MOS transistor.

In the portion of the silicon oxide layer 57, tungsten silicide thereon is etched, but the polycrystalline silicon layer 52, the interlayer insulating layer 53, and the polycrystalline silicon layer 54 below the silicon oxide layer 57 are formed of silicon. Oxide layer 57 functions as a mask, and a capacitor including polycrystalline silicon layers 52 and 54 and interlayer insulating layer 53 can be formed. Further, the mask body formed on first polycrystalline silicon layer 52 serves as a high-resistance region where tungsten silicide is not deposited, and can be used as a resistance element.

Then, using the gate electrode as a mask, impurities are diffused into the active region to form source / drain diffusion layers (see FIG. 1F).

The thus obtained capacitor according to the present embodiment is suitable for oxidizing polycrystalline silicon because its interlayer insulating layer can be formed separately from other layers, for example, a gate oxide layer. This can be performed under the conditions described above, and can be performed before the formation of the metal (W) silicide, so that contamination of the metal silicide can be prevented, and a highly reliable interlayer insulating layer can be obtained.

Further, the transistor has a laminated structure in which the gate portion is composed of a tungsten silicide layer and a polycrystalline silicon layer, and can operate at high speed with low resistance. 3.) Since the silicide layer can be formed independently before forming, a highly reliable gate oxide layer can be obtained.

As described above, according to this embodiment, the gate oxide layer and the interlayer insulating layer of the capacitor can be formed before forming the polycrystalline silicon layer or the metal silicide layer.
In addition, since the first mask body covers the upper surface and the side surfaces of the upper electrode, it is possible to prevent contamination at the time of etching the metal silicide and to prevent unnecessary etching of the upper electrode.

Although the interlayer insulating layer is formed by thermal oxidation in this embodiment, it may be formed by CVD.

(Embodiment 2) This embodiment corresponds almost directly to the method of manufacturing the semiconductor device shown in FIG. However, in the present embodiment, as a result of controlling the phosphorus doping amount into the first polycrystalline silicon layer 52 to a specific value, the sheet resistance value is set to 30 to 1000 Ω / □, preferably 35 to 1000 Ω / □.
The method described above is different in that the step of controlling the first polycrystalline silicon layer 52 to be a lightly doped layer and the step of performing doping of the second polycrystalline silicon layer 54 after patterning are performed by controlling the first polycrystalline silicon layer 52 to Ω / □. different.

The sheet resistance value controlling step will be described. First, the first polycrystalline silicon layer 52 having a thickness of 3500.degree.
Is formed, the first polycrystalline silicon layer 52 is doped under specific conditions. This doping is performed by, for example, heating a mixed gas composed of N ₂ gas (5 L / min), O ₂ gas (0.5 L / min) and POCl ₃ gas (120 mg / min) to a temperature of about 1000 ° C. For 4 minutes. By following this condition,
The sheet resistance value of first polycrystalline silicon layer 52 can be controlled within the specific range described above. In a polycrystalline silicon layer exhibiting a sheet resistance value in this specific range, no crystal grains are generated inside the layer even when it is exposed to heat during doping or heat in a subsequent heat process. Does not occur.

After the step of controlling the sheet resistance of the first polycrystalline silicon layer 52, as shown in FIG. 1B, the non-doped second polycrystalline silicon in which impurities (dopants) are not diffused is formed. A resist 56 is provided on the layer 54, and the second polycrystalline silicon layer 54 is patterned. At this time, the lower interlayer insulating layer 53 may be patterned. Next, except that the doping time is set to 9 minutes for the exposed surface of the first polycrystalline silicon layer 52 not covered by the second polycrystalline silicon layer 54 and the second polycrystalline silicon layer 54. The doping is performed under the same conditions as the doping in the sheet resistance value control step. By this step, the dopant (phosphorus) concentration of the already patterned second polycrystalline silicon layer 54 increases, and the second polycrystalline silicon layer 54 becomes a heavy doped layer. The exposed portion of the first polycrystalline silicon layer 52 that is not covered by the second polycrystalline silicon layer 54 has a high concentration exceeding the dopant (phosphorus) concentration before doping, which is also a heavy doped layer. Become. Subsequently, the portion of the first polycrystalline silicon layer 52 covered by the second polycrystalline silicon layer 54 becomes a lightly doped layer with the dopant (phosphorus) concentration before doping. continue,
1C to 1F, a semiconductor device having a target unit capacitor structure and a semiconductor having a gate electrode and a resistor is obtained.

In such a semiconductor device, the first polycrystalline silicon layer 52 surrounded by the above-mentioned heavy doped layer is formed.
In the part, the dopant concentration is maintained in a predetermined range, and the light-doped layer remains. The lightly-doped layer functions as a lower electrode of the capacitor, and the heavyly-doped layer above the lightly-doped layer functions as an upper electrode of the capacitor. Both doped layers form a unit capacitor via the interlayer insulating layer 53. C ₁ or C ₂ of the SCF in FIG 2 and aggregate multiple units capacitors
Is configured. In the present embodiment, the sheet resistance of the lightly doped layer as the lower electrode of the capacitor is controlled within a specific range, and the surface thereof has no irregularities.
The lightly doped layer does not lower the specific accuracy of the unit capacitor. Since the lightly doped layer having less unevenness on the surface is used as one electrode in the unit capacitor, the specific accuracy can be easily raised, and the performance of the SCF can be improved.

In the above embodiment, the patterned second
Although the doping time for making the polycrystalline silicon layer 54 a heavy dope layer was 9 minutes, the doping amount may be arbitrarily changed to 4 to 9 minutes. In this case, the patterned second polysilicon layer 54 does not become a heavy doped layer, but becomes a lightly doped layer similarly to the first polycrystalline silicon layer 52 in a lower portion thereof. However, even in this case, the portion adjacent to the first polycrystalline silicon layer 52 which is a lightly doped layer becomes a heavy doped layer because the impurity concentration becomes high. Also in this case, the first
The portion of the lightly doped layer in the polycrystalline silicon layer 52 functions as the lower electrode of the capacitor as in the case of the above embodiment.

It should be noted that also in this embodiment, not only the first polycrystalline silicon layer 52 but also the second polycrystalline silicon layer 54 can be doped for light doping. Further, in each of the above-described embodiments, since it can be manufactured using a conventional thin layer deposition technique, impurity diffusion technique, or the like, there is an effect that the mass productivity is excellent. Furthermore, in each of the above embodiments, phosphorus was used as the dopant, but the present invention is not limited to this.

[0058]

As described above, according to the present invention,
Excellent transistor with high-speed operation having a gate with a laminated structure of a polycrystalline silicon layer and a metal silicide layer, and excellent voltage coefficient using a polycrystalline silicon thermal oxide layer as an interlayer insulating layer and polycrystalline silicon as both electrodes. Capacitor formed. In addition, by forming a gate oxide layer of a transistor before introducing high-concentration impurities into polycrystalline silicon and forming an interlayer insulating layer of a capacitor before forming a metal silicide layer, contamination of impurities and metal silicide can be prevented. In addition to preventing the insulating layer, the oxidation of the gate oxide layer and the oxidation of the interlayer insulating layer can be performed separately,
The semiconductor device can be formed under oxidation conditions suitable for each of them, and a highly reliable semiconductor device can be provided.

Further, since the first mask body covers the upper and side surfaces of the upper electrode, it is possible to prevent contamination during etching of the metal silicide layer and to prevent unnecessary etching of the upper electrode. it can.

Further, in addition to the above-described transistor and capacitor, a single-layer structure of high-resistance polycrystalline silicon can be formed over the same substrate. Therefore, a capacitor having an excellent voltage coefficient, a resistance element requiring a high resistivity, and a gate portion and a wiring portion requiring high speed can be formed on the same substrate.

Further, since the sheet resistance of the lower electrode of the unit capacitor is controlled within the range of 30 to 1000 Ω / □, the performance of the SCF to which the present invention is applied is maintained without lowering the specific accuracy of the unit capacitor. Can be improved. Further, when doping the second polycrystalline silicon layer, the resistance of the gate electrode and the resistor formed of the first polycrystalline silicon is also reduced. Therefore, according to the present invention, it is possible to maintain S
It is possible to improve the performance of CF.

Further, the present invention can be carried out while maintaining mass productivity because the doping of the first and second polycrystalline silicon layers is performed by the thermal diffusion method.

[Brief description of the drawings]

FIGS. 1A to 1F are process diagrams for explaining a first embodiment of a method of manufacturing a semiconductor device according to the present invention, wherein FIGS. 1A to 1F are schematic cross-sectional views showing the configuration of a semiconductor device after each process; It is.

FIG. 2 is a circuit diagram showing a configuration of a general SCF.

FIGS. 3A to 3H are process diagrams for explaining an example of a conventional method for manufacturing a semiconductor device, and FIGS. 3A to 3H are schematic cross-sectional views showing the configuration of the semiconductor device after each process.

FIGS. 4A to 4I are process diagrams illustrating an example of a conventional method for manufacturing a semiconductor device, and FIGS. 4A to 4I are schematic cross-sectional views showing the configuration of the semiconductor device after each process.

[Explanation of symbols]

 Reference Signs List 50 semiconductor substrate 51 field oxide layer 52 first polycrystalline silicon layer 53 interlayer insulating layer 55 gate oxide layer 54 second polycrystalline silicon layer 56 resist 57 first mask body (insulating layer, silicon oxide layer) 58 resist 59 Metal silicide layer 60 Second mask body (resist)

Claims (1)

[Claims] 1. A semiconductor substrate, a MOS transistor provided on the semiconductor substrate and having a gate electrode composed of a polycrystalline silicon layer and a metal silicide layer, and a first polycrystalline silicon layer forming a lower electrode And a second polycrystalline silicon layer forming an upper electrode layer, and a resistor made of a single polycrystalline silicon layer, wherein the first polycrystalline The silicon layer and the polycrystalline silicon layer of the resistor are formed at the same time, and the portion of the first polycrystalline silicon layer forming the lower electrode of the capacitor has an impurity concentration relatively higher than that of its peripheral portion. And a sheet resistance value in the range of 30 to 1000 Ω / □.