HK1118379B - Semiconductor component and method of manufacture - Google Patents

Description

Semiconductor component and method for manufacturing the same

Technical Field

The present invention relates generally to semiconductor components, and more particularly to semiconductor components including one or more passive circuit elements.

Background

Semiconductor component manufacturers are continually striving to increase the functionality and performance of their products while reducing the cost of the products. One way to increase functionality and performance has been to increase the number of circuit elements fabricated from semiconductor wafers. As will be appreciated by those skilled in the art, a semiconductor wafer is divided into a plurality of areas or regions called chips or dies. The same circuit elements are fabricated in each chip. Increasing the number of chips in a semiconductor wafer reduces the cost of manufacturing semiconductor components. However, a drawback of integrating a large number of circuit elements in a semiconductor wafer is that it increases the area occupied by each chip and thereby reduces the number of chips that can be manufactured from a single semiconductor single wafer. Integrating passive circuit elements with active circuit elements also increases chip size because they occupy a larger area than active devices. Thus, in reducing manufacturing costs, semiconductor component manufacturers compromise the number of circuit elements that can be fabricated in a chip and the number of chips that can be obtained from a semiconductor wafer.

Another drawback of monolithically integrating passive and active circuit elements in a semiconductor chip is that the tools for fabricating passive circuit elements are optimized for fabricating larger geometry devices, while the tools for fabricating active circuit devices are optimized for fabricating smaller geometry devices. For example, equipment used in the manufacture of passive circuit elements is accurate to within a tenth of a micron, while equipment used in the manufacture of active circuit elements is accurate to within a thousandth of a micron.

It would therefore be advantageous to have an area and cost effective method for fabricating passive and active circuit elements in a semiconductor chip. It is a further advantage to be able to use common equipment or kits for manufacturing both passive and active circuit components.

Drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference designators refer to like elements, and in which:

FIG. 1 is a cross-sectional view of a semiconductor component at an initial stage of manufacture according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of the semiconductor component of FIG. 1 at a later stage in its manufacture;

FIG. 3 is a cross-sectional view of the semiconductor component of FIG. 2 at a later stage in fabrication;

FIG. 4 is a cross-sectional view of the semiconductor component of FIG. 3 at a later stage in fabrication;

FIG. 5 is a cross-sectional view of the semiconductor component of FIG. 4 at a later stage in fabrication;

FIG. 6 is a cross-sectional view of the semiconductor component of FIG. 5 at a later stage in fabrication;

FIG. 7 is a cross-sectional view of the semiconductor component of FIG. 6 at a later stage in fabrication;

FIG. 8 is a cross-sectional view of the semiconductor component of FIG. 7 at a later stage in fabrication;

FIG. 9 is a cross-sectional view of the semiconductor component of FIG. 8 at a later stage in fabrication;

FIG. 10 is a cross-sectional view of the semiconductor component of FIG. 9 at a later stage in fabrication;

FIG. 11 is a cross-sectional view of the semiconductor component of FIG. 10 at a later stage in fabrication;

FIG. 12 is a cross-sectional view of the semiconductor component of FIG. 11 at a later stage in fabrication;

FIG. 13 is a cross-sectional view of the semiconductor component of FIG. 12 at a later stage in fabrication;

fig. 14 is a cross-sectional view of a semiconductor component according to another embodiment of the present invention;

fig. 15 is a cross-sectional view of a semiconductor component according to another embodiment of the present invention;

fig. 16 is a cross-sectional view of a semiconductor component at an initial stage of manufacture according to another embodiment of the present invention;

fig. 17 is a cross-sectional view of the semiconductor component of fig. 16 at a later stage in fabrication;

FIG. 18 is a cross-sectional view of the semiconductor component of FIG. 17 at a later stage in fabrication;

FIG. 19 is a cross-sectional view of the semiconductor component of FIG. 18 at a later stage in fabrication;

FIG. 20 is a cross-sectional view of the semiconductor component of FIG. 19 at a later stage in fabrication;

FIG. 21 is a cross-sectional view of the semiconductor component of FIG. 20 at a later stage in fabrication;

fig. 22 is a cross-sectional view of a semiconductor component at an initial stage of manufacture according to another embodiment of the present invention;

fig. 23 is a cross-sectional view of the semiconductor component of fig. 22 at a later stage in manufacture;

fig. 24 is a cross-sectional view of the semiconductor component of fig. 23 at a later stage in manufacture;

FIG. 25 is a cross-sectional view of the semiconductor component of FIG. 24 at a later stage in fabrication;

fig. 26 is a cross-sectional view of the semiconductor component of fig. 25 at a later stage in manufacture;

fig. 27 is a cross-sectional view of the semiconductor component of fig. 26 at a later stage in manufacture;

fig. 28 is a cross-sectional view of the semiconductor component of fig. 27 at a later stage in manufacture;

fig. 29 is a cross-sectional view of the semiconductor component of fig. 28 at a later stage in manufacture;

fig. 30 is a cross-sectional view of the semiconductor component of fig. 29 at a later stage in manufacture;

fig. 31 is a cross-sectional view of the semiconductor component of fig. 30 at a later stage in manufacture;

FIG. 32 is a cross-sectional view of the semiconductor component of FIG. 31 at a later stage in manufacture;

FIG. 33 is a cross-sectional view of the semiconductor component of FIG. 32 at a later stage in fabrication;

fig. 34 is a cross-sectional view of a semiconductor component at an initial stage of manufacture according to another embodiment of the present invention;

FIG. 35 is a cross-sectional view of the semiconductor component of FIG. 34 at a later stage in its manufacture;

FIG. 36 is a cross-sectional view of the semiconductor component of FIG. 35 at a later stage in fabrication;

fig. 37 is a cross-sectional view of a semiconductor component at a beginning stage of manufacture according to another embodiment of the present invention;

fig. 38 is a cross-sectional view of the semiconductor component of fig. 37 at a later stage in manufacture;

fig. 39 is a cross-sectional view of the semiconductor component of fig. 38 at a later stage in manufacture;

fig. 40 is a cross-sectional view of the semiconductor component of fig. 39 at a later stage in manufacture.

Detailed Description

In general, the present invention provides vertically integrated passive and active devices and methods of fabricating such vertically integrated passive and active devices. According to one embodiment of the present invention, a resistor, a metal-insulator-metal ("MIM") capacitor, an inductor, and an active device are fabricated as a monolithic integrated circuit. It should be noted that inductors and capacitors are also referred to as energy storage elements or devices. The resistor is fabricated in a first device level or a first circuit element level. The resistor may be a precision resistor formed of metal or other resistive material. The MIM capacitor is fabricated in a second device level or a second circuit element level, wherein the second circuit element level is in a higher plane than the first circuit element level. Preferably, the two plates of the MIM capacitor consist essentially of aluminum. The inductor is fabricated in a third device level or a third circuit element level using a copper damascene process, wherein the third device level or the third circuit element level is in a higher plane than the second circuit element level. Thus, integrated active devices are fabricated using either a single damascene process or a dual damascene process, which allows the devices to be integrated into high performance semiconductor fabrication processes. The use of a damascene process to form the inductor allows it to be fabricated with aspect ratios greater than about 0.7: 1 to 5: 1 and with line widths less than about 3.5 microns. It should be noted that the aspect ratio is the ratio of the height of the inductor to its width. Furthermore, integrated passive devices can be fabricated on top of active devices, further reducing the area occupied by the devices.

According to another embodiment, a passivation layer is formed on the copper inductor and on the copper interconnect layer (copper interconnect layer) of the first embodiment. An opening is formed in the passivation layer to expose copper of the interconnect layer, copper of the inductor, or copper of both the interconnect layer and the inductor. Aluminum is formed on copper. Forming aluminum on copper according to this embodiment overcomes the difficulty of passivating copper. Thus, the present invention allows vertical integration of passive circuit elements formed of copper and allows packaging of circuit elements using silicon wafer packaging techniques. For example, a wire bond or bump bond (bump) may be formed to the aluminum over the copper.

According to another embodiment, the resistor is in a first circuit element level, the inductor is in a second circuit element level, and the MIM capacitor is fabricated in a third circuit element level. The inductor may be fabricated using a single damascene process or a dual damascene process. According to this embodiment, an aluminum layer is formed in electrical contact with the copper, wherein the aluminum layer forms one plate of the MIM capacitor.

According to another embodiment, the resistor is in a first circuit element level, the inductor is in a second circuit element level, and the MIM capacitor is fabricated in a third circuit element level. The inductor may be fabricated using a single damascene process or a dual damascene process. According to this embodiment, a portion of the inductor forms one of the plates of the MIM capacitor. The capacitance value of the MIM capacitor is set by exposing a predetermined portion or size of the inductor. A dielectric material for the MIM capacitor is formed on the exposed portion of the copper inductor.

It should be noted that a circuit level is also referred to as a vertical planar area (vertical planar area), where one vertical planar area is either above or below the other.

Fig. 1 is a side cross-sectional view of a portion of a semiconductor component 10 during fabrication according to an embodiment of the present invention. Shown in fig. 1 is a substrate 12 having a major surface 14. The active device 16 and the passive components 18 are formed from the substrate 12. Techniques for forming active devices in or on a substrate are well known to those skilled in the art. The active devices 16 may be diodes, Zener diodes (Zener diodes), field effect transistors, bipolar transistors, or the like, while the passive devices 18 may be resistors, capacitors, inductors, or the like. Although only one active device and one passive device are described, it should be understood that one or more active and passive devices may be formed from substrate 12. Alternatively, the substrate 12 may be free of active devices, passive devices, or both active and passive devices. According to one embodiment, the substrate 12 is silicon doped with a P-type conductivity impurity material such as boron. By way of example, the substrate 12 may have a resistivity of from about 0.001 ohm-centimeters (Ω -cm) to about 10000 Ω -cm. Although the substrate 12 may be a high resistivity substrate, the resistivity or dopant concentration of the substrate 12 is not a limitation of the present invention. Similarly, the type of material used for substrate 12 is not limited to silicon, and the conductivity type of substrate 12 is not limited to P-type conductivity. It is understood that the impurity material is also referred to as a dopant or impurity species (inpurityspecies). Other suitable materials for substrate 12 include polysilicon, germanium, silicon germanium, semiconductor-on-insulator ("SOI") materials, and the like. In addition, the substrate 12 may be composed primarily of compound semiconductor materials, such as III-V semiconductor materials, II-VI semiconductor materials, and the like.

Referring now to FIG. 2, having a thickness ranging from about 1000 angstromsTo about 60000Is formed on surface 14. According to one embodiment, dielectric material 20 is formed by decomposing tetraethylorthosilicate ("TEOS") to form a dielectric layer having a thickness of about 8000 aAn oxide layer of (a). The dielectric layer formed in this manner is commonly referred to as TEOS. The type of material used for the dielectric layer 20 is not a limitation of the present invention. A photoresist layer is formed over the TEOS layer 20 and patterned to have openings that expose portions of the TEOS layer 20. The remaining portion of the photoresist layer serves as a masking structure 26.

Referring now to fig. 3, an opening is formed in the exposed portion of the dielectric layer 20 using, for example, anisotropic reactive ion etching. The opening exposes active device 16, passive device 18, and a portion of substrate 12. A refractory metal layer (not shown) is conformally deposited over the active 16, passive 18 and exposed portions of the substrate 12 and over the dielectric layer 20. By way of example, the refractory metal is nickel, having a thickness of from about 50To about 150Is measured. The refractory metal is heated to a temperature of from about 350 degrees celsius (c) to about 500 c. The heat treatment reacts the nickel with the silicon to form nickel silicide (NiSi) in all regions where the nickel is in contact with the silicon. Thus, the silicided region 28 is formed by the active device 16, the silicided region 30 is formed by the substrate 12, and the silicided regions 32 and 34 are formed by the passive device 18. The nickel portion on dielectric layer 20 remains unreacted. After the formation of the nickel silicide region, any unreacted nickel is removed. It should be understood that the type of silicide is not a limitation of the present invention. For example, other suitable silicides include titanium silicide (TiSi), platinum silicide (PtSi), cobalt silicide (CoSi)₂) Or the like. As will be appreciated by those skilled in the art, silicon is consumed during the formation of the silicide, and the consumed silicon is consumedThe amount of (c) varies with the type of silicide formed.

According to one embodiment, the passive device 18 is a resistor and the silicide region 30 serves as a ground. The mask structure 26 is removed.

Referring now to FIG. 4, having a thickness ranging from about 25 aTo about 200Is formed on dielectric layer 20 and within the opening formed within dielectric layer 20. Has a thickness ranging from about 75To about 600Titanium nitride layer 33 is formed on titanium layer 31. Has a thickness in the range of about 5000 aTo about 40000Is formed on the titanium nitride layer 33. By way of example, the aluminum layer 35 has a thickness of about 20000Is measured. Having a thickness ranging from about 400 aTo about 900Is formed on the aluminum layer 35. Layers 31, 33, 35, and 36 may be formed using chemical vapor deposition ("CVD"), plasma enhanced chemical vapor deposition ("PECVD"), sputtering, evaporation, or the like. It should be understood that the materials of layers 31, 33 and 36 are not limited toAnd are not limiting of the present invention. Other suitable materials for layer 31 include tantalum, tungsten, platinum, refractory metal compounds, refractory metal carbides, refractory metal borides, or the like, and other suitable materials for layers 33 and 36 include tantalum nitride, carbon-doped metal nitrides, silicon-doped metal nitrides, or the like. Having a thickness ranging from about 400 aTo about 2500Is formed over titanium nitride layer 36. Suitable dielectric materials for layer 37 include silicon nitride, silicon dioxide, and dielectric materials having a high dielectric constant, i.e., a dielectric constant greater than 3.9, dielectric materials having a low dielectric constant, and the like. Having a thickness ranging from about 500 aTo about 4000Is formed on the dielectric layer 37. Having a thickness ranging from about 600 aTo about 1200Titanium nitride layer 39 is formed on aluminum layer 38. A photoresist layer is formed over titanium nitride layer 39 and patterned to have openings that expose portions of titanium nitride layer 39. The remaining portion of the photoresist layer serves as a masking structure 42.

Referring now to fig. 5, the exposed portion of titanium nitride layer 39 and the portion of aluminum layer 38 underlying the exposed portion of titanium nitride layer 39 are anisotropically etched using, for example, a reactive ion etch. Dielectric layer 37 serves as an etch stop layer. Thus, etching aluminum layer 38 exposes a portion of dielectric layer 37. The exposed portion of dielectric layer 37 is anisotropically etched using titanium nitride layer 36 as an etch stop. After the anisotropic etch, portions 39A, 38A, and 37A of titanium nitride layer 39, aluminum layer 38, and dielectric layer 37 remain. Portion 37A serves as a dielectric layer for metal-insulator-metal (MIM) capacitor 50 and portions 38A and 39A together form conductor 41 of MIM capacitor 50, i.e., conductor 41 serves as one plate of MIM capacitor 50. A portion of the aluminum layer 35 serves as the other plate of the MIM capacitor 50. This plate will be further described with reference to fig. 7. The mask structure 42 is removed.

Referring now to fig. 6, a photoresist layer is formed over silicon nitride layer 37 and over portion 39A of silicon nitride layer 37. The photoresist layer is patterned to have an opening 52 that exposes a portion of titanium nitride layer 36. The remaining portion of the photoresist layer serves as a masking structure 54.

Referring now to fig. 7, the exposed portion of titanium nitride layer 36 and the portions of layers 35, 33, and 31 underlying the exposed portion of titanium nitride layer 36 are anisotropically etched using, for example, reactive ion etching. The dielectric layer 20 serves as an etch stop layer. After the anisotropic etch, portions 35A, 35B, 35C, 35D, 35E, and 35F of aluminum layer 35, portions 36A, 36B, 36C, 36D, 36E, and 36F of titanium nitride layer 36, and portions 31A, 31B, 31C, 31D, 31E, and 31F of titanium layer 31 remain. Portions 31A, 33A, 35A, and 36A collectively form conductor 56; portions 31B, 33B, 35B, and 36B collectively form conductor 58; portions 31C, 33C, 35C, and 36C collectively form conductor 36; portions 31D, 33D, 35D, and 36D collectively form conductor 61; portions 31E, 33E, 35E, and 36E collectively form conductor 62, and portions 31F, 33F, 35F, and 36F collectively form conductor 63. Conductors 56 and 58 serve as conductors for active device 16 and ground 32, respectively, while conductor 60 serves as the other plate of MIM capacitor 50. Conductors 62 and 63 serve as conductors for passive device 18.

Referring now to fig. 8, a layer of dielectric material 64 is formed. According to one embodiment, dielectric material 64 is TEOS. The type of material used for the dielectric layer 64 is not a limitation of the present invention. Dielectric layer 64 is planarized using a planarization technique (CMP) to have about 2000 a above conductor 41, i.e., one plate of MIM capacitor 50To about 25000The thickness range of (a). Having a thickness ranging from about 500 aTo about 3000Is formed over the dielectric layer 64. Preferably, the dielectric material of the etch stop layer 66 has a different etch selectivity than the dielectric material of the dielectric layer 64. Suitable materials for the etch stop layer 66 include silicon nitride, silicon carbide, silicon carbon nitride ("SiCN"), silicon carbon nitro-oxide ("SiCNO"), or the like. A photoresist layer is formed on the etch stop layer 66 and patterned to have openings 68 that expose portions of the etch stop layer 66. The remaining portion of the photoresist layer serves as a masking structure 70.

Referring now to fig. 9, the exposed portions of etch stop layer 66 are anisotropically etched to expose portions 72, 74, 76, 78, 80, and 82 of dielectric layer 64. By way of example, a reactive ion etch is used to etch stop layer 66. The mask structure 70 is removed.

Referring now to FIG. 10, having a thickness ranging from about 10000 aTo about 120000Is formed on the exposed portion of etch stop layer 66 and the exposed portion of dielectric layer 64. According to one embodiment of the present invention, dielectric material 84 is TEOS. The type of material used for dielectric material 84 is not a limitation of the present invention. Optionally, a planarization technique, such as CMP, may be employed to planarize the dielectric layer 84. A photoresist layer is formed over dielectric layer 84 and patterned with openings 86 that expose portions of dielectric layer 84. The remainder of the photoresist layerThe remaining portion serves as a mask structure 88.

Referring now to fig. 11, the exposed portions of the dielectric layer 84 are anisotropically etched using, for example, a reactive ion etch and an etch chemistry (etch chemistry) that preferentially etches oxide. The etch stops on the exposed portions of silicon nitride layer 66, on the exposed portions of conductors 41, and on the exposed portions of conductors 61 to leave openings 90 and 92, also referred to as damascene openings. Masking structure 88 is removed. A barrier layer 94 is formed on the exposed areas of portion 66 along the sidewalls of openings 90 and 92 on the exposed portions of conductors 41 and 61. By way of example, barrier layer 94 is titanium nitride. Alternatively, the barrier layer 94 may consist essentially of an adhesive sub-layer (adhesive sub-layer) formed to contact the sidewalls of the openings 90 and 92 and contact the exposed areas of the portions 66 and a barrier sub-layer. By way of example, the adhesion sublayer is titanium and the barrier sublayer is titanium nitride. The materials used for the sublayers are not limiting to the invention.

Referring now to fig. 12, a copper layer is formed over the barrier layer 94. The copper layer is planarized using, for example, CMP techniques. The remaining portion 94A of barrier layer 94 and the copper within opening 90 collectively form a conductive trace 96, and the remaining portion 94B of barrier layer 94 and the copper within opening 92 collectively form a conductive trace 98. The combination of conductive traces 96 and 98 and damascene openings 90 and 92, respectively, is referred to as a damascene structure and serves as a partial inductor 99. A passivation layer 100 is formed over dielectric layer 84 and conductive traces 96 and 98. A photoresist layer is formed over the passivation layer 94 and patterned with openings 102 that expose portions of the passivation layer 94. The remaining portion of the photoresist layer serves as a masking structure 104.

Referring now to fig. 13, the exposed portions of passivation layer 100 and portions of layers 84 and 64 are anisotropically etched using, for example, reactive ion etching to form contact openings (contacts) for active and passive devices 16 and 18, respectively. Thus, there has been provided an integrated passive device 108 comprising a resistor disposed in a first vertical level (vertical level), a capacitor disposed in a second vertical level, and an inductor disposed in a third vertical level. An advantage of the integrated passive device 108 is that it is a vertically stacked device that occupies less area than circuit elements that are horizontally disposed from one another. In addition, the inductor is fabricated using a damascene process that allows for smaller line widths and spacings with spacing and line aspect ratios greater than 1: 1.

Fig. 14 is a cross-sectional view of a semiconductor component 110 according to another embodiment of the present invention. Semiconductor component 110 is similar to semiconductor component 10 except that after etching titanium nitride layer 36 and aluminum layer 35, an etch stop layer 112 is formed over the exposed portions of dielectric layer 20 and the remaining portions of silicon nitride layers 36 and 39. By way of example, the etch stop layer 112 is of a thickness ranging from about 150 aTo about 2000Silicon nitride of (2). Including the etch stop layer 112 provides an additional process margin for etching involved in the formation of, for example, inductors and spacers.

Fig. 15 is a cross-sectional view of a semiconductor component 150 according to another embodiment of the present invention. Semiconductor component 150 is similar to semiconductor component 10 except that opening 152 is formed simultaneously with openings 90 and 92 (illustrated in fig. 11). Thus, barrier layer 94 is formed along the sidewalls of openings 90, 92, and 152 and on the exposed areas of conductors 41, 61, 56, 62, and 63. Copper formed on portions of barrier layer 94 within openings 90 and 92 is also formed on portions of the barrier layer within opening 152 and planarized using, for example, CMP to form conductors 154, 156, and 158. It should be noted that conductor 154 includes portion 94C of barrier layer 94, conductor 156 includes portion 94D of barrier layer 94, and conductor 158 includes portion 94E of barrier layer 94.

A silicon nitride layer 160 is formed over dielectric layer 84 and conductors 96, 98, 154, 156, and 158. An opening is formed on the silicon nitride layer 160 and an aluminum layer is formed on the silicon nitride layer 160 and within the opening. A photoresist layer is formed on the aluminum layer and patterned to have an opening exposing a portion of the aluminum layer. The exposed portions of the aluminum layer are etched leaving aluminum contacts 162, 164, and 166 in contact with conductors 154, 156, and 158, respectively. A layer of dielectric material 168 is formed on the silicon nitride layer 160 and on the aluminum contacts 162, 164, and 166. A photoresist layer is formed over the dielectric layer 168 and patterned to have openings that expose portions of the dielectric layer 168 over the aluminum contacts 162, 164, and 166. The exposed portions of dielectric layer 168 are removed, thereby exposing aluminum contacts 162, 164, and 166. Dielectric layers 160 and 168 serve as passivation layers. As will be appreciated by those skilled in the art, softer, spin-on type materials are typically used to passivate the copper. These softer types of materials are generally incompatible with wafer packaging technologies such as flip-chip packaging technology (flip-chip packaging technology). Forming aluminum over copper in accordance with the present invention overcomes the difficulty of passivating copper circuit elements. Thus, the present invention allows vertical integration of passive circuit elements formed of copper and allows packaging of circuit elements using silicon wafer packaging techniques.

Fig. 16 shows a cross-sectional view of a semiconductor component 200 during a manufacturing process according to another embodiment of the invention. It should be noted that the manufacturing steps described with reference to fig. 1-7 are also applicable to the manufacture of the semiconductor component 200. Accordingly, fig. 16 will be described further from the description of fig. 7, and reference numeral 200 will be used in place of reference numeral 10 in fig. 7. Having a thickness ranging from about 2000 aTo about 12000Is formed on conductors 41, 56, 58, 61, 62, 63, exposed portions of conductor 60, and exposed portions of dielectric layer 202. According to an embodiment of the present invention, dielectric material 202 is silicon nitride. The type of material used for the dielectric material 202 is not a limitation of the present invention. A photoresist layer is formed on the silicon nitride layer 202 and patterned to have an opening 204 exposing a portion of the silicon nitride layer 202. The remaining portion of the photoresist layer serves as a masking structure 206.

Referring now to fig. 17, the exposed portions of silicon nitride layer 202 are anisotropically etched to expose conductors 56, 58, 41, 61, 62, and 63. The mask structure 206 is removed.

Referring now to fig. 18, a layer of dielectric material 208 is formed over the exposed portions of conductors 41, 56, 58, 61, 62, 63 and the remaining portion of dielectric layer 202. According to one embodiment of the present invention, dielectric material 208 is TEOS. The type of material used for the dielectric layer 208 is not a limitation of the present invention. Preferably, the dielectric material of layer 202 has a different etch selectivity than the dielectric material of dielectric layer 208. Planarizing the dielectric layer 208 using a planarization technique, such as CMP, to have a thickness from about 10000 above the conductor 41To about 120000Wherein conductor 41 is one of the electrodes or plates of MIM capacitor 50. A photoresist layer is formed over the TEOS layer 208 and patterned with an opening 210 that exposes a portion of the layer 208. The remaining portion of the photoresist layer serves as a masking structure 212.

Referring now to fig. 19, the exposed portion of TEOS layer 208 is anisotropically etched to form an opening 209, opening 209 exposing conductors 41 and 61 and the remaining portion of silicon nitride layer 202 between conductors 41 and 61. The anisotropic etch process is enhanced if the dielectric 208 is selectively etched with respect to the dielectric 202. The mask structure 212 is removed. Referring now to FIG. 20, having a thickness ranging from about 50aTo about 250Is formed over the TEOS layer 208 and within the opening 209. Having a thickness in the range of up to about 250 aIs nitrided inA tantalum layer is formed on the tantalum layer. Having a thickness ranging from about 11000 aTo about 130000Is formed on the tantalum nitride layer. The copper, tantalum nitride and tantalum layers are planarized using, for example, CMP. The TEOS layer 208 serves as an etch stop. After the CMP step, portions 210, 212, and 214 of the copper layer, the tantalum nitride layer, and the tantalum layer remain within the opening 209. Portions 210, 212, and 214 collectively form conductor 218. It should be noted that the use of tantalum and tantalum nitride is not a limitation of the present invention and other materials may be formed between TEOS layer 208 and the copper layer.

Having a thickness ranging from about 2000 aTo about 10000Is formed over conductor 218 and a portion of TEOS layer 208. By way of example, the material of the dielectric layer 220 is silicon nitride. A photoresist layer is formed on dielectric layer 220 and patterned to expose portions 222 of silicon nitride layer 220. The remaining portion of the photoresist layer serves as a mask structure 224.

Referring now to fig. 21, the exposed portions of silicon nitride layer 220 are anisotropically etched to form openings that expose conductors 56 and 58 and portions of TEOS layer 202 laterally adjacent conductors 56 and 58. The mask structure 224 is removed.

Fig. 22 is a cross-sectional view of a semiconductor component 300 according to another embodiment of the present invention. Shown in fig. 22 is a semiconductor substrate 302 from which a plurality of active devices 304 and a plurality of passive devices 306 are formed. The active device 304 may be a diode, zener diode, thyristor, field effect transistor, bipolar transistor, combinations thereof, or the like, and the passive device 306 may be a resistor, capacitor, inductor, combinations thereof, or the like. While a plurality of active and passive devices have been described, it should be understood that one or more active and passive devices may be formed in or on substrate 302. Alternatively, the substrate 302 may be free of passive devices, active devices, or neither passive nor active devices. One or more of devices 304 or devices 306 may be electrically connected to each other.

According to one embodiment of the invention, substrate 302 is silicon doped with a P-type conductivity impurity material, such as boron. By way of example, the resistivity of the substrate 302 may be from about 0.001 ohm-centimeters (Ω -cm) to about 10000 Ω -cm. The resistivity of the substrate is selected according to the design criteria of the different semiconductor components. Although the substrate 302 may be a high resistivity substrate, the resistivity or dopant concentration of the substrate 302 is not a limitation of the present invention. Similarly, the type of material used for the substrate 302 is not limited to silicon, and the conductivity type of the substrate 302 is not limited to P-type conductivity. A layer of dielectric material 308 is formed on the substrate 302 and a resistor 310 is formed on the dielectric layer 308. A layer of dielectric material 312 is formed over the dielectric layer 308 and the resistor 310. According to one embodiment, resistor 310 is a metal resistor. Suitable materials for the metal resistor 310 include titanium nitride, titanium tungsten nitride ("TiWN"), nickel, tungsten, tantalum nitride, or the like. It should be noted that the resistor 310 is not limited to a metal resistor. Alternatively, it may be formed of a semiconductor material such as doped polysilicon or the like.

Referring now to FIG. 23, having a thickness ranging from about 2000 aTo about 10000Is formed on the dielectric layer 312. Has a thickness ranging from about 10000To about 120000Is formed on silicon nitride layer 314. Although the material of layer 314 is silicon nitride and the material of dielectric layer 316 is TEOS according to one embodiment, the materials used for layers 314 and 316 are not limited to silicon nitride and TEOS. However, it is desirable that the material used for layer 314 have a different etch rate than the material of layers 312 and 316. Thus, dielectric layer 314 is an etchant that is resistant to etching dielectric layers 312 and 316.

A photoresist layer is formed over the TEOS layer 316 and patterned with openings 318 that expose portions of the TEOS layer 316. The remaining portion of the photoresist layer serves as a masking structure 320.

Referring now to fig. 24, the exposed portions of TEOS layer 316 are anisotropically etched to form openings 330, 332, 334, 336, 338 and 340 within TEOS layer 316. According to one embodiment, the etch is a timed etch that terminates before openings 330-340 extend to silicon nitride layer 314. According to another embodiment, silicon nitride layer 314 serves as an etch stop layer and openings 330-340 extend to silicon nitride layer 314. Openings 330-340 are also referred to as damascene openings. The masking structure 320 is removed and another photoresist layer is formed over the TEOS layer 316 and within the openings 330-340. The photoresist layer is patterned to open portions of openings 330 and 332 again. The remaining portion of the photoresist layer serves as a masking structure 342.

Referring now to fig. 25, a portion of TEOS 316, a portion of silicon nitride layer 314, and a portion of TEOS 312 underlying the reopened portions of openings 330 and 332 are anisotropically etched using, for example, a reactive ion etch. The etching exposes the end regions of the resistor 310. The mask structure 342 is removed.

Referring now to fig. 26, a tantalum layer is formed over TEOS layer 316 and the exposed portion of resistor 310 and a tantalum nitride layer is formed over the tantalum layer. A copper layer is formed on the tantalum nitride layer and preferably fills openings 330-340. The copper, tantalum nitride and tantalum layers are planarized using, for example, CMP techniques. The TEOS layer 316 serves as an etch stop. After the planarization step, portions 346A, 346B, 346C, 346D, 346E and 346F of the tantalum layer remain within the openings 330-340, respectively; portions 348A, 348B, 348C, 348D, 348E, and 348F of the tantalum nitride layer remain on portions 346A-346F, respectively; portions 350A, 350B, 350C, 350D, 350E and 350F of the copper layer remain on portions 348A-348F, respectively. Portions 346A, 348A, and 350A collectively form conductor 352; portions 346B, 348B, and 350B collectively form conductor 354; portions 346C, 348C, and 350C collectively form conductor 356; portions 346D, 348D, and 350D collectively form conductor 358; portions 346E, 348E, and 350E collectively form conductor 360; and portions 346F, 348F, and 350F collectively form conductor 362. It should be understood that the materials of the tantalum layer, tantalum nitride and copper layer are not limitations of the present invention. Other suitable materials for use in place of tantalum include titanium, tungsten, platinum, refractory metal compounds, refractory metal carbides, refractory metal borides, or the like, and other suitable materials for use in place of tantalum nitride include titanium nitride, carbon-doped metal nitrides, silicon-doped metal nitrides, or the like. The combination of conductors 352-362 with damascene openings 330-340, respectively, is referred to as a damascene structure and may be used as part of an integrated passive device.

Having a thickness ranging from about 1000 aTo about 4000A dielectric material layer 366 is formed over TEOS layer 316 and conductor 352 and 362. Preferably, the dielectric material of layer 366 is silicon nitride. A photoresist layer is formed on the silicon nitride layer 366 and patterned to have an opening 368 that exposes a portion of the silicon nitride layer 366. The remaining portion of the photoresist layer serves as a masking structure 370.

Referring now to fig. 27, the exposed portions of silicon nitride layer 366 are anisotropically etched using, for example, a reactive ion etch to expose portions of conductors 352, 356, 358, 360, and 362. The mask structure 370 is removed.

Referring now to fig. 28, an aluminum layer is formed on silicon nitride layer 366 and the exposed portions of conductors 352, 356, 358, 360 and 362. The aluminum layer is planarized using, for example, CMP. Silicon nitride layer 366 serves as an etch stop layer for planarization, which leaves conductor 372 in contact with a portion of conductor 352, conductor 374 in contact with conductors 356, 358, and 360, and conductor 376 in contact with conductor 362.

Referring now to FIG. 29, having a thickness ranging from about 400 aTo about 2500Is formed on silicon nitride layer 366 and conductors 372, 374 and 376. Preferably, the dielectric material of layer 380 is silicon nitride. A photoresist layer is formed on the silicon nitride layer 380 and patterned to form a mask structure 390. A mask structure 390 overlies conductors 356, 358, and 360.

Referring now to fig. 30, the exposed portion of the silicon nitride layer 380 is anisotropically etched using, for example, reactive ion etching. After removing the exposed portions of silicon nitride layer 380, conductors 372 and 376 and portions of silicon nitride layer 366 are exposed. An aluminum layer 392 is formed on the conductors 372 and 376, on the remaining portions of the silicon nitride layer 380, and also on the exposed portions of the silicon nitride layer 366. The aluminum layer 392 is planarized using, for example, CMP. A photoresist layer is formed on the aluminum layer 392 and patterned with openings 394 that expose portions of the aluminum layer 392. The remaining portion of the photoresist layer serves as a mask structure 396.

Referring now to FIG. 31, exposed portions of aluminum layer 392 are anisotropically etched to form conductors 400, 402, 404, and 406. Etching the aluminum layer 392 exposes a portion of the silicon nitride layer 366. The exposed portions are anisotropically etched using a wet etchant (wet etch). Because the etch is an anisotropic etch, a portion of the silicon nitride layer 380 underlying the conductor 404 is etched laterally.

Referring now to FIG. 32, having a thickness ranging from about 4000 aTo about 15000Dielectric material layer 410 is formed over conductors 400 and 406, conductor 354, and the exposed portions of conductor 360 and TEOS layer 316. Having a thickness ranging from about 2000 aTo about 10000Is formed on the dielectric layer 410. By way of example, dielectric material 410 is TEOS and dielectric material 412 is silicon nitride. Although the type of material used for dielectric materials 410 and 412 is not a limitation of the present invention, it is desirable that they have different etch characteristics so that TEOS layer 410 may act as an etch stop. Thus, the etch is selective to the dielectric layer 412. A photoresist layer is formed on silicon nitride layer 412 and patterned with openings 414 that expose a portion of silicon nitride layer 412 over conductor 406. The remaining portion of the photoresist layer serves as a mask structure 416.

Referring now to fig. 33, the exposed portion of silicon nitride layer 412 is anisotropically etched using, for example, a reactive ion etch to expose a portion of TEOS layer 410. The etch chemistry is changed to anisotropically etch the exposed portions of TEOS layer 410, thereby exposing conductor 406. The mask structure 416 is removed. The conductor 406 is used, for example, as a wire bond pad.

Fig. 34 is a cross-sectional view of a semiconductor component 400 during fabrication according to another embodiment of the present invention. It should be noted that in addition to the photoresist layer having different patterns formed therein, the fabrication steps described with reference to fig. 22-26 are also applicable to the fabrication of the semiconductor component 400. Accordingly, the description of fig. 34 is continued from the description of fig. 26, in which reference numeral 400 is substituted for reference numeral 300 in fig. 26. It should be noted that opening 368 and mask structure 370 are not formed in the embodiment described with reference to fig. 34. According to this embodiment, layer 366 has from about 400 aTo about 2500The thickness range of (a).

Has a thickness ranging from about 1500To about 4000Is formed over the silicon nitride layer 366. Preferably, the dielectric material of layer 402 is TEOS. A photoresist layer is formed over the TEOS layer 402 and patterned to have openings 404 that expose portions of the TEOS layer 402. The remaining portion of the photoresist layer 402 serves as a masking structure 406. The portion of the TEOS layer 402 exposed by the opening 404 is anisotropically etched. The silicon nitride layer 366 serves as an etch stop layer. The masking structure 406 is removed and another photoresist layer is formed over the exposed portions of the silicon nitride layer 366 and over the TEOS layer 402. The photoresist layer is patterned to have openings that expose portions of silicon nitride layer 366 over conductors 352 and 354. The exposed portions of silicon nitride layer 366 are anisotropically etched to expose conductors 352 and 354. The photoresist layer is removed.

Referring now to fig. 35, a layer 410 of conductive material, such as aluminum, is formed over TEOS layer 402, conductors 352 and 354, and silicon nitride layer 366.

Referring now to fig. 36, aluminum layer 410 is planarized using, for example, CMP, leaving conductor 412 in contact with conductor 352, conductor 414 in contact with conductor 354, and conductor 416 over a portion of silicon nitride layer 366. A passivation layer 418 is formed over TEOS layer 402 and conductors 412, 414, and 416. Openings 422, 424, and 426 are formed in passivation layer 418 to expose conductors 412, 414, and 416, respectively. Conductor 356 serves as part of inductor 428 and also serves as a plate of capacitor 430. Inductor 416 serves as the other plate of capacitor 430.

Figure 37 is a cross-sectional view of a semiconductor component 450 during manufacture according to another embodiment of the present invention. It should be noted that in addition to the photoresist layer having different patterns formed therein, the fabrication steps described with reference to fig. 22-26 are also applicable to the fabrication of semiconductor component 450. Accordingly, the description of fig. 37 continues from the description of fig. 26, where reference numeral 300 in fig. 26 is replaced with reference numeral 450. It should be noted that the openings 368 and mask structure 370 are not formed in the embodiment described with reference to fig. 37.

Having a thickness ranging from about 1000 aTo about 5000Is formed on the silicon nitride layer 366. Preferably, the dielectric material of layer 402 is TEOS. A photoresist layer is formed over the TEOS layer 452 and patterned with openings 454 that expose portions of the TEOS layer 452. The remaining portion of the photoresist layer serves as a masking structure 456. The portion of the TEOS layer 452 exposed by the opening 452 is anisotropically etched. The silicon nitride layer 366 serves as an etch stop layer. The exposed portions of the silicon nitride layer 366 are then anisotropically etched to expose the electrodes 352, 354, and 356.

Referring now to fig. 38, mask structure 456 is removed and formed over TEOS layer 452 and over conductors 352, 354, and 356 having a thickness ranging from about 400 aTo about 2500Of the dielectric material layer. By way of example, the material for the dielectric layer is silicon nitride. A photoresist layer is formed on the silicon nitride layer and patterned to form a mask structure. The silicon nitride layer unprotected by the masking structure is anisotropically etched leaving dielectric layer 458 over conductor 356 and portions of TEOS 452 laterally adjacent conductor 356.

A layer of conductive material 460, such as aluminum, is formed over TEOS layer 452, conductors 352 and 354, and dielectric layer 458.

A photoresist layer is formed on the aluminum layer 460 and patterned to have an opening 462 that exposes a portion of the aluminum layer 460. The remaining portion of the photoresist layer serves as a masking structure 464.

Referring now to fig. 39, the exposed portion of the aluminum layer 460 is anisotropically etched to expose a portion of the TEOS layer 452. Portion 468 of aluminum layer 460 remains over silicon nitride layer 458, portion 470 remains over conductor 352, and portion 472 remains over conductor 354. Conductor 356 serves as part of inductor 482 and also serves as the plate of capacitor 484. Conductor 468 serves as the other plate of capacitor 484. Thus, conductor 356 is a conductor of a capacitor at the same vertical circuit level as the inductor, and is common to both the capacitor and the inductor. The mask structure 464 is removed.

Referring now to fig. 40, a passivation layer 474 is formed over TEOS layer 452 and conductors 470, 472 and 468. Openings 476, 478, and 480 are formed in passivation layer 418 to expose conductors 470, 472, and 468, respectively.

By now it should be appreciated that there has been provided a semiconductor component including integrated passive devices and a method of manufacturing the semiconductor component. The fabrication of integrated passive devices according to the present invention allows the use of process technologies compatible with the fabrication of high performance semiconductor devices, such as single and dual damascene process technologies. Furthermore, the density of devices fabricated in a single semiconductor chip may be increased, since the integrated passive devices are integrated in a vertical direction. Advantageously, the present invention allows for vertical integration of integrated passive devices directly on active devices without degrading the performance of the active devices. Accordingly, the present invention provides methods and structures for forming passive devices over active regions of active devices or semiconductor chips.

While certain preferred embodiments and methods have been described herein, it will be apparent from the foregoing disclosure to those skilled in the art that various changes and modifications can be made to such embodiments without departing from the spirit and scope of the invention. For example, the resistor may be fabricated in a higher level than the capacitor and inductor levels, or the resistor may be fabricated in the same level as the active device. In addition, the capacitor is not limited to the MIM structure. It is intended that the invention be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (8)

1. A method of manufacturing a semiconductor component, comprising:

providing a substrate;

forming a first passive circuit element at a first level over the substrate, wherein forming the first passive circuit element comprises forming an inductor; and

forming a second passive circuit element at a second level above the first level, the second passive circuit element having a conductor in contact with the inductor, wherein at least one of the first passive circuit element and the second passive circuit element comprises a damascene structure, and wherein the step of forming the second passive circuit element comprises forming a capacitor.

2. The method of claim 1, wherein the step of providing the substrate comprises forming a third passive circuit element from or over the substrate, and wherein:

the step of forming the third passive circuit element includes forming a resistor.

3. A method of manufacturing a semiconductor component, comprising:

providing a substrate;

forming a capacitor at a first level over the substrate;

forming a first passive circuit element at a second level below the first level, wherein a conductor of the capacitor contacts a conductor of the first passive circuit element, and wherein at least one of the capacitor or first passive circuit element comprises a damascene structure, and wherein forming the first passive circuit element at the second level below the first level comprises:

forming a first layer of dielectric material over the substrate;

forming at least one damascene opening in the first layer of dielectric material;

forming copper in the at least one damascene opening; and wherein the step of forming the capacitor comprises:

forming a first layer of conductive material over the first layer of dielectric material, the first layer of conductive material having a first portion and a second portion;

forming a second layer of dielectric material over the first layer of conductive material;

a third layer of conductive material is formed over the second layer of dielectric material.

4. The method of claim 3, wherein forming the at least one damascene opening comprises:

forming a third dielectric material layer on the first dielectric material layer;

forming a first portion of the at least one damascene opening in the first layer of dielectric material; and

forming a second portion of the at least one damascene opening in the third layer of dielectric material.

5. The method of claim 3, wherein:

the step of providing the substrate comprises forming a second passive circuit element from or over the substrate;

the step of forming the first passive circuit element comprises forming an inductor;

the step of forming the second passive circuit element includes forming a resistor; and wherein the step of forming the at least one damascene opening further comprises:

forming a third layer of dielectric material over the first layer of dielectric material;

forming a fourth layer of dielectric material over the third layer of dielectric material, wherein at least the first layer of dielectric material and the fourth layer of dielectric material are different materials than the third layer of dielectric material; and

forming the at least one damascene opening in the first, third, and fourth layers of dielectric material.

6. A method of manufacturing a semiconductor component, comprising:

providing a substrate having a resistivity in a range of 0.001 ohm-cm to 10000 ohm-cm;

forming a layer of dielectric material over the substrate;

forming an inductor using a damascene process, the inductor being formed in a first vertical plane region; and

forming a capacitor in a second vertical plane area, the capacitor having a first conductor separated from a second conductor by a layer of a second dielectric material, wherein the second vertical plane area is above the first vertical plane area.

7. A semiconductor component, comprising:

a substrate;

an inductor at a first level above the substrate;

a capacitor at a second level above the first level, wherein a portion of the capacitor is at the first level and at least one of the inductor or the capacitor comprises a damascene structure; and

the conductor of the inductor contacts the conductor of the capacitor.

8. A semiconductor component, comprising:

a first vertical circuit level and a second vertical circuit level;

a capacitor at the first vertical circuit level, wherein a portion of the capacitor is at the second vertical circuit level; and

an inductor at the second vertical circuit level, wherein the first vertical circuit level is above the second vertical circuit level and a conductor of the inductor contacts a conductor of the capacitor.