HK1194861B

HK1194861B - Semiconductor device and manufacturing method of the same

Info

Publication number: HK1194861B
Application number: HK14108103.1A
Authority: HK
Inventors: 秋叶俊彦; 木村稔; 小田切政雄
Original assignee: 瑞萨电子株式会社
Priority date: 2009-01-22
Filing date: 2014-08-07
Publication date: 2017-07-21

Description

Semiconductor device and method for manufacturing the same

The present application is a divisional application of a chinese invention patent application having an application date of 2010, 1/7, an application number of 201010002041.6, and an invention name of "semiconductor device and method for manufacturing the same".

Technical Field

The present invention relates to a structure of a semiconductor device (or a semiconductor integrated circuit device), or a technique effective for a dicing technique in a manufacturing method of a semiconductor device (or a semiconductor integrated circuit device).

Background

Japanese patent laid-open No. 2008-55519 (patent document 1) discloses a technique of cutting an optical IC structure, in which the optical IC structure is cut with a rotary blade (rotary blade) so as not to generate cracks in the structure, the structure being obtained by attaching a softer prismatic layer composed of an optical glass to an optical IC substrate composed of a harder silicon material. Specifically, according to this technique, a part of the upper prismatic layer is cut with a first blade of a large width, and then the remaining part of the upper prismatic layer and the lower optical IC substrate are cut across the full thickness with a second blade of a small width, thereby avoiding any burden on the blades.

Japanese patent laid-open No. 2007-194469 (patent document 2) and japanese patent laid-open No. 2005-191436 (patent document 3) disclose a two-step cutting technique of a semiconductor wafer, which includes forming a groove with a tapered blade (tapered blade), and then dicing the wafer with a straight blade (straight blade) having a width smaller than that of the tapered blade.

[ patent document 1]

Japanese patent laid-open No. 2008-55519

[ patent document 2]

Japanese patent laid-open No. 2007-194469

[ patent document 3]

Japanese patent laid-open publication No. 2005-191436

Disclosure of Invention

In recent years, due to ever-shrinking semiconductor processes, the thickness of an insulating layer formed between interconnect layers or interconnect design rules has become smaller and smaller. In order to prevent parasitic capacitance between interconnect layers, a material having a low dielectric constant (a low-k material, i.e., a material having a dielectric constant of 3.0 or less) has become popular as a material of an insulating layer in a multilayer interconnect.

The low-k materials contain much carbon or the like to reduce their dielectric constant, so that the strength of the materials themselves is lower than that of the materials constituting the existing insulating layer (non-low-k materials, i.e., materials having a dielectric constant exceeding 3.0). On the other hand, porous low-k materials have a structure more fragile than the material (non-porous material) constituting the insulating layer of the existing structure because there are many gaps (cavities) in the insulating layer composed of the porous low-k material.

The inventors of the present invention have found that the following problems occur when a semiconductor wafer having such a low-k material is diced with a dicing blade (so-called straight blade) having an angle (inclination angle) of about 90 ° between the side face and the face (cutting face) at the tip portion to be brought into contact with the semiconductor wafer.

When the dicing blade is in contact with the surface (main surface) of the semiconductor wafer, the entire cutting face of the dicing blade is in contact with the semiconductor wafer as shown in fig. 27. A large cutting stress is then generated in this contact region. When the dicing blade reaches the low-k layer in the state shown in fig. 28, a large cutting stress is also generated in the contact region between the low-k layer and the face at the tip portion of the dicing blade. The inventors of the present invention have thus found that cracks are generated in the brittle low-k layer due to the influence of the cutting stress.

The inventors of the present invention have also found that when the dicing blade has a side surface perpendicular to the surface (main surface) of the semiconductor wafer, a large cutting stress is also generated in the contact region between the low-k layer and the side surface of the dicing blade during the insertion of the dicing blade into the semiconductor wafer, which can easily cause cracks in the low-k layer.

Thus, when cracks occur in the low-k layer, they may even propagate into the device region adjacent to the scribe region and deteriorate the reliability of the semiconductor device.

It is to be noted that japanese patent laid-open No. 2008-55519 (patent document 1) has no specific explanation about the above-described positional relationship between the dicing blade and the low-k layer during the dicing step. Even if this technique is applied, it is difficult to suppress the generation of cracks while cutting a semiconductor wafer having a low-k layer.

In order to overcome such a problem, the inventors of the present invention studied a dicing step performed using a dicing blade (so-called chamfering blade) having a taper shape as shown in fig. 29 at a tip portion thereof.

When the dicing blade is in contact with the surface (main surface) of the semiconductor wafer, the adoption of such a structure can limit the contact between the dicing blade and the surface of the semiconductor wafer to the contact between only a part of the cutting face of the dicing blade and the surface (main surface) of the semiconductor wafer. In short, with this structure, the contact area between the dicing blade and the semiconductor wafer can be reduced. As a result, cutting stress generated when the dicing blade is inserted into the semiconductor wafer can be reduced, and cracks can be suppressed even if the dicing blade reaches the low-k layer.

However, since the wear frequency of the tip portion is high, the dicing blade as shown in fig. 29 cannot cut the semiconductor wafer to a predetermined depth. When the dicing blade with the worn tip portion and the dicing blade with the unworn tip portion are inserted to the same depth, the width cut with the former becomes greater than the width cut with the latter. Therefore, in the former case, it is frequently required to replace with a new dicing blade. As soon as the dicing blade is replaced with a new one, the conditions in the dicing apparatus (the position of the dicing blade) must be reset, which deteriorates the manufacturing TAT.

The present invention overcomes the above-mentioned problems.

An object of the present invention is to suppress the generation of cracks (improve the machinability) in a semiconductor wafer having a low-k layer.

Another object of the present invention is to ensure reliability of a semiconductor device.

It is yet another object of the present invention to improve the life of the dicing blade.

The above and other objects and novel features of the present invention will be apparent from the description and drawings herein.

The following briefly describes the gist of an exemplary invention disclosed herein.

In a method of manufacturing a semiconductor device having a multilayer interconnection layer including a low-k layer, a step-and-cut dicing process is performed on a semiconductor wafer, in which grooves are formed using a tapered blade (first dicing blade), and then the resulting grooves are divided with a straight blade (second dicing blade) thinner than the groove width. The tapered blade has a shape of a cross section in a radial direction having a multi-step tapered structure substantially symmetrical with respect to a thickness direction, wherein an inclination angle becomes larger toward a tip portion of the blade. The upper end of the first tapered surface is outside the main surface of the device when viewed from the center of rotation. The lower end of the first tapered surface is penetrated into a substrate region of the wafer or a base material layer (base material layer), and a scribe groove is formed by cutting a device. Then, the wafer is divided by cutting a dicing groove portion corresponding to a portion between a pair of the lower ends with a straight blade.

The advantages of the exemplary invention disclosed herein are briefly described as follows.

In a method of manufacturing a semiconductor device having a multilayer interconnection layer including a low-k layer, when a step-cut dicing process of forming a groove with a tapered blade (first dicing blade) and then dividing the groove with a straight blade (second dicing blade) having a blade width smaller than the width of the groove is performed on a semiconductor wafer, a portion of the multilayer interconnection layer is covered with the tapered surface and cutting is simultaneously performed, and then the wafer is divided with a blade having a small blade width and not in contact with the portion of the multilayer interconnection layer, thereby performing dicing without causing damage to the fragile low-k layer.

Drawings

Fig. 1(a), 1(b), and 1(c) are schematic views illustrating a process flow of a dicing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein fig. 1(a) is a top view of an entire wafer, fig. 1(b) is a top view of two chip regions, and fig. 1(c) is a cross-sectional view taken along line X-X' of fig. 1(b) (before being attached to a dicing tape);

fig. 2(a), 2(b), and 2(c) are schematic views illustrating a process flow of a dicing process in a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which fig. 2(a) is a top view of an entire wafer, fig. 2(b) is a top view of two chip regions, and fig. 2(c) is a cross-sectional view taken along line X-X' of fig. 2(b) (after being attached to a dicing tape);

fig. 3 is an enlarged cross-sectional view of a dotted line portion R2 (edge of chip and region between chips) of fig. 2 (c);

fig. 4(a), 4(b), and 4(c) are schematic views illustrating a process flow of a dicing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which fig. 4(a) is an overall top view of a wafer, fig. 4(b) is a top view of two chip regions, and fig. 4(c) is a cross-sectional view taken along line X-X' of fig. 4(b) (during dicing with a first blade);

fig. 5 is an enlarged sectional view of a dotted line portion R2 (edge of chip and region between chips) of fig. 4 (c);

fig. 6 is an enlarged sectional view (after dicing with a first blade) of a dotted line portion R2 (edge of chip and region between chips) of fig. 4 (c);

fig. 7(a), 7(b), and 7(c) are schematic views illustrating a process flow of a dicing process in a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which fig. 7(a) is an overall top view of a wafer, fig. 7(b) is a top view of two chip regions, and fig. 7(c) is a cross-sectional view taken along line X-X' of fig. 7(b) (during dicing with a second blade);

FIG. 8 is an enlarged cross-sectional view of the edges of the chips and the area between the chips shown in FIG. 7(c) (prior to dicing with a second blade);

FIG. 9 is an enlarged cross-sectional view of the edges of the chips and the area between the chips shown in FIG. 7(c) (after dicing with a second blade);

FIG. 10 is an enlarged cross-sectional view of the edges of the chips and the area between the chips shown in FIG. 7(c) (after being peeled from the dicing tape);

fig. 11(a) and 11(b) are schematic views illustrating a process flow of a manufacturing process in a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention, in which fig. 11(a) illustrates an upper surface of a lead frame cell region, and fig. 11(b) is a cross-sectional view taken along line a-a' of fig. 11(a) (before die bonding);

fig. 12(a) and 12(b) are schematic views showing a process flow of a manufacturing process in a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention, in which fig. 12(a) shows an upper surface of a lead frame unit region, and fig. 12(b) is a cross-sectional view taken along line a-a' of fig. 12(a) (a die bonding step);

fig. 13(a) and 13(b) are schematic views showing a process flow of a manufacturing process in a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention, in which fig. 13(a) shows an upper surface of a lead frame unit region, and fig. 13(b) is a sectional view taken along line a-a' of fig. 13(a) (a wire bonding step);

fig. 14 is an enlarged cross-sectional view of a device corresponding to the broken line portion of fig. 13 (b);

fig. 15(a) and 15(b) are schematic views showing a process flow of a manufacturing process in a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention, in which fig. 15(a) shows an upper surface of a unit device to be sealed, and fig. 15(b) shows a lower surface of the device (after completion of a sealing step and a separation step);

FIG. 16 is a cross-sectional view of the cell device taken along line A-A' of FIG. 15;

fig. 17(a) and 17(b) are schematic views showing a dicing apparatus used in a semiconductor integrated circuit device manufacturing method according to an embodiment of the present invention, in which fig. 17(a) shows a front view in a direction of a rotation axis of a spindle (spindle), and fig. 17(b) is a cross-sectional view taken along a line Y-Y' of fig. 17 (a);

FIG. 18 is a view of a particular cross-sectional configuration of the rotary blade and its edge taken along line Y-Y' of FIG. 17 (a);

fig. 19 shows a modification 1 of the dicing process ("basic dicing process") shown in fig. 1 to 10 (an embodiment using a first blade whose blade width is small);

fig. 20 shows a modification 2 (an example of cutting the polyimide coating) of the dicing process ("basic dicing process" + modification 1) shown in fig. 1 to 10;

fig. 21(a), 21(b), 21(c), 21(d), and 21(e) are cross-sectional views of a blade portion showing changes in the shape of a cross section in the radial direction of a tapered dicing blade used in the dicing processes (each dicing process) shown in fig. 1 to 10, 19, and 20, in which fig. 21(a) is a large-inclination pyramid insertion type (tip-inclination pyramid inserted type), fig. 21(b) is a tip flat type, and fig. 21(c), 21(d), and 21(e) are tip-chamfer types; wherein FIG. 21(c) is a rounded chamfer type, FIG. 21(d) is a flat chamfer type, and FIG. 21(e) is a pointed rounded chamfer type;

FIGS. 22(a) and 22(b) are cross-sectional views showing particularly preferred ranges of maximum dimension and maximum rake angle, and minimum dimension and minimum rake angle, respectively, of the insert cross-sectional configuration shown in FIG. 21 (b);

FIGS. 23(a) and 23(b) are cross-sectional views showing particularly preferred ranges of maximum dimension and maximum rake angle, and minimum dimension and minimum rake angle, respectively, of the insert cross-sectional configuration shown in FIG. 21 (a);

FIGS. 24(a) and 24(b) are cross-sectional views showing particularly preferred ranges of maximum dimension and maximum rake angle, and minimum dimension and minimum rake angle, respectively, of the insert cross-sectional configuration shown in FIG. 21 (c);

fig. 25 is a schematic view showing a relationship between a sectional structure of a tapered dicing blade used in each dicing process of the present invention and a member to be cut therewith;

fig. 26(a) is a schematic front view of a dicing step for explaining a cross-sectional structure and a dicing action of a tapered dicing blade used in each dicing process of the present invention, and fig. 26(b) is a cross-sectional view taken along line C-C' of fig. 26 (a);

fig. 27 is a referential sectional view (straight blade 1) for explaining the problem of the present invention;

fig. 28 is a referential sectional view (straight blade 2) for explaining the problem of the present invention; and

fig. 29 is a reference sectional view (tapered blade) for explaining the problem of the present invention.

Detailed Description

First, the gist of an exemplary embodiment of the invention disclosed herein is explained.

1. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface on a side opposite to the main surface; (b) inserting a first dicing blade into the semiconductor wafer from the main surface side up to the back surface side of the semiconductor wafer in a dicing area of the semiconductor wafer and moving the first dicing blade along the dicing area, thereby forming a dicing groove (or cutting the main surface) in the main surface of the semiconductor wafer; (c) after step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer and moving the second dicing blade along the dicing area, thereby dividing the semiconductor wafer into a plurality of semiconductor chips; (d) placing (fixing, mounting) the semiconductor chip (or one of them) obtained in step (c) over a chip mounting portion (e.g., die pad) of a chip mounting substrate (e.g., a lead frame or a wiring substrate) (e.g., with an adhesive); (e) after step (d), electrically coupling (via a plurality of conductive members (e.g., bond wires)) the (plurality of electrode pads of the semiconductor chip) to (a plurality of joining members (e.g., leads) of the (chip mounting substrate placed at an edge of the) chip mounting substrate; and (f) sealing the semiconductor chip (and the conductive member) with a resin, wherein the semiconductor wafer has a base material layer (silicon substrate layer), a semiconductor element layer formed over the base material layer, a first interconnect layer (low-k layer) made of, for example, copper and formed over the semiconductor element layer, and a second interconnect layer (non-low-k layer) made of, for example, copper and formed over the first interconnect layer, wherein a dielectric constant of a first insulating layer placed in the first interconnect layer (placed between a large number of interconnects) is lower than a dielectric constant of each of a pre-metal insulating layer (pre-metal insulating layer) formed in the semiconductor element layer and a second insulating layer placed in the second interconnect layer (placed between a plurality of interconnects) (the above conditions may be replaced with either of [1] a volume of an air gap formed in the first insulating layer is larger than a volume of an air gap formed in each of the pre-metal insulating layer and the second insulating layer), [2] the first insulating layer is weaker than each of the pre-metal insulating layer and the second insulating layer, [3] the first insulating layer has a heat dissipation rate lower than that of each of the pre-metal insulating layer and the second insulating layer), wherein a planar shape (taken in a thickness direction of the first dicing blade) of the first dicing blade is a circle, wherein a cross-sectional shape at a circumferential portion of the first dicing blade has a first side face, a second side face having a first side face inclination angle with respect to the first side face, and a third side face having a second side face inclination angle with respect to the first side face larger than the first side face inclination angle, wherein a width between the second side and a second boundary point of the third side is smaller than a width between the first side and a first boundary point of the second side, and wherein in step (b), the first dicing blade is inserted into the semiconductor wafer so that the second boundary point of the first dicing blade reaches the base material layer.

It is to be noted that, since the first dicing blade has a small width at its tip portion (as compared with the width of a blade such as a straight blade having a large width), when the blade is inserted into the low-k layer, the stress on the low-k layer can be reduced and thus the low-k layer can be protected from damage or cracks.

In addition, because the low-k layer is cut with the inclined second side of the first dicing blade, when the blade is inserted into (or in contact with) the low-k layer, stress on the low-k layer can be reduced (as compared to the case of a blade such as a straight blade in which the side to be in contact with the low-k layer is perpendicular to the low-k layer), and thus the low-k layer can be protected from damage or cracking.

2. The manufacturing method of a semiconductor device as described above in 1, wherein the planar shape of the second dicing blade to be used in step (c) taken in the thickness direction of the second dicing blade is a circle, wherein the cross-sectional shape of the second dicing blade at the circumference thereof has a fourth side face and a tip face, wherein the width between the fourth side face and the third boundary point of the tip face is smaller than the width between the portions of the second side face of the first dicing blade to be in contact with the semiconductor element layer, and wherein in step (c), the second dicing blade is inserted into the dicing groove so that a part of the second dicing blade reaches a dicing tape (a member for carrying a separated semiconductor chip) attached to the back surface of the semiconductor wafer before step (b).

3. The manufacturing method of a semiconductor device as described above in 1 or 2, wherein each of the device regions has a rectangular planar shape, wherein a plurality of electrode pads are formed in each of the device regions along a side thereof, and wherein in each of the device regions, a seal ring is formed between the electrode pad and the side (or between the electrode pad for product and the test pad) and along the side.

4. The manufacturing method of a semiconductor device as described in any one of above 1 to 3, wherein an insulating film (organic film) is formed in the scribe region to cover the test pad, and wherein after step (a) and before step (b), a metal layer is formed over the electrode pad formed in each device region.

5. The method for manufacturing a semiconductor device as described above in 4, wherein the metal layer is formed using electroless plating (electroetched plate).

6. The manufacturing method of the semiconductor device according to any one of above 1 to 5, wherein the test pad formed in the scribe region of the main surface of the semiconductor wafer is electrically coupled to the semiconductor element layer through the first interconnect layer and the second interconnect layer.

7. The method for manufacturing a semiconductor device as described above in 6, wherein in step (b), all the test pads are removed with the first dicing blade.

8. The method for manufacturing a semiconductor device as described above in 6, wherein in step (b), some of the test pads are removed with the first dicing blade.

9. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface on a side opposite to the main surface; (b) inserting a first dicing blade into the semiconductor wafer from the main surface side up to the back surface side of the semiconductor wafer in a dicing area of the semiconductor wafer and moving the first dicing blade along the dicing area, thereby forming a dicing groove (or cutting the main surface) in the main surface of the semiconductor wafer; (c) after step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer and moving the second dicing blade along the dicing area, thereby dividing the semiconductor wafer into a plurality of semiconductor chips; (d) placing (fixing, mounting) the semiconductor chip (or one of them) obtained in step (c) over a chip mounting portion (e.g., die pad) of a chip mounting substrate (e.g., a lead frame or a wiring substrate) (e.g., with an adhesive); (e) after step (d), electrically coupling (via a plurality of conductive members (e.g., bond wires)) the (plurality of electrode pads of the semiconductor chip) to (a plurality of joining members (e.g., leads) of the (chip mounting substrate placed at an edge of the) chip mounting substrate; and (f) sealing the semiconductor chip with a resin, wherein the semiconductor wafer has a base material layer (silicon substrate layer), a semiconductor element layer formed over the base material layer, a first interconnect layer (low-k layer) made of, for example, copper and formed over the semiconductor element layer, and a second interconnect layer (non-low-k layer) made of, for example, copper and formed over the first interconnect layer, wherein a dielectric constant of each of a first insulating layer placed in the first interconnect layer (placed between a large number of interconnects) is lower than a dielectric constant of each of a pre-metal insulating layer (pre-insulating layer) formed in the semiconductor element layer and a second insulating layer placed in the second interconnect layer (placed between a plurality of interconnects) (the above conditions may be replaced with any of [1] a volume of an air gap formed in the first insulating layer is larger than a volume of an air gap formed in each of the pre-metal insulating layer and the second insulating layer, [2] the first insulating layer is weaker than each of the pre-metal insulating layer and the second insulating layer, [3] the first insulating layer has a heat dissipation rate lower than that of each of the pre-metal insulating layer and the second insulating layer), wherein a planar shape (taken in a thickness direction of the first dicing blade) of the first dicing blade is a circle, wherein a cross-sectional shape of the first dicing blade at a circumferential portion thereof has a first face and a second face having a first side face inclination angle with respect to the first face, wherein in step (b), the first dicing blade is moved along the dicing area so that the first interconnect layers (all cutting faces of the first interconnect layers) are in contact with the second face of the first dicing blade.

10. The manufacturing method of a semiconductor device as described above in 9, wherein the planar shape of the second dicing blade to be used in step (c) taken in the thickness direction of the second dicing blade is a circle, wherein the cross-sectional shape of the second dicing blade at the circumferential portion thereof has a fourth face and a tip face, wherein the width between the fourth face and the third boundary point of the tip face is smaller than the width between the portions of the second face of the first dicing blade to be in contact with the semiconductor element layer, and wherein in step (c), the second dicing blade is inserted into the dicing groove so that a part of the second dicing blade reaches the dicing tape attached to the back surface of the semiconductor wafer before step (b).

11. The manufacturing method of a semiconductor device as described above in 9 or 10, wherein the device regions respectively have a rectangular planar shape, wherein a plurality of electrode pads are formed in each of the device regions along a side thereof, and wherein in each of the device regions, a seal ring is formed between the electrode pad and the side (or between the electrode pad for product and the test pad) and along the side.

12. The manufacturing method of a semiconductor device as described in any one of above 9 to 11, wherein an insulating film (organic film) is formed in the scribe region to cover the test pad, and wherein after step (a) and before step (b), a metal layer is formed over the electrode pad formed in each device region.

13. The method for manufacturing a semiconductor device as described above in 12, wherein the metal layer is formed using electroless plating.

14. The manufacturing method of the semiconductor device according to any one of above 9 to 13, wherein the test pad formed in the scribe region of the main surface of the semiconductor wafer is electrically coupled to the semiconductor element layer through the first interconnect layer and the second interconnect layer.

15. The method for manufacturing a semiconductor device as described above in 14, wherein in the step (b), all the test pads are removed with the first dicing blade.

16. The method for manufacturing a semiconductor device as described above in 14, wherein in the step (b), some of the test pads are removed with the first dicing blade.

17. A semiconductor device, comprising: (a) a chip mounting portion; (b) a plurality of bonding members (placed at edges of the chip mounting portion); (c) a semiconductor chip having a main surface, a plurality of electrode pads formed over the main surface, a back surface on a side opposite to the main surface, and a side surface between the main surface and the back surface, and placed over the chip mounting portion; (d) a plurality of conductive members for electrically coupling the electrode pads of the semiconductor chip to the bonding members, respectively; and (e) a sealing member for sealing a semiconductor chip (and a conductive member) (in a manner that a part of each of the bonding members (and the chip mounting portion) is exposed), wherein the semiconductor chip has a base material layer (a silicon substrate layer), a semiconductor element layer formed over the base material layer, a first interconnect layer (a low-k layer) formed (for example, made of copper) over the semiconductor element layer, and a second interconnect layer (a non-low-k layer) formed (for example, made of copper) over the first interconnect layer, wherein a dielectric constant of a first insulating layer placed in the first interconnect layer (placed between the plurality of interconnects) is lower than a dielectric constant of each of a pre-metal insulating layer formed in the semiconductor element layer and a second insulating layer placed in the second interconnect layer (placed between the plurality of interconnects) (the above conditions may be replaced with any one of the following conditions [1] a volume of an air gap formed in the first insulating layer is larger than a volume of gold A volume of an air gap formed in each of the pre-metal insulating layer and the second insulating layer, [2] the first insulating layer is more fragile than each of the pre-metal insulating layer and the second insulating layer, [3] a heat dissipation rate of the first insulating layer is lower than that of each of the pre-metal insulating layer and the second insulating layer), and wherein the side face of the semiconductor chip has a first end face exposing a part of the first interconnect layer, a second end face closer to a back surface side of the semiconductor chip than the first end face, and a third end face for connecting the first end face and the second end face.

18. The semiconductor device as recited above in 17, wherein the second end face is formed in a direction perpendicular to the back surface, wherein the third end face forms a first end face inclination angle with respect to the second end face, and wherein the first end face forms a second end face inclination angle with respect to the second end face that is smaller than the first end face inclination angle.

19. The semiconductor device as recited above in 18, wherein the first end face has an inclination of 90 °.

20. The semiconductor device as recited in any one of above 17 to 19, wherein the electrode pads are electrically coupled to the semiconductor element layer via the first interconnect layer and the second interconnect layer, respectively.

21. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface on a side opposite to the main surface; (b) inserting a first dicing blade into the semiconductor wafer from the main surface side up to the back surface side of the semiconductor wafer in a dicing area of the semiconductor wafer and moving the first dicing blade along the dicing area, thereby forming a dicing groove in the main surface of the semiconductor wafer; (c) after step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer and moving the second dicing blade along the dicing area, thereby dividing the semiconductor wafer into a plurality of semiconductor chips; (d) placing the semiconductor chip obtained in step (c) over a chip mounting portion of a chip mounting substrate; (e) after step (d), electrically coupling the semiconductor chips to the chip mounting substrates, respectively; and (f) sealing the semiconductor chip with a resin, wherein the semiconductor wafer has a base material layer, a semiconductor element layer formed over the base material layer, a first interconnect layer formed over the semiconductor element layer, and a second interconnect layer formed over the first interconnect layer, wherein a dielectric constant of a first insulating layer placed in the first interconnect layer is lower than a dielectric constant of a second insulating layer placed in the second interconnect layer, wherein the first dicing blade has a planar circular shape in which a cross-sectional shape at an edge portion thereof of the first dicing blade has a first side, a second side having a first side inclination angle with respect to the first side, and a third side having a second side inclination angle with respect to the first side which is larger than the first side inclination angle, wherein a width between second boundary points of the second side and the third side is smaller than a width between the first boundary points of the first side and the second side, wherein in step (b), the first boundary point of the first dicing blade exists outside the main surface of the semiconductor wafer and the first dicing blade is inserted into the semiconductor wafer so that the second boundary point reaches the base material layer beyond the semiconductor element layer.

22. The method for manufacturing a semiconductor device as described above in 21, wherein the planar shape of the second dicing blade to be used in step (c) taken in the thickness direction of the second dicing blade is a circle, wherein the cross-sectional shape of the second dicing blade at the circumferential portion thereof has a fourth side face and a tip face, wherein a width between the fourth side face and a third boundary point of the tip face is smaller than a width between portions of the second face of the first dicing blade to be in contact with the semiconductor element layer, and wherein in step (c), the second dicing blade is inserted into the dicing groove so that a part of the second dicing blade reaches the dicing tape attached to the back surface of the semiconductor wafer before step (b).

23. The method of manufacturing a semiconductor device as described above in 21 or 22, wherein the device regions respectively have a rectangular planar shape, wherein a plurality of electrode pads are formed in each of the device regions along a side thereof, and wherein in each of the device regions, a seal ring is formed between and along the electrode pads and the side.

24. The manufacturing method of a semiconductor device as described in any one of claims 21 to 23 above, wherein an insulating film (organic film) is formed in the scribe region to cover the test pad, and wherein after step (a) and before step (b), a metal layer is formed over the electrode pad formed in each device region.

25. The method of manufacturing a semiconductor device as described above in 24, wherein the metal layer is formed using electroless plating.

26. The manufacturing method of the semiconductor device as recited in any one of above 21 to 25, wherein the test pad formed in the scribe region of the main surface of the semiconductor wafer is electrically coupled to the semiconductor layer through the first interconnect layer and the second interconnect layer.

27. The method for manufacturing a semiconductor device as described above in 26, wherein in step (b), all the test pads are removed with the first dicing blade.

28. The method for manufacturing a semiconductor device as described above in 26, wherein in step (b), some of the test pads are removed with the first dicing blade.

29. The method for manufacturing a semiconductor device as described above in 21 to 28, wherein the second side inclination angle is about 90 °.

30. The manufacturing method of a semiconductor device according to any one of claims 21 to 29, wherein the dicing channel has an upper first chip end face and a lower third chip end face, and wherein in the step (c), the second dicing blade is inserted into and moved in the dicing channel in such a manner that a side face of the second dicing blade does not contact with the first chip end face.

31. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface on a side opposite to the main surface; (b) inserting a first dicing blade into the semiconductor wafer from the main surface side up to the back surface side of the semiconductor wafer in a dicing area of the semiconductor wafer and moving the first dicing blade along the dicing area, thereby forming a dicing groove in the main surface of the semiconductor wafer; (c) after step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer and moving the second dicing blade along the dicing area, thereby dividing the semiconductor wafer into a plurality of semiconductor chips; (d) placing the semiconductor chip obtained in step (c) over a chip mounting portion of a chip mounting substrate; (e) after step (d), electrically coupling the semiconductor chips to the chip mounting substrates, respectively; and (f) sealing the semiconductor chip with a resin, wherein the semiconductor wafer has a base material layer, a semiconductor element layer formed on the base material layer, a first interconnect layer formed on the semiconductor element layer, and a second interconnect layer formed on the first interconnect layer, wherein a dielectric constant of a first insulating layer placed in the first interconnect layer is lower than a dielectric constant of a second insulating layer placed in the second interconnect layer, wherein the first dicing blade has a circular planar shape in which a cross-sectional shape of the first dicing blade at a circumferential portion thereof has a first face and a second face having a first side inclination angle with respect to the first face, wherein in step (b), a first boundary point of the first dicing blade exists outside a main surface of the semiconductor wafer and the first dicing blade is moved along a dicing region so that the second boundary point passes through the semiconductor element layer to the base material layer, and the first interconnect layer is in contact with the second side of the first dicing blade.

32. The method for manufacturing a semiconductor device as described above in 31, wherein the planar shape of the second dicing blade to be used in step (c) taken in the thickness direction of the second dicing blade is a circle, wherein the cross-sectional shape of the second dicing blade at a circumferential portion thereof has a fourth face and a tip face, wherein a width between a fourth face and a third boundary point of the tip face is smaller than a width between portions of the second face of the first dicing blade to be in contact with the semiconductor element layer, and wherein in step (c), the second dicing blade is inserted into the dicing groove so that a part of the second dicing blade reaches the dicing tape attached to the back surface of the semiconductor wafer before step (b).

33. The method of manufacturing a semiconductor device as described above in 31 or 32, wherein the device regions respectively have a rectangular planar shape, wherein a plurality of electrode pads are formed in each of the device regions along a side thereof, and a seal ring is formed between the electrode pads and the side.

34. The manufacturing method of a semiconductor device as described in any one of above 31 to 33, wherein an insulating film (organic film) is formed in the scribe region to cover the test pad, and wherein after step (a) and before step (b), a metal layer is formed over the electrode pad formed in each device region.

35. The method of manufacturing a semiconductor device as described above in 34, wherein the metal layer is formed using electroless plating.

36. The manufacturing method of the semiconductor device as recited in any one of above 31 to 35, wherein the test pad formed in the scribe region of the main surface of the semiconductor wafer is electrically coupled to the semiconductor element layer through the first interconnect layer and the second interconnect layer.

37. The method for manufacturing a semiconductor device as described above in 36, wherein in step (b), all the test pads are removed with the first dicing blade.

38. The method for manufacturing a semiconductor device as recited in 36 above, wherein in step (b), some of the test pads are removed with the first dicing blade.

39. The method for manufacturing a semiconductor device as recited in any one of above 31 to 38, wherein the second side inclination angle is about 90 °.

40. The manufacturing method of a semiconductor device according to any one of claims 31 to 39, wherein the dicing channel has an upper first chip end face and a lower third chip end face, and wherein in the step (c), the second dicing blade is inserted into and moved in the dicing channel in such a manner that a side face of the second dicing blade does not contact with the first chip end face.

41. A semiconductor device, comprising: (a) a chip mounting portion; (b) a plurality of engaging members; (c) a semiconductor chip having a main surface, a plurality of electrode pads formed over the main surface, a back surface on a side opposite to the main surface, and a side surface between the main surface and the back surface, and being placed over the chip mounting portion, (d) a plurality of conductive members for electrically coupling the electrode pads of the semiconductor chip to the bonding members, respectively; and (e) a sealing member for sealing the semiconductor chip, wherein the semiconductor chip has (c 1) a base material layer, (c 2) a semiconductor element layer formed over the base material layer, (c 3) a first interconnect layer formed over the semiconductor element layer, and (c 4) a second interconnect layer formed over the first interconnect layer, wherein a dielectric constant of a first insulating layer placed in the first interconnect layer is lower than that of a second insulating layer placed in the second interconnect layer, and wherein a side surface of the semiconductor chip has (i) a first end surface exposing a portion of the first interconnect layer, (ii) a second end surface closer to a back surface side of the semiconductor chip than the first end surface, and (iii) a third end surface for connecting the first end surface and the second end surface, wherein the second end surface is substantially perpendicular to the back surface, the third end surface forming a first end surface inclination angle with respect to the second end surface, and the first end face forms a second end face inclination angle smaller than the first end face inclination angle with respect to the second end face.

42. The semiconductor device as recited above in 41, wherein the first end face has an inclination of 90 °.

43. The semiconductor device as described above in 41 or 42, wherein the electrode pads are electrically coupled to the semiconductor element layer via the first interconnect layer and the second interconnect layer, respectively.

44. The semiconductor device as recited in any one of above 41 to 43, wherein the second face inclination angle is 2 ° or more but not more than 20 °.

45. The semiconductor device as recited in any one of above 41 to 43, wherein the second face inclination angle is 3 ° or more but not more than 15 °.

46. The semiconductor device as recited in any one of above 41 to 43, wherein the second face inclination angle is 4 ° or more but not more than 10 °.

47. The semiconductor device as described above in any one of 41 to 46, wherein the first insulating layer has a dielectric constant of 3.0 or less.

48. The semiconductor device as recited in any one of 41 to 47 above, wherein the second insulating layer has a dielectric constant greater than 3.

49. The semiconductor device as recited in any of 41 to 48 above, wherein the first end face inclination is greater than 20 °.

50. The semiconductor device as recited in any one of above 41 to 49, wherein the first insulating layer has a dielectric constant of 3 or less and the second insulating layer has a dielectric constant greater than 3.

51. The manufacturing method of the semiconductor device as described in any one of above 1 to 40, wherein the second side face inclination angle is 2 ° or more but not more than 20 °.

52. The manufacturing method of the semiconductor device as described in any one of above 1 to 40, wherein the second side face inclination angle is 3 ° or more but not more than 15 °.

53. The manufacturing method of the semiconductor device as described in any one of above 1 to 40, wherein the second side face inclination angle is 4 ° or more but not more than 10 °.

54. The manufacturing method of the semiconductor device as described in any one of 1 to 40 above, wherein the dielectric constant of the first insulating layer is 3 or less.

55. The manufacturing method of the semiconductor device as described in any one of above 1 to 40, wherein the dielectric constant of the second insulating layer is larger than 3.

56. The method for manufacturing a semiconductor device according to any one of above 1 to 40, wherein the first side inclination angle is greater than 20 °.

57. The manufacturing method of the semiconductor device as described in any one of 1 to 40 above, wherein the dielectric constant of the first insulating layer is 3 or less and the dielectric constant of the second insulating layer is greater than 3.

58. The manufacturing method of a semiconductor device as described in any one of 1 to 40 above, wherein the insulating film is an organic insulating film.

59. The method for manufacturing a semiconductor device as described in any one of 1 to 40 above, wherein the insulating film includes a polyimide resin film as a main component thereof.

60. The manufacturing method of a semiconductor device as described in any one of 1 to 40 above, wherein a cross section in the thickness direction of a portion of the first dicing blade closer to the tip than the second boundary point extends perpendicular to a radial direction of the first dicing blade and has a flat tip face.

61. The method for manufacturing a semiconductor device as described in any one of 1 to 40 above, wherein a cross section of a portion of the first dicing blade closer to the tip than the second boundary point in the thickness direction is curved.

62. The manufacturing method of a semiconductor device as described in any one of 1 to 40 above, wherein a cross section of a portion of the first dicing blade closer to the tip than the second boundary point in the thickness direction is an isosceles triangle.

63. The manufacturing method of a semiconductor device as recited in any one of 1 to 40 above, wherein a cross section in a thickness direction of a portion of the first dicing blade closer to the tip than the second boundary point is an isosceles triangle having a chamfered vertex (leveledapees).

64. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor wafer having a main surface, a plurality of device regions formed over the main surface, a dicing region formed between the device regions, and a back surface on a side opposite to the main surface; (b) inserting a first dicing blade into the semiconductor wafer from the main surface side up to the back surface side of the semiconductor wafer in a dicing area of the semiconductor wafer and moving the first dicing blade along the dicing area, thereby forming a dicing groove in the main surface of the semiconductor wafer; (c) after step (b), inserting a second dicing blade into the dicing groove from the main surface side of the semiconductor wafer and moving the second dicing blade along the dicing area, thereby dividing the semiconductor wafer into a plurality of semiconductor chips; (d) placing the semiconductor chip obtained in step (c) over a chip mounting portion of a chip mounting substrate; (e) after step (d), electrically coupling the semiconductor chip to the chip mounting substrate; and (f) sealing the semiconductor chip with a resin, wherein the semiconductor wafer has (i) a base material layer, (ii) a semiconductor element layer formed over the base material layer, and (iii) a multilayer interconnection layer formed over the semiconductor element layer, wherein the first dicing blade has a circular planar shape in which a cross-sectional shape thereof at a circumferential portion thereof has a first side, a second side having a first-side inclination angle with respect to the first side, and a third side having a second-side inclination angle with respect to the first side that is larger than the first-side inclination angle, wherein a width between second boundary points of the second side and the third side is smaller than a width between first boundary points of the first side and the second side, and wherein in step (b), the first boundary point of the first dicing blade exists outside the main surface of the semiconductor wafer and the first dicing blade is inserted into the semiconductor wafer so that the second boundary points pass through the semiconductor element layer to reach the base substrate And (5) a material layer.

65. The method for manufacturing a semiconductor device as described above in 64, wherein the planar shape of the second dicing blade to be used in step (c) taken in the thickness direction of the second dicing blade is a circle, wherein the cross-sectional shape of the second dicing blade at the circumferential portion thereof has a fourth side face and a tip face, wherein the width between the fourth side face and the third boundary point of the tip face is smaller than the width between the portions of the first dicing blade to be in contact with the semiconductor element layer at the second side face, and wherein in step (c), the second dicing blade is inserted into the dicing groove so that a part of the second dicing blade reaches the dicing tape attached to the back surface of the semiconductor wafer before step (b).

66. The method of manufacturing a semiconductor device as described above in 64 or 65, wherein each device region has a rectangular planar shape, wherein a plurality of electrode pads are formed in each device region along a side thereof, and wherein in each device region, a seal ring is formed between and along the electrode pads and the side.

67. The method of manufacturing a semiconductor device as described above in 64 or 65, wherein an insulating film is formed in the scribe region to cover the test pad, and wherein after step (a) and before step (b), a metal layer is formed over the electrode pad formed in each device region.

68. The method of manufacturing a semiconductor device, as recited above in 67, wherein the metal layer is formed using electroless plating.

69. The manufacturing method of the semiconductor device as recited in any one of 64 to 68 above, wherein the test pad formed in the scribe region of the main surface of the semiconductor wafer is electrically coupled to the semiconductor element layer through the first interconnect layer and the second interconnect layer.

70. The method of manufacturing a semiconductor device as recited above in 69, wherein in step (b), all of the test pads are removed with the first dicing blade.

71. The method of manufacturing a semiconductor device as recited above in 69, wherein in step (b), some of the test pads are removed with a first dicing blade.

72. The method for manufacturing a semiconductor device as described above in 64 to 71, wherein the second side inclination angle is about 90 °.

73. The manufacturing method of a semiconductor device according to any one of claims 64 to 72, wherein the dicing channel has an upper first chip end face and a lower third chip end face, and wherein in the step (c), the second dicing blade is inserted into and moved in the dicing channel in such a manner that a side face of the second dicing blade does not contact with the first chip end face.

74. The method for manufacturing a semiconductor device as described in any one of above 64 to 73, wherein the second side face inclination angle is 2 ° or more but not more than 20 °.

75. The method for manufacturing a semiconductor device as described in any one of above 64 to 73, wherein the second side face inclination angle is 3 ° or more but not more than 15 °.

76. The method for manufacturing a semiconductor device as described in any one of above 64 to 73, wherein the second side face inclination angle is 4 ° or more but not more than 10 °.

77. The method for manufacturing a semiconductor device as recited in any one of above 64 to 76, wherein the first side inclination angle is greater than 20 °.

78. The manufacturing method of the semiconductor device as described in any one of above 64 to 77, wherein the insulating film is an organic insulating film.

79. The manufacturing method of a semiconductor device as described in any one of above 64 to 77, wherein the insulating film includes a polyimide resin film as a main component thereof.

80. The method for manufacturing a semiconductor device as described in any one of 64 to 79 above, wherein a cross section in the thickness direction of a portion of the first dicing blade closer to the tip than the second boundary point extends perpendicular to a radial direction of the first dicing blade and has a flat tip face.

81. The method for manufacturing a semiconductor device as described in any one of above 64 to 79, wherein a cross section of a portion of the first dicing blade closer to the tip than the second boundary point in the thickness direction is curved.

82. The manufacturing method of a semiconductor device as described in any one of above 64 to 79, wherein a cross section of a portion of the first dicing blade closer to the tip than the second boundary point in the thickness direction is an isosceles triangle.

83. The manufacturing method of a semiconductor device as described in any one of above 64 to 79, wherein a cross section in the thickness direction of a portion of the first dicing blade closer to the tip than the second boundary point is an isosceles triangle having a chamfered vertex.

Description of modes of description, basic terms, and usage thereof in the present application 1 in the present invention, description in the embodiments may be made after being divided into a plurality of parts for convenience. Unless otherwise specified, the parts are not independent of each other, but may each be part of a single embodiment or part of a detail or modification of another part or whole. In principle, descriptions of parts similar to the foregoing parts are not repeated. In addition, when referring to elements of the embodiments, they are not necessary unless specifically stated, limited theoretically, or otherwise apparent from the context.

2. With respect to any material, any component, etc. in the description of the embodiments, the term "X made of a" or the like does not exclude that X has an element other than a as one of its main constituents, unless specifically indicated or otherwise evident from the context.

For example, the term "X made of a" means "X has a as its main constituent. Of course, for example, the term "silicon member" is not limited to a member made of pure silicon, but may be a member containing a SiGe alloy, other multi-element alloy including silicon as a main component, or an additive or the like.

Similarly, the terms "copper interconnect", "aluminum interconnect" and the like are not limited to pure copper interconnects, pure aluminum interconnects or the like, but refer to copper-based interconnects, aluminum-based interconnects or the like. The same applies to the terms "polyimide film", "gold plating", etc.

Similarly, of course, the term "silicon oxide film" refers not only to a relatively pure undoped silicon dioxide film, but also to a thermally oxidized film such as an FSG (fluorosilicate glass) film, a TEOS-based silicon oxide film, an SiOC (silicon oxycarbide) film, a carbon-doped silicon oxide film, an OSG (organosilicate glass) film, a PSG (phosphosilicate glass) film, or a BPSG (borophosphosilicate glass) film; a CVD oxide film; a coating type silicon oxide film such as an SOG (spin on glass) film or an NSC (nano-clustered silicon dioxide) film; a silicon oxide-based low-k insulating film (porous insulating film) obtained by introducing pores into a similar member; and a composite film between such a film as a main constituent element and another silicon-based insulating film.

3. Preferred embodiments of shapes, positions, and attributes and the like will be described, however, it is to be understood that shapes, positions, attributes and the like are not strictly limited to the preferred embodiments unless specifically indicated or otherwise evident from the context.

4. When a particular number or amount is recited, the number or amount may be greater or less than the particular number or amount unless specifically stated, theoretically limited by the particular number or amount, or otherwise apparent from the context.

5. The term "wafer" generally refers to a single crystal silicon wafer upon which semiconductor devices (which may be semiconductor integrated circuit devices or electronic devices) are to be formed. However, it includes, of course, a composite wafer composed of a semiconductor layer and an insulating substrate, such as an epitaxial wafer, an SOI substrate, or an LCD glass substrate.

6. The term "low-k insulating film" may generally refer to an insulating film having a lower dielectric constant than, for example, a non-porous plasma TEOS silicon oxide film. However, in the present invention, according to the conventional practice in the semiconductor field, an insulating film having a dielectric constant of 3 or less is referred to as a "low-k insulating film", and an insulating film having a dielectric constant exceeding 3 is referred to as a "non-low-k insulating film". Reducing the dielectric constant to 3 or less generally requires either the inclusion of a sufficient amount of carbon in the material composition or the introduction of micro-sized pores or macro-sized air gaps into the material structure, but this degrades the material strength or structural strength. Therefore, in the present invention, the FSG (fluorosilicate glass) film belongs to the non-low-k insulating film (k ═ about 3.4).

Typical examples of the "low-k insulating film" include silicon/glass type CVD insulating films such as SiOC (silicon oxycarbide), carbon-doped silicon oxide film, and OSG (organosilicate glass) film; an SSQ (silsesquioxane) -based silicon/glass type coating insulating film (or SOG), such as HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), and PSQ (phenyl silsesquioxane); heat-resistant polymer resins (including copolymers with siloxane and the like), such as polyimide-based organic resins and BCB (benzocyclobutene); and porous insulating films obtained by introducing microscopic-sized pores or macroscopic air gaps (cavities) into the materials of the above-described examples, i.e., "non-low-k insulating film" materials. These materials can certainly be used in embodiments of the present invention.

Of course, the term "low-k interconnect layer" or the like rarely means that the entire portion of the insulating film in the interconnect portion is made of a low-k insulating film, it means that the main portion of the insulating film (interlayer insulating film, intralayer insulating film) is made of a low-k insulating film. It should be noted that the main insulating film of the interconnect layer may be simply referred to as "interlayer insulating film" without distinguishing between interlayer and interlayer insulating films.

The multi-layered interconnect layer is composed of a low-k interconnect layer and/or a non-low-k interconnect layer, and each of the low-k interconnect layer and the non-low-k interconnect layer generally includes a plurality of interconnect layers (generally about two to ten layers).

7. The term "annular (circular ring shape)" refers not only to a geometric circle or a circular ring, but also to a rectangular ring or other ring shapes according to the actual situation. In addition, it is not always limited to closed loops in a strict sense.

In addition, the term "hub-shaped (hub-shaped) dicing blade" does not mean a disc shape in a strict sense but means a circular ring shape. When referring to the edge or circumferential portion of the dicing blade, the term "circular" is used only to ensure simplicity.

Details of the embodiment is explained more specifically below. In all the drawings, the same or similar components will be identified by the same or similar symbols or reference numerals, and repetitive description will be omitted in principle.

1. Description on the outline of each embodiment of the present invention (mainly from fig. 25 to fig. 29).

In recent years, due to ever shrinking semiconductor processes, interconnect design rules or the thickness of interconnect layers have become smaller and smaller. To meet this trend, low-k materials are used as materials for insulating layers in multilayer interconnects.

However, the strength of low-k materials is low. As shown in fig. 27 and 28, when they are cut with a straight blade, the contact area between the blade and the wafer becomes large, and cutting stress is generated at the contact surface. Therefore, cracks are likely to occur in low-k materials of low strength. As is apparent from fig. 27 and 28, when the wafer 1 is cut with the straight blade 51b from the device surface side 1a (the surface opposite to the back surface 1 b), the contact area 114 between the wafer and the tip portion of the blade is large. This may cause deterioration in reliability of the semiconductor device.

The inventors of the present invention have thus studied and found that this crack problem can be suppressed by employing a step-cutting operation, i.e., first forming a scribe groove on the wafer surface with a tapered blade (first blade) and then performing full cutting with a straight blade (second blade) having a smaller blade thickness than that of the tapered blade. However, as shown in fig. 29, using an existing wide-angle tapered blade (first blade) having a cross-sectional apex angle of 60 ° to 90 ° in the radial direction (30 ° to 45 ° in terms of an inclination angle between the tapered surface and the main surface of the wafer) makes it possible to reduce the contact area 114 between the wafer and the tip portion of the blade, but increases the wear frequency of the tip portion (in addition to the short tip portion length), resulting in such a problem that the replacement frequency increases.

In one embodiment of the present invention, in the dicing step of the wafer, first, a cutting groove reaching the semiconductor substrate is formed from the device surface side of the wafer with a narrow-angle tapered blade having a complementary angle of inclination of 70 ° or more but not more than 88 ° (a cross-sectional apex angle of about 4 ° to 40 °, in terms of inclination, from about 2 ° to 20 °), and then, the bottom of the groove is completely cut with a straight blade having a width smaller than the width of the cutting groove. This enables the blade life to be extended because the width of the tapered portion of the tapered blade can be made larger.

However, the narrow angle tapered dicing blade has a disadvantage in that when the tip portion of the dicing blade is narrow, it wears quickly, which makes it difficult to control the height of the blade. This problem can be overcome by using a first dicing blade having a two-step taper (including a shape in which a tip portion is removed) as will be described later in section 2. The use of such blades is effective regardless of the rake angle range. However, it is more effective to use it in combination with a small angle tapered blade because the length of the tip portion can be increased. The gist of which will be explained later.

Fig. 25 (corresponding to the Y-Y' section of the circumferential portion R4 of the dicing blade shown in fig. 26 (a)) is a sectional view in the radial direction of the circumferential portion of the tapered dicing blade 51a to be used in the first cutting step of the two-step dicing process in the manufacturing method of a semiconductor device according to an embodiment of the present invention (including a sheet-like member such as a semiconductor wafer to be diced). Fig. 26(a) and 26(b) (26 (a) is an overall schematic sectional view and 26(b) is a C-C' sectional view of a circumferential portion R4 of the dicing blade shown in fig. 26 (a)) are process views for explaining a principle of forming a groove using a tapered dicing blade 51a to be used in the first cutting step of the two-step dicing process in the semiconductor device manufacturing method according to one embodiment of the present invention. As shown in fig. 25 or 26, the dicing blade is composed of a flat inner ring portion 101 having a flat first side face 104 (the inclination angle complement angle θ 1 of the inner ring side face is, for example, 90 °), an outer ring portion 102 located below the inner ring portion and having an inclined second side face 105 (the inclination angle complement angle θ 2 of the outer ring side face is, for example, 83 °, which means that the inclination angle θ 2 of the outer ring side face is 7 °), and an outer edge portion 103 located below the outer ring portion and having an inclined third side face 106 (the inclination angle complement angle θ 3 of the outer edge side face is, for example, 45 °, means that the inclination angle θ 3 of the outer edge side face is 45 °). In the figure, a distance between first boundary points P and P 'as transition points from the flat first side 104 to the inclined second side 105 is designated as a first boundary point width T1, and a distance between second boundary points Q and Q' as transition points from the second side 105 to the third side 106 is designated as a second boundary point width T2.

As can be seen from fig. 25, a single-stage tapered blade having a tip portion like QVQ' is narrow at its tip portion, so that blade wear is severe during cutting and variation in height of the blade edge is inevitable. On the other hand, the two-step tapered dicing blade 51a shown in solid lines has a wider tip portion (the outer edge portion 103 and a portion of the outer ring portion 102 near the tip) so that abrasion of the dicing blade can be suppressed. As a result, the blade height does not need to be frequently adjusted or can be easily adjusted. When a narrow-angle tapered blade is used, the life thereof can be made considerably long due to the large width between P and Q, and even if the outer cloth edge portion 103 disappears due to wear, a part of the outer ring portion 102 near the tip end becomes a new outer edge portion 103.

In addition, as shown in fig. 25, only the outer ring side surface 105 (second side surface) of the cutting portion 111 (portion inserted into the wafer from the cutting face 112 of the wafer) of the tapered dicing blade 51a is in contact with the weaker low-k interconnect layer 8 (first interconnect layer). In addition, in the cross-section of fig. 26(a) and 26(b) near the relief point (escapepoint) 62 of the blade where chipping occurs most frequently, there is a space between the side wall surface of the dicing groove 21 and the outer ring side surface 105 (second side surface) of the tapered dicing blade 51a because the blade is tapered. This structure makes it possible to greatly suppress the generation of debris. This effect is independent of whether or not the low-k interconnect layer 8 is present, but is significant when the low-k interconnect layer 8 is present.

As will be described later on the basis of fig. 8 and the like, in the second step, the small-width straight blade 51b (second dicing blade) having a blade thickness smaller than the second boundary point width T2 enters into a part of the dicing groove 21 formed in the first step between the pair of second boundary points Q and Q' so that the side face of the straight blade 51b does not contact the exposed surface of the low-k interconnect layer 8 (first interconnect layer). This also greatly suppresses the occurrence of cracks. Chipping (cracking) hardly occurs unless the dicing blade is in contact with the fragile low-k interconnect layer 8, and therefore it is only necessary that the width T3 of the second dicing blade 51b be at least smaller than the width T4 of a portion of the second side (or second face) of the first dicing blade (tapered dicing blade) to be in contact with the semiconductor element layer 14 (or the thickness of the corresponding portion of the dicing blade). However, there is a fear that misalignment of the cutting position may be caused by the rotational operation and the contact stress with the semiconductor wafer 1 because the semiconductor wafer 1 is cut with the rotary dicing blade in the dicing step. In view of such misalignment, it is preferable that the width T3 of the second dicing blade 51b is smaller than the width T2 between the second boundary points, as described above.

2. A dicing process in the semiconductor wafer manufacturing method according to one embodiment of the present invention (mainly, from fig. 1(a) to fig. 10) is explained below.

First, in this section, a preparation step for dicing is explained. As described in fig. 1(a) to 1(c) (in particular, fig. 1 (a)), it is necessary to prepare a semiconductor wafer 1 whose wafer stage has almost been completed. The wafer 1 is, for example, a p-type single crystal silicon substrate 1p having a diameter of about 300 Φ (may be 200 Φ or 450 Φ), and has many chip regions 2 on a device surface (main surface) 1a thereof. Two of these chip regions, R1, are shown in FIGS. 1(a) through 1(c) (specifically, FIG. 1(b) and FIG. 1(c) showing an X-X' cross-section thereof). Most of the device surface 1a (the surface opposite to the back surface 1 b) except for portions such as pad openings (padapending) and dicing areas (scribe region) is covered with a final passivation film 3 (e.g., a lower inorganic insulating film and an upper photosensitive polyimide organic resin film). Electrode pads 4 (bonding pads) of the product region 2 and test electrode pads 5 of the dicing region 6 are formed corresponding to these openings. Near the edge of the product area 2 a sealing ring 18 is placed around. These electrode pads are typically formed as an aluminum (or may be copper) interconnect layer or pad layer. The wafer 1 has, over its substrate region, a multilayer interconnect layer 10 having a low-k interconnect layer 8 (first interconnect layer) using, for example, an SiOC film (k is about 2.6) or the like as a lower portion of an interlayer insulating film 8i (first insulating film), and a non-low-k insulating layer 7 (second interconnect layer) using, for example, a plasma TEOS silicon oxide film (k is about 4.1) as an upper portion of an interlayer insulating film 7i (second insulating film). Each interconnect layer is comprised of a copper type (which may also be silver) damascene interconnect or a conventional aluminum type (which may also include tungsten plugs, etc.) interconnect or a combination thereof. In the present embodiment, the electrode pads 4 which have a rectangular planar shape (a square planar shape in the present embodiment) and are placed along each side of the product region 2; they may be placed in row(s) in the product area 2 and may be placed along one side edge of the product area 2 in the central portion of the product area 2; or may be concentrated on one side of the product region 2.

Next, as shown in fig. 2, the back surface 1b of the wafer 1 is attached to a dicing tape 11 and then fixed to a dicing frame (dicing frame) or the like. Details of the region R2 around and between the chips will be described in detail next with reference to fig. 3. As shown in fig. 3, the wafer 1 has a semiconductor element layer 14 (including a well, a silicon substrate surface, a gate electrode, a metal front layer, and the like) on its base material layer 1 p. In the region L1 between the seal rings, the scribe line region 6 is provided between a pair of chip margin regions (chipping margin regions) 17. The scribe line region 6 has a TEG test pad opening 15 in the inside thereof. The interconnects in the multilayer interconnect layer 10 constitute a seal ring 18 and a TEG test interconnect 19. In the present embodiment, the back surface 1b of the wafer 1 is attached to the dicing tape 11 after the preparation of the semiconductor wafer 1, but before the attachment to the dicing tape 11, a redistribution layer (redistribution layer) may be formed on the device surface (main surface) 1a of the semiconductor wafer 1 to change the position of the electrode pad 4.

Next, a cutting step using the tapered insert 51a as a first cutting step will be described with reference to fig. 4(a) to 4 (c). As shown in fig. 4(a) to 4(c), the wafer is cut (half-cut as a first step of two-step cutting) in each direction of X and Y along a scribe line (straight line region where scribe regions join together) to form a scribe groove 21a at the side of the device surface 1a of the wafer 1. The details of the cross section will be explained based on fig. 5. The sectional structure of the tapered dicing blade 51a (first dicing blade) at its circumferential portion is substantially line-symmetrical with respect to the center line in the thickness direction. It has the structure: from the rotation center, there are provided a flat inner ring portion 101, an outer ring portion 102 having a side surface inclined, an outer rim portion 103 having a side surface inclined more, and the like. A pair of such two slope changing points (inflection points) are referred to as first boundary points P and P '(between the flat inner ring portion 101 and the outer ring portion 102) and second boundary points Q and Q' (between the outer ring portion 102 and the outer rim portion 103), respectively. The distance between the first boundary points P and P 'is referred to as a first boundary point width T1, and the distance between the second boundary points Q and Q' is referred to as a second boundary point width T2. The following relationship is evident between them: t1> T2. The cutting result with the taper dicing blade 51a of fig. 5 is shown in fig. 6.

As shown in fig. 6, the scribe groove 21a has a steep first chip end surface 205 (groove side surface), a gentle third chip end surface 206 (groove bottom surface), and the like in correspondence with the two-step taper.

Next, a cutting step as a second step of dicing with the straight blade 51b will be described with reference to fig. 7(a) to 7 (c). As shown in fig. 7(a) to 7(c), the wafer is cut along the dicing groove 21a in each direction of X and Y (cutting as the second step of two-step cutting), and the dicing groove 21a on the device surface 1a of the wafer 1 extends into the dicing tape 11 attached to the back surface 1 b. The cross section will be specifically described next with reference to fig. 8. As shown in fig. 8, the thickness T3 of the straight blade 51b (the distance between the third boundary points S and S', i.e., the third boundary point width T3) is smaller than the second boundary point width T2 of the tapered dicing blade 51a so that the straight blade 51b cuts only the third chip end face 206 of the dicing groove 21 a. There is no small device structure in this region, so dicing can be performed without damaging the device. In addition, this portion is made of single crystal silicon and is therefore relatively hard and strong, so that the frequency of occurrence of chipping is low. In this embodiment, the straight blade 51b has a flat tip face (tip face) 110 as its tip portion. The tip portion does not have to have a flat surface per se, but such a flat surface can be easily manufactured. Therefore, it may have a shape similar to the tapered dicing blade 51a (refer to fig. 21(a) to 21 (e)). What is important is the relative thickness relationship between the two blades described above. The cutting results using the straight blade 51b are shown in fig. 9.

As shown in fig. 9, the second scribe groove 21b is newly formed, and thus, the vertical face 207 (second chip end face) of the chip 2 is formed. In addition, the chip side wall portion 209 is also composed of a steep first chip end surface 205 (groove side surface), a gentle third chip end surface 206 (groove bottom surface), and the like.

As shown in fig. 10, the dicing tape 11 is then peeled off, whereby a large number of individual chips 2 appear. In practice, the chip 2 is picked up from the dicing tape 11, and then die bonding described in section 3 below is performed.

3. Description is made regarding an assembly process or the like (mainly, from fig. 11(a) to fig. 16) in the manufacturing method of the semiconductor device described in each embodiment of the present invention.

In this section, an example of an assembly process after the dicing step described in each section will be described.

First, a chip mounting substrate 31 (only a unit device region is shown) is shown in fig. 11(a) and 11(b) (fig. 11(a) shows an upper surface, and fig. 11(b) shows an a-a' cross section). This figure shows an example of a lead frame, but an organic multilayer interconnect substrate or other interconnect substrate may be used instead. As shown in fig. 11(a) and 11(b), the chip mounting substrate 31 has a die pad portion 32 (chip mounting portion) at a central portion thereof. The die pad portion 32 is fixed in four directions by suspending leads (suspending leads) 33. A number of outer lead portions 34 (bonding members) extend at the outer periphery of the die pad portion 32.

Then, the chip 2 in the state shown in fig. 9 is picked up and die-bonded onto the die pad portion 32 as shown in fig. 12(a) and 12 (b). Then, as shown in fig. 13(a) and 13(b), the external lead portion 34 and the electrode pad 4 on the upper surface of the chip 2 are subjected to, for example, ball-wedge bonding using a bonding wire 35 (conductive member).

Fig. 14 is an enlarged view of the chip end portion R3 of fig. 13(a) and 13 (b). As shown in fig. 14, the first chip end face 205 is inclined at a second end face inclination angle Σ 2 with respect to the vertical face 207. The third chip end face 206 is inclined with respect to the vertical face 207 at a first end face inclination angle Σ 1 larger than the second end face inclination angle Σ 2.

Then, as shown in fig. 15(a) and 15(b), the lead frames 31 are separated from each other and each becomes a resin sealing portion 36 (individual device). The resulting device has a cross-sectional shape as shown in fig. 16.

4. Description is made regarding a dicing apparatus or the like used in the manufacturing method of a semiconductor device described in each embodiment of the present invention (mainly, fig. 17(a) to 18).

In this section, a dicing apparatus and the like to be used in each embodiment are explained. As shown in fig. 17(a) and 17(b), the dicing apparatus has a suction table (wafer stage) 54, and the wafer 1 adhered and fixed to the ring frame 55 by the dicing tape is vacuum-sucked onto the suction table. In this state, with the blade holding portion 52, the dicing blade 51 is attached to the tip end portion 58 of the spindle 57 held by the spindle holding portion 56, and is rotated at high speed to perform cutting. At this time, the stage 54 is moved in a horizontal direction to perform cutting so as to form the scribe groove 21. During the cutting, pure water or a coolant for cooling or cleaning is supplied from a cooling water supply arm nozzle 59, a pure water sprayer (spray) 60, a pure water sprayer (shower) 61, or the like. In the present invention, the term "cross section of the blade in the radial direction" (or simply, the cross-sectional shape of the blade) refers to the Y-Y' cross section of fig. 17(a), unless otherwise specified.

The blade shown in fig. 17(a) and 17(b) is of an assembled type. A hub type blade that is now in popular use is shown in fig. 18. In the hub type blade, the blade holding portion 52 has a spindle attaching portion 53 at a central portion thereof, and the dicing blade 51 is integrated as one body. In this case, the dicing blade 51 itself is not a disk type but a circular ring shape.

Each member has standard dimensions as shown in this figure. Of course, members having other dimensions may also be used.

5. Description is made with respect to a dicing process (modification 1: taper thin blade system) and the like in the manufacturing method of a semiconductor device according to another embodiment of the present invention (mainly, fig. 19).

In the present embodiment, in the first step of section 2, only some of the TEG test pads 5 (test pads or electrode pads) are cut and removed. Fig. 19 is a sectional view in which fig. 5 and 8 of section 2 overlap each other. In this example, in contrast to fig. 5, the non-device region 6 (scribe region) is greater than the thickness T1 (first boundary point width) of the flat inner ring portion of the tapered dicing blade.

In the existing dicing step, almost all the TEG test pads 5 are removed to prevent leakage of test mechanics (testknock-how) or to prevent dust from being generated in the subsequent steps. However, this easily enlarges the dicing area. The enlargement of the dicing area leads to a considerable reduction in the number of available chips, and therefore this must be avoided as much as possible. In a SIP (system in package) type product, the size of the dicing area is often set in advance to a small value for design convenience. In addition, it is difficult to narrow the chip margin in consideration of its intended use. In order to meet the above object, the best method is to remove all the TEG test pads 5 as in another embodiment of the present invention, but if not, it is effective to reduce the thickness of the first-step blade as in the present embodiment.

When only the main TEG test pads 5 are removed as in the present embodiment, the width of the dicing area can be reduced because they can be removed with a blade of a small width (a blade for the first cutting). Such a system is also effective for preventing leakage of test skills and suppressing generation of dust in subsequent steps because the main TEG test pad 5 is removed.

6. Description is made with respect to a dicing process (modification 2: polyimide coating system) and the like in the manufacturing method of a semiconductor device according to still another embodiment of the present invention (mainly, fig. 20).

This example is a modification of the device structure described in sections 2 and 5. In a device having a rewiring structure such as a wafer level package or a device having bump electrodes (bump electrodes), it is necessary to pattern an upper final passivation film 12 (e.g., a photosensitive polyimide type organic resin film) over a lower final passivation film 3 and then form a plating layer (metal layer) over the electrode pads 4 in the product area by electroplating or electroless plating (electroless plating or the like is intended to be used). However, in the plating, a plating layer is also unnecessarily formed on the electrode pad 5 in the scribe region, or the electrode pad 5 is corroded by an acid for pretreatment. To prevent such a problem, the electrode pads 5 of the dicing area are often covered with an organic protective film such as a polyimide film formed in the same layer as the final passivation film 12 on the upper portion. However, when such an organic resin film and a hard silicon member are mechanically diced at the same time, an additional burden may be imposed on the rotary blade, resulting in frequent generation of chips (also in the case where the low-k interconnect layer 8 is absent).

In this case, the dicing method as described in section 1 or section 5 is effective. As described in connection with fig. 26(a) and 26(b), even if the blade is slightly misaligned due to an extra burden, its influence on the side wall of the dicing groove can be suppressed because there is a space between the side wall of the dicing groove and the side face of the blade in the vicinity of the relief point where chipping is most likely to occur.

7. Description is made regarding a cross-sectional structure of a dicing blade that can be used in a dicing apparatus to be used in the manufacturing method of a semiconductor device according to each embodiment of the present invention (mainly, from fig. 21(a) to fig. 24 (b)).

In the above sections, a tapered dicing blade having a two-step taper shape to be used for the first step is mainly described in detail. In this section, on the other hand, the change in the sectional shape of the blade circumferential portion R4 (fig. 18) will be specifically described.

As shown in fig. 21(a) to 21(e), the sectional shape of the blade circumferential portion R4 (fig. 18) in each embodiment of the present invention can be roughly classified into five types in terms of form. The insert shown in fig. 21(a) has the basic cross-sectional shape described in section 2, in which a flat inner ring portion 101 (corresponding to an inner ring portion side 104 or a first side) has a trapezoidal outer ring portion 102 (corresponding to an outer ring side 105 or a second side) below it, and an isosceles triangular outer edge portion 103 (corresponding to an outer ring side 106 or a third side) below it. The insert shown in fig. 21(b) (of the non-pointed type) has a sectional shape similar to that of the insert of fig. 21(a), except that the outer edge portion 103 of the isosceles triangle is replaced with a flat tip face 108. Each of the other blades has a sectional shape similar to the basic shape except that the outer edge portion 103 of the isosceles triangle is modified. Fig. 21(c) is a sectional shape having a gentle curve instead of an isosceles triangle (arc tip type); fig. 21(d) is a sectional shape in which a portion near the apex of the isosceles triangle is linearly chamfered (outer-end chamfered portion 107); fig. 21(e) is a sectional shape in which a portion near the isosceles triangle is spherically chamfered (outer-end chamfered portion 107).

With respect to the test inserts of each embodiment manufactured and evaluated under various conditions by the inventors of the present invention, preferable ranges of angles and dimensions of the sectional shape of the insert circumferential portion R4 are explained below with reference to fig. 22(a) to 24 (b). In these figures, the dimensions are expressed in units of mm, while the angles are expressed in units of °. In these figures, (a) of each figure represents an optimum maximum complementary angle of inclination (a maximum complementary angle of inclination actually available under normal conditions) and an optimum maximum width of the outer ring portion. The (b) diagram in each figure represents the optimum minimum complementary angle of the inclination angle (the minimum complementary angle of the inclination angle actually available under normal conditions) and the optimum minimum width of the outer ring portion. The internal angle at the vertex in fig. 23(a) and 23(b) is preferably 50 ° to 180 ° (equal to that in fig. 22(a) and 22 (b)). An example of 75 ° to 87 ° can thus be given as a practical range of complementary angles of inclination angles of the outer ring portion side face under normal conditions. This means that the inclination angle theta 2 (first flank inclination angle) of the side of the outer ring portion is 3 deg. to 15 deg.. Examples of 70 ° to 88 ° can be given as the actual range of the complementary angle of the inclination angle Θ 2 of the outer ring portion side under normal conditions, allowing sufficient mechanical precision. This means that the inclination angle theta 2 (first flank inclination angle) of the side of the outer ring portion is 2 deg. to 20 deg.. In the case where reliability is particularly required, an example of 80 ° to 86 ° can be given as a practical range of the complementary angle of the inclination angle Θ 2 of the outer ring portion side face under normal conditions. This means that the inclination angle theta 2 (first flank inclination angle) of the side of the outer ring portion is 4 deg. to 10 deg..

8. Overview

The invention proposed by the inventors of the present invention has been described above in detail. It should be borne in mind, however, that the present invention is not so limited, but can be modified without departing from the scope of the invention.

For example, in the above embodiments, the specific explanation is made on the premise of the conventional dicing step to be performed after the back surface grinding. However, the present invention is not limited thereto, and of course, the present invention may be applied to DBG (pre-grinding dicing) that performs dicing prior to back surface grinding. In this case, half cutting is performed using the second cutting instead of full cutting.

In the above embodiments, the invention is used for an interconnect structure using aluminum-based conventional interconnects or copper-based damascene interconnects. Of course, the present invention may be applied not only to these cases, but also to the use of silver-based damascene interconnects or other types of interconnect structures.

Claims

1. A semiconductor device, comprising:

(a) a chip mounting portion;

(b) a plurality of engaging members;

(c) a semiconductor chip having a main surface, a plurality of electrode pads formed on the main surface, a back surface opposite to the main surface, and a side surface between the main surface and the back surface, and mounted on the chip mounting portion;

(d) a plurality of conductive members for electrically coupling the electrode pads of the semiconductor chip to the bonding members, respectively; and

(e) a sealing member sealing the semiconductor chip,

wherein the semiconductor chip has a base material layer, a semiconductor element layer formed on the base material layer, a first interconnection layer formed on the semiconductor element layer, and a second interconnection layer formed on the first interconnection layer,

the first insulating layer disposed in the first interconnect layer has a dielectric constant lower than that of each of the pre-metal insulating layer formed in the semiconductor element layer and the second insulating layer disposed in the second interconnect layer,

the side face of the semiconductor chip has a first end face exposing a part of the first interconnect layer, a second end face closer to a back surface side of the semiconductor chip than the first end face, and a third end face between the first end face and the second end face,

a first inclination angle formed by the first end face with respect to the back surface is smaller than a second inclination angle formed by the second end face with respect to the back surface and larger than a third inclination angle formed by the third end face with respect to the back surface, and

each of the first inclination angle, the second inclination angle, and the third inclination angle is an angle of not more than 90 °.

2. The semiconductor device according to claim 1, wherein the second end face is formed in a direction perpendicular to the back surface.

3. The semiconductor device according to claim 2, wherein the second inclination angle is 90 °.

4. The semiconductor device of claim 3, wherein the electrode pads are electrically coupled to the semiconductor element layer via a first interconnect layer and a second interconnect layer, respectively.