GB2034992A - Analog-to-digital converter - Google Patents

Abstract

An analog-to-digital converter is supervised by a microprocessor 16 and includes means for digitally compensating for initial gain and offset errors and gain and offset drift errors due to temperature variations. An analog input voltage is applied to the analog-to-digital converter 4, the output of which is both stored in the microprocessor 16 and applied to a linear digital-to-analog converter 6. The output of the linear converter is summed with the original analog input voltage and the difference applied to the analog-to-digital converter as an unknown input signal. This process is continued to achieve a desired resolution. The output of a differential temperature sensor 14 is similarly processed to determine the proper amount of compensation for gain and offset drift. The microprocessor provides both control and computation capabilities. <IMAGE>

Description

SPECIFICATION Analog-to-digital converter This invention relates generally to analog-todigital converters, and, more particularly to a microprocessor supervised analog-to-digital converter.

The use of a recirculating remainder technique to perform analog-to-digital conversion is well known.

However, it has been necessary to provide special calculators or, in the alternative, a large amount of complex logic circuitry to perform the required computations associated with the recirculating remainder technique.

An additional disadvantage of known analog-todigital converters employing the recirculating remainder technique resides in the use of analog devices to compensate for gain and offset drift which occurs as a result of temperature variations.

It is an object of the present invention to provide an analog-to-digital converter which is highlyaccu- rate.

In subsidiary features the invention provides a high-speed analog-to-digital converter which is supervised by a microprocessor which also provides computing power and which employs digital means for cancelling the effects of drift due to temperature variations.

According to a broad aspect of the invention there is provided a microprocessor supervised analog-todigital converter implemented to perform a recirculating remainder conversion of an analog input signal, comprising first means for performing a first conversion of said analog input signal into a digital representation; second means coupled to said first means for comparing said digital representation with said analog input signal to produce a remainder signal corresponding to the difference; third means for substituting said remainder signal for said analog input signal to produce a second conversion resulting in the production of a second digital representation and a second remainder signal; and microprocessing means coupled to said first means and said third means for controlling the number of conversions each of which produces a remainder signal and a consequent digital representation thereof, for storing said digital representations and computing therefrom a digital output corresponding to said analog input voltage.

According to a further aspect of the invention there is provided a method of converting an analog input voltage into a digital output, comprising applying said analog input voltage to a first analog-todigital converter to obtain a digital representation thereof; converting said digital representation into an analog voltage; comparing said analog voltage with said analog input signal; generating a remainder signal corresponding to the difference between said analog voltage and said analog input signal; substituting said remainder signal for said analog input signal to generate a digital representation thereof and a second remainder signal, each time substituting the new previous remainder signal, storing the digital representations of the analog input voltage and a predetermined numberofsub- sequent remainder signals in a microprocessor, determining in said microprocessor the amount of drift compensation required as a result of temperature variations; and generating in said microprocessor a digital output corresponding, after drift compensation, to said analog input voltage.

Hereinafter the invention is described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a first embodiment of an analog-to-digital converter according to the present invention; Figure 2 is a block diagram of a second embody ment of the inventive analog-to-digital converter; and Figure 3 is a block diagram of a third embodiment of a n a an analog-to-digital converter according to the present invention.

Figure 1 consists of a bank of switches 2 (S1, S2 and S3), an eight-bit integrating analog-to-digital converter 4 (or a successive approximation analogto-digital converter), a five-bit resolution sixteen-bit linear digital-to-analog converter 6, sample-andhold circuit 8, sample-and-hold circuit 10, a summing amplifier 12, a differential temperature sensor 14, a microprocessor 16 and gain and offset drift storage register 18.

Sample-and-hold circuits 8 and 10 are used to store intermediate voltages, and microprocessor 16 controls the conversion sequence, signal flow through electronic switches 2 and performs all computations necessary to obtain a 16-bit digital word representing the analog input.

Speed of conversion is limited by integrating analog-to-digital converter4 and the requirements for high normal mode rejection. To increase the speed of conversion, the integrating analog-todigital converter may be replaced by a successive approximation analog-to-digital converter.

Conversion of an input voltage Vin is commenced when electronic switch S1 is closed by microprocessor 16 by means of switch control lines and when 8-bit integrating analog-to-digital converter 4 receives a "Start Conversion" signal from microprocessor 16. Microprocessor 16 may be any one of a variety of known types such as a MOSTEK 3870.

Switches S1,S2 and S3 may comprise a commercially available quad-switch of the type used by Burr-Brown Research Corporation and bearing part number ICC-701. The eight-bit integrating analogto-digital converter may be of a commercially available type, for example, a Teledyne 8703.

A five-bit output from integrating analog-to-digital converter4 represents a first digital approximation of the analog input voltage Vin. This first approximation is applied to inputs of microprocessor 16 and to inputs of linear digital-to-analog converter 6 which may include a 12-bit current switch of the type bearing Burr-Brown part number CIC-294.

The output of digital-to-analog converter6 is applied to an input of error amplifier 12 and is summed with the input voltage Vin. The difference is multiplied by sixteen since error amplifier 12 is designed to have a gain of sixteen. At this point, sample-and-hold 8 is in a "sample" mode and sample-and-hold 10 is in a "hold" mode as a result of control signals applied to sample-and-hold cir cuits 8 and 10 from microprocessor 16. Thus, the output of error amplifier 12 (Va) is received by the first sample-and-h old circuit 8.

Microprocessor 16 then places sample-and-hold circuit 8 in a "hold" mode and sample-and-hold circuit 10 in a "sample" mode. Thus, the error voltage Va is now stored in sample-and-hold 8 and is applied to sample-and-hold 10. Now, by again placing sample-and-hold 10 in a "hold" mode and sampleand-hold 8 in a "sample" mode, the error voltage Va is stored in sample-and-hold circuit 10. Thus, there has been a shifting of the error voltage Va from the output of error amplifier 12 through sample-and-hold circuit 8 to sample-and-hold circuit 10.

Further, there has been a first conversion of the input voltage Vin stored in microprocessor 16 in the form of a five-bit digital word.

The microprocessor 16 now causes switch S1 to open and switch S2 to close. The voltage stored in sample-and-hold circuit 10 is applied via switch S2 to analog-to-digital converter 4 as an unknown input voltage and is also applied to one input of error amplifier 12. As a result, a second five-bit digital conversion is stored in microprocessor 16. Since the output of digital-to-analog converter 6 is still coupled to an input of error amplifier 12, a second error signal Va is generated. This error voltage is shifted serially through sample-and-hold circuit 8 to sample-andhold circuit 10 as described above. Switch S2 remains closed until third and fourth five-bit conversions are generated by analog-to-digital converter4 and stored in microprocessor 16.

While the conversion process may be repeated as many times as required to obtain a desired resolution, 16 conversions during one 30 Hz period result in good normal mode rejection. Further, four conversions are required to obtain sixteen-bit resolution, and since a sixteen-bit accurate linear digitalto-analog converter is utilized, maximum obtainable linearity is 0.001%. Of course, a better digital-toanalog converter (e.g. 18-bit, 20-bit, etc.) may be employed to achieve greater linearity. For example, an 18-bit digital-to-analog converter increases accuracy to 0.00019%. Furthermore, the use of an external reference would permit the microprocessor to calculate linearity errors for each bit and digitally compensate for them.

Afterfourconversions have been completed, microprocessor 16 processes the four 5-bit words to obtain a sixteen-bit digital word representing the analog input.

The inventive conversion system compensates for gain and offset drift which results from temperature variations as follows. Prior to beginning the conversion process for an input voltage Vin (e.g. during initialization or reset of the system), a first reference voltage (+Vri), for example +9.92187 volts, is applied to the conversion- apparatus to determine a positive full-scale reference. A second reference voltage (-Vri), for example -9.92218 volts is applied to the conversion apparatus to determine a negative full-scale reference. Both the positive and negative full-scale voltages are stored in microprocessor 16 in the form of sixteen-bit digital words. Next, switch S3 is closed (S1 and S2 are open), and a voltage generated by differential temperature sensor 14 is applied to the conversion apparatus via switch S3.After four conversions of this voltage, in a manner described above, a sixteen-bit temperature reference is likewise stored in microprocessor 16. This calibration phase should be performed in the same environment as that in which the conversion apparatus will be employed, to obtain maximum compensation range over +25 C around ambient temperature.

After the calibration phase is complete, the analog-to-digital conversion of an analog input voltage Vin proceeds in the manner described above.

After a sixteen-bit digital representation of the input voltage Vin has been computed and stored in microprocessor 16, switch S2 is opened and switch S3 is closed by microprocessor 16 via switch control lines 20. This permits a voltage Vt generated by differential temperature sensor 14, which may include a thermistor, to be applied to the remainder of the conversion apparatus via switch S3. After four conversions of the type above described, a sixteen-bit digital representation of Vt is computed and stored in microprocessor 16. This digital representation of Vt is then compared with the sixteen-bit temperature reference voltage which was stored in microprocessor 16 during the calibration phase. The difference is divided by thirty-two since a temperature change of 1"C will correspond to a voltage difference of thirtytwo least significant bits.

Gain and offset drift storage register 18 is preprogrammed to contain the amount of gain and offset drift which occurs as a function of temperature change. Thus, after the temperature change has been calculated by dividing the temperature voltage difference by thirty-two, the gain and offset drift storage register is searched to determine the appropriate amount of gain and offset drift compensation. The sixteen-bit digital representation of the analog input voltage Vin is then compensated by this amount, and the result is available at the output of microprocessor 16.

Figure 2 is a block diagram of a second embodiment of the inventive microprocessor supervised analag-to-digital converter. Like elements are denoted by like reference numbers; however, in this embodiment switch bank 2 contains switches S1, S2, S3 and S4. An additional bank of switches 20 contains switches SS, S6, S7 and S8.

Conversion of the input voltage Vin is commenced when switches S1 and S6 are closed by a microprocessor 16 via the switch control lines and when converter4 receives a "Start Conversion" signal from microprocessor 16. A first five-bit output from converter 4 represents a first approximation of the analog input voltage Vin. This first approximation is stored in microprocessor 16 and is applied to inputs of converter 6.

The output of didigtal-to-analog converter 6 is applied to error amplifier 12. The input voltage Vin is likewise applied to error amplifier 12 and the result ing error voltage (Va) is applied to sample-and-hold circuit 8 which was previously placed in a "sample" mode by microprocessor 16. When Va is stored in sample-and-hold 8, microprocessor 16 opens switches S1 and S6 and closes switches 53 and S7.

in this manner, the voltage (Va) stored in sampleand-hold circuit 8 is applied as an unknown input voltage to converter4 via switch S3 and to error amplifier 12 via switch S7. A second conversion is stored in microprocessor 16 and a second error voltage is applied to sample-and-hold circuit 10 which has been placed in a "sample" mode by microprocessor 16.

Switches S3 and S7 are now opened and switches S2 and S8 are closed by microprocessor 16. In this manner, the contents of sample-and-hold circuit 10 is applied as an unknown imput voltage to converter 4 via switch S2 and to error amplifier 12 via switch S8. The resulting error voltage (Va) is stored in sample-and-hold circuit 8 thus completing a third conversion. Switches 52 and S8 are opened and switches S3 and S7 are closed to accomplish a fourth conversion.

Microprocessor 16 then processes four 5-bit words representing the four conversions to obtain a sixteen-bit digital word representing the analog input Vin.

Gain and offset drift are compensated for in the same manner described in conjunction with the apparatus shown in Figure 1 using the following switch sequence. The first conversion of the differential temperature sensor 14 output voltage (Vt) is accomplished by closing switches S4 and S5. For the second conversion, switches S3 and S7 are closed.

Switches S2 and S8 are closed for the third conversion, and switches S3 and S7 are again closed for the fourth conversion. Of course, compensation for gain and offset drift requires a calibration phase similar to that described in conjunction with Figure 1 using the appropriate switch sequence; i.e. S4 and S5; S3 and S7; S2 and S8; S3 and S7.

Figure 3 is a block diagram of a third embodiment of the inventive microprocessor supervised analogto-digital converter. Like elements are again denoted by like reference numbers; however, in this embodiment switch bank 2 contains switches S1 and S2, switch bank 20 contains switches S6, S7, S8, and S9 and a new bank of switches 22 contains switches S3, S4 and S5. Furthermore, an additional eight-bit successive approximation analog-to-digital converter 24 is provided having an input coupled to sample-andhold circuit 8, sample-and-hold circuit 10 and differential temperature sensor 14 via switches S3, S4 and S5 respectively. A five-bit output from converter 24 is coupled to microprocessor 16 and linear digital-to-analog converter 6 as is the output of analog-to-digital converter4.The inclusion of successive approximation analog-to-digital converter 24 increases the speed of the inventive analog-to-digital converter while introducing only a small amount of error.

The system operates in a manner similar to that of the arrangement shown in Figure 2. The primary difference resides in the switching sequence for switches S1-S9. For the first conversion of an input analog voltage (Vin), switches S1 and S7 are on. The second conversion takes place when switches S2 and S8 are on and the remaining switches are off.

For the third conversion, all switches are off except switches S4 and S9. Finally, to accomplish the fourth conversion all switches are off except switches S3 and S8. The same switching sequence is employed when converting Vt from differential temperature sensor 14 during both the calibration phase and the compensation phase.

The sample-and-hold circuits and the gain and off set drift registers are commercially available integrated circuits, preferably of the types bearing Burr-Brown part numbers ICC 702 and ICC 317 respectively. Furthermore, error amplifier 12 may be implemented in any standard configuration, for example, of the type employing three operational amplifiers bearing Burr-Brown part number ICC108.

Afirst input of a first operational amplifier is coupled to the analog input voltage (Vin), and a first input of a second operational amplifier is coupled to the output of linear digital-to-analog converter 6. A second input of the first and second operational amplifiers are coupled together. The outputs of the first and second operational amplifiers are coupled respectively to first and second inputs of a third operational amplifier.

While the inventive analog-to-digital converter has been particularly shown and described with reference to preferred embodiments thereof, it should be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the invention as defined in the appendant claims.

Claims (12)

1. An analog-to-digital converter comprising first means which converts an anlog input signal into a first digital representation, second means coupled to said first means which compares said digital representation with said analog input signal and produces an analog error signal in response to said comparison, third means which converts said analog error signal into a second digital representation, and fourth means which combines said first and second digital representations.

2. An analog-to-digital converter according to Claim 1 wherein said second means comprises a digital-to-analog converter having inputs coupled to the outputs of said first means, and comparing means having a first input coupled to the output of said digital-to-analog converter and a second input coupled to said analog input voltage.

3. An analog-to-digital converter according to Claim 1 or Claim 2 wherein said third means comprises means which stores said error signal, and switching means coupled to said storing means and to said first means which connects said error signal to said first means.

4. An analog-to-digital converter according to any of Claims 1,2 or3 wherein said fourth means comprises a microprocessor.

5. An analog-to-digital converter according to any of Claims 1,2,3 or 4 comprising fifth means which provides a voltage indicative of temperature, and sixth means coupled to said fifth means and to said first means which substitutes said voltage for said analog input signal, said fourth means generating a digital representation of said voltage to deter mine the amount of drift compensation.

6. An analog-to-digital converter according to any of the preceding claims comprising first storage means coupled to said fourth means for storing, in digital form, amounts of drift compensation for various amounts of temperature change.

7. An analog-to-digital converter according to Claim 2 or any claims appendant thereto wherein said comparing means is an error amplifier.

8. An analog-to-digital converter according to Claim 4when appendantto Claim 3 orto any of Claims 5 to 7 when the latter are appendantto Claims 3 and 4, wherein said storage means comprises a first sample-and-hold circuit coupled to said microprocessor for receiving said error signal when placed in a "sample" mode by said microprocessor and storing said error signal when placed in a hold mode by said microprocessor, and a second sample-and-hold circuit coupled to said microprocessor for receiving the contents of said first sample-and-hold circuit when placed in a "sample" mode by said microprocessor and storing the contents of said first sample-and-hold circuit when placed in a "hold" mode by said microprocessor, said first sample-and-hold circuit being again placed in a "sample" mode after said second sample-andhold circuit is placed in a "hold" mode so as to be available to receive a subsequent error signal.

9. An analog-to-digital converter according to Claim 8 wherein said switching means comprises a first switch which couples said analog input signal to said first means, and a second switch which couples the contents of said second sample-and-hold circuit to said first means, said first switch being opened when said second switch is closed.

10. An analog-to-digital converter according to Claim 3 and Claim 4 wherein said storing means comprises first and second sample-and-hold circuits controlled by said microprocessor and having inputs coupled to an output of said error amplifier for alternately receiving and storing successive error signals.

11. An analog-to-digital converter according to Claim 10 wherein said switching means comprises first switching means controlled by said microprocessor which selectively couples said analog input signal, said first sample-and-hold circuit and said second sample-and-hold circuit to said first means, and second switching means which selectively cou ples said analog input signal, said first sample-and hold circuit to said comparing means.

12. An analog-to-digital converter substantially as described herein with reference to Figure 1 or Figure 2 of the accompanying drawing.