GB201801251D0 - Soft-partitioning of a register file cache - Google Patents
Soft-partitioning of a register file cacheInfo
- Publication number
- GB201801251D0 GB201801251D0 GBGB1801251.8A GB201801251A GB201801251D0 GB 201801251 D0 GB201801251 D0 GB 201801251D0 GB 201801251 A GB201801251 A GB 201801251A GB 201801251 D0 GB201801251 D0 GB 201801251D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- partitioning
- soft
- register file
- file cache
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1801251.8A GB2556740A (en) | 2013-11-29 | 2013-11-29 | Soft-partitioning of a register file cache |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1801251.8A GB2556740A (en) | 2013-11-29 | 2013-11-29 | Soft-partitioning of a register file cache |
| GB1617657.0A GB2545307B (en) | 2013-11-29 | 2013-11-29 | A module and method implemented in a multi-threaded out-of-order processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB201801251D0 true GB201801251D0 (en) | 2018-03-14 |
| GB2556740A GB2556740A (en) | 2018-06-06 |
Family
ID=61558179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1801251.8A Withdrawn GB2556740A (en) | 2013-11-29 | 2013-11-29 | Soft-partitioning of a register file cache |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2556740A (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6314511B2 (en) * | 1997-04-03 | 2001-11-06 | University Of Washington | Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers |
| US7634621B1 (en) * | 2004-07-13 | 2009-12-15 | Nvidia Corporation | Register file allocation |
| CN101627365B (en) * | 2006-11-14 | 2017-03-29 | 索夫特机械公司 | Multi-threaded architecture |
| US20130086364A1 (en) * | 2011-10-03 | 2013-04-04 | International Business Machines Corporation | Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information |
| GB2496934B (en) * | 2012-08-07 | 2014-06-11 | Imagination Tech Ltd | Multi-stage register renaming using dependency removal |
| GB2501791B (en) * | 2013-01-24 | 2014-06-11 | Imagination Tech Ltd | Register file having a plurality of sub-register files |
| GB2502857B (en) * | 2013-03-05 | 2015-01-21 | Imagination Tech Ltd | Migration of data to register file cache |
-
2013
- 2013-11-29 GB GB1801251.8A patent/GB2556740A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB2556740A (en) | 2018-06-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |