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DE60320026D1 - Verbessertes speichermanagement für echtzeitanwendungen - Google Patents

Verbessertes speichermanagement für echtzeitanwendungen

Info

Publication number
DE60320026D1
DE60320026D1 DE60320026T DE60320026T DE60320026D1 DE 60320026 D1 DE60320026 D1 DE 60320026D1 DE 60320026 T DE60320026 T DE 60320026T DE 60320026 T DE60320026 T DE 60320026T DE 60320026 D1 DE60320026 D1 DE 60320026D1
Authority
DE
Germany
Prior art keywords
real
storage management
improved storage
address translation
time applications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60320026T
Other languages
English (en)
Other versions
DE60320026T2 (de
Inventor
Michael Norman Day
Harm Peter Hofstee
Charles Ray Johns
James Allan Kahle
Thuong Quang Truong
David Shippy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE60320026D1 publication Critical patent/DE60320026D1/de
Application granted granted Critical
Publication of DE60320026T2 publication Critical patent/DE60320026T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)
DE60320026T 2002-12-12 2003-11-21 Verbessertes speichermanagement für echtzeit-anwendungen Expired - Lifetime DE60320026T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/318,541 US7103748B2 (en) 2002-12-12 2002-12-12 Memory management for real-time applications
US318541 2002-12-12
PCT/GB2003/005108 WO2004053698A2 (en) 2002-12-12 2003-11-21 Improved tlb management for real-time applications

Publications (2)

Publication Number Publication Date
DE60320026D1 true DE60320026D1 (de) 2008-05-08
DE60320026T2 DE60320026T2 (de) 2009-05-14

Family

ID=32506386

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60320026T Expired - Lifetime DE60320026T2 (de) 2002-12-12 2003-11-21 Verbessertes speichermanagement für echtzeit-anwendungen

Country Status (11)

Country Link
US (1) US7103748B2 (de)
EP (1) EP1581873B1 (de)
JP (1) JP4129458B2 (de)
KR (1) KR100843536B1 (de)
CN (1) CN100397367C (de)
AT (1) ATE390667T1 (de)
AU (1) AU2003302824A1 (de)
CA (1) CA2505610C (de)
DE (1) DE60320026T2 (de)
IL (1) IL169136A0 (de)
WO (1) WO2004053698A2 (de)

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US7362705B2 (en) * 2004-05-13 2008-04-22 International Business Machines Corporation Dynamic load-based credit distribution
JP4233492B2 (ja) * 2004-06-02 2009-03-04 富士通マイクロエレクトロニクス株式会社 アドレス変換装置
US7840757B2 (en) * 2004-07-29 2010-11-23 International Business Machines Corporation Method and apparatus for providing high speed memory for a processing unit
US20060045031A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Automatic hardware data link initialization using multiple state machines
US20060047862A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Automatic hardware data link initialization
US7546401B2 (en) * 2004-09-23 2009-06-09 International Business Machines Corporation Byte to byte alignment of multi-path data
US7305524B2 (en) * 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US20060080511A1 (en) * 2004-10-08 2006-04-13 International Business Machines Corporation Enhanced bus transactions for efficient support of a remote cache directory copy
US7577794B2 (en) 2004-10-08 2009-08-18 International Business Machines Corporation Low latency coherency protocol for a multi-chip multiprocessor system
US7475190B2 (en) * 2004-10-08 2009-01-06 International Business Machines Corporation Direct access of cache lock set data without backing memory
US8332592B2 (en) * 2004-10-08 2012-12-11 International Business Machines Corporation Graphics processor with snoop filter
US7385925B2 (en) * 2004-11-04 2008-06-10 International Business Machines Corporation Data flow control method for simultaneous packet reception
US7260765B2 (en) * 2004-12-17 2007-08-21 International Business Machines Corporation Methods and apparatus for dynamically reconfigurable parallel data error checking
US20060140122A1 (en) * 2004-12-28 2006-06-29 International Business Machines Corporation Link retry per virtual channel
US7499452B2 (en) * 2004-12-28 2009-03-03 International Business Machines Corporation Self-healing link sequence counts within a circular buffer
US20060159023A1 (en) * 2005-01-14 2006-07-20 International Business Machines Corporation CRC error history mechanism
US7234017B2 (en) * 2005-02-24 2007-06-19 International Business Machines Corporation Computer system architecture for a processor connected to a high speed bus transceiver
US7194567B2 (en) * 2005-02-24 2007-03-20 International Business Machines Corporation Method and system for ordering requests at a bus interface
US7469312B2 (en) * 2005-02-24 2008-12-23 International Business Machines Corporation Computer system bus bridge
US7275124B2 (en) * 2005-02-24 2007-09-25 International Business Machines Corporation Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability
US7206886B2 (en) * 2005-02-24 2007-04-17 International Business Machines Corporation Data ordering translation between linear and interleaved domains at a bus interface
US20060190655A1 (en) * 2005-02-24 2006-08-24 International Business Machines Corporation Apparatus and method for transaction tag mapping between bus domains
US7330925B2 (en) * 2005-02-24 2008-02-12 International Business Machines Corporation Transaction flow control mechanism for a bus bridge
US7275125B2 (en) * 2005-02-24 2007-09-25 International Business Machines Corporation Pipeline bit handling circuit and method for a bus bridge
US7500062B2 (en) * 2005-11-17 2009-03-03 International Business Machines Corporation Fast path memory read request processing in a multi-level memory architecture
JP2007233615A (ja) * 2006-02-28 2007-09-13 Fujitsu Ltd アドレス変換装置
US7886112B2 (en) * 2006-05-24 2011-02-08 Sony Computer Entertainment Inc. Methods and apparatus for providing simultaneous software/hardware cache fill
US7908439B2 (en) * 2007-06-25 2011-03-15 International Business Machines Corporation Method and apparatus for efficient replacement algorithm for pre-fetcher oriented data cache
US8244979B2 (en) * 2007-07-13 2012-08-14 International Business Machines Corporation System and method for cache-locking mechanism using translation table attributes for replacement class ID determination
US8099579B2 (en) * 2007-07-13 2012-01-17 International Business Machines Corporation System and method for cache-locking mechanism using segment table attributes for replacement class ID determination
US20090049272A1 (en) * 2007-08-13 2009-02-19 International Business Machines Corporation Method for improving the performance of software-managed tlb
US8966219B2 (en) * 2007-10-30 2015-02-24 International Business Machines Corporation Address translation through an intermediate address space
US8108617B2 (en) * 2008-02-08 2012-01-31 International Business Machines Corporation Method to bypass cache levels in a cache coherent system
JP5300407B2 (ja) 2008-10-20 2013-09-25 株式会社東芝 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法
KR100987332B1 (ko) 2008-11-07 2010-10-18 서울대학교산학협력단 메모리 구조에 따른 메모리 관리 장치
EP2192493A1 (de) 2008-11-28 2010-06-02 ST Wireless SA Verfahren zum Rufen auf Anfrage für eine virtuelle Speicherverwaltung in einem Verarbeitungssystem und entsprechendes Verarbeitungssystem
US8397049B2 (en) * 2009-07-13 2013-03-12 Apple Inc. TLB prefetching
CN102662869B (zh) * 2012-04-01 2015-08-26 龙芯中科技术有限公司 虚拟机中的内存访问方法和装置及查找器
US9003125B2 (en) 2012-06-14 2015-04-07 International Business Machines Corporation Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
US9086980B2 (en) 2012-08-01 2015-07-21 International Business Machines Corporation Data processing, method, device, and system for processing requests in a multi-core system
US9213532B2 (en) 2013-09-26 2015-12-15 Oracle International Corporation Method for ordering text in a binary
US10229048B2 (en) 2016-06-29 2019-03-12 Western Digital Technologies, Inc. Unified paging scheme for dense and sparse translation tables on flash storage systems
US11216361B2 (en) 2016-06-29 2022-01-04 Western Digital Technologies, Inc. Translation lookup and garbage collection optimizations on storage system with paged translation table
US10175896B2 (en) 2016-06-29 2019-01-08 Western Digital Technologies, Inc. Incremental snapshot based technique on paged translation systems
US10235287B2 (en) 2016-06-29 2019-03-19 Western Digital Technologies, Inc. Efficient management of paged translation maps in memory and flash
US10353813B2 (en) 2016-06-29 2019-07-16 Western Digital Technologies, Inc. Checkpoint based technique for bootstrapping forward map under constrained memory for flash devices
US10579522B2 (en) * 2016-09-13 2020-03-03 Andes Technology Corporation Method and device for accessing a cache memory

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US6442664B1 (en) * 1999-06-01 2002-08-27 International Business Machines Corporation Computer memory address translation system
US6430667B1 (en) * 2000-04-13 2002-08-06 International Business Machines Corporation Single-level store computer incorporating process-local address translation data structures
EP1182569B8 (de) 2000-08-21 2011-07-06 Texas Instruments Incorporated TLB-Ver- und Entriegelungsoperation
JP2002140234A (ja) 2000-11-02 2002-05-17 Hitachi Ltd キャッシュ装置
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Also Published As

Publication number Publication date
WO2004053698A3 (en) 2006-01-12
IL169136A0 (en) 2007-07-04
EP1581873A2 (de) 2005-10-05
US7103748B2 (en) 2006-09-05
JP2006515088A (ja) 2006-05-18
CA2505610C (en) 2009-06-23
AU2003302824A8 (en) 2004-06-30
DE60320026T2 (de) 2009-05-14
WO2004053698A2 (en) 2004-06-24
CN100397367C (zh) 2008-06-25
AU2003302824A1 (en) 2004-06-30
US20040117592A1 (en) 2004-06-17
CA2505610A1 (en) 2004-06-24
CN1820258A (zh) 2006-08-16
EP1581873B1 (de) 2008-03-26
KR20050088077A (ko) 2005-09-01
ATE390667T1 (de) 2008-04-15
KR100843536B1 (ko) 2008-07-04
JP4129458B2 (ja) 2008-08-06

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition