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DE19983737T1 - Verfahren und Vorrichtung zum Erfassen der Kollision von Daten auf einem Datenbus im Fall von Außer-Reihe-Speicherzugriffen oder unterschiedlichen Zeiten der Speicherzugriffsausführung - Google Patents

Verfahren und Vorrichtung zum Erfassen der Kollision von Daten auf einem Datenbus im Fall von Außer-Reihe-Speicherzugriffen oder unterschiedlichen Zeiten der Speicherzugriffsausführung

Info

Publication number
DE19983737T1
DE19983737T1 DE19983737T DE19983737T DE19983737T1 DE 19983737 T1 DE19983737 T1 DE 19983737T1 DE 19983737 T DE19983737 T DE 19983737T DE 19983737 T DE19983737 T DE 19983737T DE 19983737 T1 DE19983737 T1 DE 19983737T1
Authority
DE
Germany
Prior art keywords
data
collision
event
detecting
different times
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983737T
Other languages
English (en)
Other versions
DE19983737B3 (de
Inventor
Henry Stracovsky
Piotr Szabelski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE19983737T1 publication Critical patent/DE19983737T1/de
Application granted granted Critical
Publication of DE19983737B3 publication Critical patent/DE19983737B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
DE19983737.6T 1998-11-16 1999-11-15 System zum Neuordnen von Befehlen, die von einer Speichersteuerung zu Speichervorrichtungen ausgegeben werden, unter Verhinderung von Kollision Expired - Fee Related DE19983737B3 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10893098P 1998-11-16 1998-11-16
US60/108,930 1998-11-16
US09/439,591 US6453370B1 (en) 1998-11-16 1999-11-12 Using of bank tag registers to avoid a background operation collision in memory systems
US439591 1999-11-12
PCT/US1999/027016 WO2000029921A2 (en) 1998-11-16 1999-11-15 Methods and apparatus for detecting data collision on data bus for different times of memory access execution

Publications (2)

Publication Number Publication Date
DE19983737T1 true DE19983737T1 (de) 2002-03-07
DE19983737B3 DE19983737B3 (de) 2014-05-22

Family

ID=26806432

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983737.6T Expired - Fee Related DE19983737B3 (de) 1998-11-16 1999-11-15 System zum Neuordnen von Befehlen, die von einer Speichersteuerung zu Speichervorrichtungen ausgegeben werden, unter Verhinderung von Kollision

Country Status (7)

Country Link
US (1) US6453370B1 (de)
JP (1) JP4695761B2 (de)
KR (1) KR100716346B1 (de)
CN (1) CN100354796C (de)
DE (1) DE19983737B3 (de)
GB (1) GB2359164B (de)
WO (1) WO2000029921A2 (de)

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US8880819B2 (en) * 2011-12-13 2014-11-04 Micron Technology, Inc. Memory apparatuses, computer systems and methods for ordering memory responses
US9329990B2 (en) * 2013-01-11 2016-05-03 Micron Technology, Inc. Host controlled enablement of automatic background operations in a memory device
KR20150020477A (ko) * 2013-08-16 2015-02-26 삼성전자주식회사 메모리 장치, 이를 포함하는 메모리 시스템 및 그 동작 방법
CN103455768B (zh) * 2013-08-26 2016-04-13 中国科学院数据与通信保护研究教育中心 一种usb安全存储方法及系统
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US11024361B2 (en) 2017-01-06 2021-06-01 Qualcomm Incorporated Coincident memory bank access via cross connected shared bank resources
US10620879B2 (en) * 2017-05-17 2020-04-14 Macronix International Co., Ltd. Write-while-read access method for a memory device
CN107463759B (zh) * 2017-09-18 2020-08-04 北京兆易创新科技股份有限公司 一种计时器的仿真验证装置及仿真验证方法
US10489056B2 (en) 2017-11-09 2019-11-26 Nvidia Corporation Queue manager for streaming multiprocessor systems
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
CN109062602B (zh) * 2018-07-20 2022-03-18 卓米私人有限公司 一种针对应用程序的数据处理方法、装置及电子设备
CN109284214B (zh) * 2018-08-15 2021-04-06 英业达科技有限公司 信息共享电路及共享内存状态的方法
CN111221573B (zh) * 2018-11-26 2022-03-25 深圳云天励飞技术股份有限公司 一种寄存器访问时序的管理方法、处理器、电子设备及计算机可读存储介质
CN109885857B (zh) * 2018-12-26 2023-09-01 上海合芯数字科技有限公司 指令发射控制方法、指令执行验证方法、系统及存储介质
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CN112188697A (zh) * 2020-11-05 2021-01-05 宁波钧飞智能科技有限公司 一种面向不可靠ZigBee网络的灯光和空调控制算法及系统
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Also Published As

Publication number Publication date
CN100354796C (zh) 2007-12-12
KR20010081016A (ko) 2001-08-25
JP2002530731A (ja) 2002-09-17
WO2000029921A3 (en) 2000-10-05
GB0111923D0 (en) 2001-07-04
KR100716346B1 (ko) 2007-05-11
WO2000029921A2 (en) 2000-05-25
CN1357121A (zh) 2002-07-03
WO2000029921A9 (en) 2001-03-22
GB2359164A (en) 2001-08-15
JP4695761B2 (ja) 2011-06-08
DE19983737B3 (de) 2014-05-22
GB2359164B (en) 2003-12-03
US6453370B1 (en) 2002-09-17

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