DE1135685B - Tetradically encrypted decimal counter - Google Patents

Description

Tetradically encrypted decimal counter For counting in the decimal system one often uses tetradically coded decimal works, each with decimals four bistable multivibrators with two outputs each are assigned. By four bistable flip-flops are 16 binary four-digit numbers, so-called tetrads, can be displayed, six of which must be skipped. Let this jump be hereinafter referred to as code throwing.

A number of different decimal codes have already become known, for example the Aiken code, the 3-excess code, etc. In the known tetradically encrypted decimal counters, however, only upward counting is possible, and the use of so-called complementary codes is confronted with considerable difficulties. A code is called complementary in which the nine's complement of the respective tetrad appears at the complementary outputs of the bistable multivibrators. For example, if the number 3 is in a decimal place as a tetrad 0, 0, L, L at the outputs of the four trigger stages, the complementary outputs of these stages carry the signals L, L, 0, 0, which in the Aiken code is the decimal number 6, thus corresponds to the nine's complement of the decimal number 3.

The invention is based on the object of a tetradically encrypted Build a decimal counter from bistable multivibrators with two outputs each, the can be switched to any tetradic decimal codes and easily if necessary can be added in such a way that it is not only for counting up or down, it is also suitable for counting up and down.

According to the invention, this object is achieved by at least one gate (AND gate, OR gate) solved that the switching state of the third and fourth binary bistable flip-flop before the code throwing as preparation and the switching status of the first flip-flop after the next pulse used to trigger the switching state the second and third binary bistable flip-flop to change the code accordingly.

The gate can, for example, be an AND gate to which the signals the first, third and fourth stage and its output signal intervenes in the second and third stages. A non-gate can also be used instead of the und-gate be used, which receives the corresponding complementary signals of the tetrads. As is well known, a non-gate emits an output signal when all inputs are unoccupied.

Two gates are to be used for counting up and down, in addition are occupied by the forward or reverse signal. Again, and gates can be used here or non-gates are used. In the latter case, the complementary signals used by the forward and reverse signal.

To explain the invention in more detail, a compilation of three different decimal codes will be given and compared with the decimal numbers 0 to 15 and the tetrads: Decimal binary binary with alkene 3 excess zah @ en tetrads 15 code code code 0 0 0 0 0 0000 0 0000 0 1 0 0 0 L 000L 1 000L 1 2 0 0 L 0 00L0 2 00L0 2 3 0 0 LL OOLL 3 OOLL 3 OOLL 0 4 0 L 0 0 0L00 4 0L00 4 0L00 1 5 0 L 0 L OLOL 5 OLOL 2 6 0 LL 0 OLLO 6 OLLO 3 7 0 LLL OLLL 7 OLLL 4 8 L 0 0 0 L000 8 L000 5 9 LOOL LOOL 6 10 LOLO LOL07 11 LOLL L0 LL 5 L0 LL 8 12 LL 0 0 LL00 6 LLOO 9 13 LLO L LLOL7 14 LLLO LLLO 8 15 LLLL LLLL 9 LLLL 9 4.3.2.1. step In the case of the so-called binary with 15 code, the tetrad L, L, L, L is assigned the decimal number 9, and code throwing in the forward direction is done by changing the second and third level from 0 to L. Accordingly, the output signal A4 would be an AND gate fourth stage, the output signal Ä3 of the third stage and the output signal A1 occurring after the next pulse to the first stage. The AND gate then also switches the second and third stages from 0 to L, so that actually after the tetrad L, 0, 0, 0 representing the number $, the tetrad L, L, L, L appears as the number 9.

In the Aiken code, an AND gate must receive the signals 4 and A3 as preparation and the signal A 1 as triggering. It sets the switching states of the second and third stages from 0 to L or from L to O. The fourth stage is then moved from 0 to L. This corresponds to the jump from the tetrad 0, L; O, O (decimal number 4) to the tetrad L, 0; L, L to which the decimal number 5 is assigned.

In the 3 excess code the tetrad is L, L, 0, 0 in the tetrad 0, 0, L, L to throw. The AND gate receives the signals A3 and A4 as preparation and that Signal A1 as a trigger. There are again the switching states of the second and third Level changed from the outside and thus the fourth level was dragged along.

In the last two cases treated, the change in third stage also the change of the switching state of the fourth stage to Sequence that unwinds itself. (The transition L - 0 in any Level leads to a change in the switching status in the next higher level at Forward numbers; vice versa when counting down.) The Derive input signals for gates that roll the code when paying back.

To explain the operation of the invention in more detail, see in The following describes an embodiment that is shown schematically in the drawing is shown.

Fig. 1 shows the circuit for a decimal place of a forward and backward working counter, consisting of the four bistable flip-flops 1, 2, 3 and 4 with the outputs A1, A2, A3, A4 and the complementary outputs Äl, Ä2, Ä3, 54 'The circuits for further decimal places are structured identically. the The first level of the following decimal place is always with the outputs of the last Level connected to the preceding decimal place.

Since the counter should be suitable for counting up and down, two gates 5 and 6 are provided for code throwing. The exemplary embodiment is based on the use of non-gates. In addition to the complementary signals of the first, third and fourth level of the decimal place, the complementary signals of the forward and backward signals, namely V = R and 1i ' = V, are also introduced into the non-gates.

The pulse input of the circuit for the first decimal place is with 1, the pulse enable input labeled 1F. The counter can only use pulses controlled when there is a continuous signal at the pulse enable input. The entrances 102 and 103 of flip-flop 1 are therefore combined via an AND gate. The counting circuit also allows the entry of digits directly into individual decimal places, so that, for example, the number 245 does not have to be represented by 245 pulses, but from two pulses in the hundreds decimal place, four pulses in the tens decimal place and five pulses can be reproduced in the one-decimal place. Furthermore is it possible e.g. B. to specify the number 150 15 pulses in the tens decimal place to enter.

For this so-called decimal number input there is an input DZ, and a Release input DZr, provided, which in turn at 112 and 113 via an AND gate are summarized. Corresponding inputs are on the first level of each additional level Decade to be provided.

The up and down counting is done with the help of separate lines prescribed, the terminals of which are marked with V and R. Located at V. Continuous signal, the circuit counts up, and it counts down when there is a continuous signal to R. The signals V and R are mutually exclusive.

Furthermore, the counter can be reset to 0 by a reset pulse at terminal L. The clearing inputs 101, 201, 301, 401 are combined with the remaining clearing inputs of all flip-flops and routed to a common clearing newspaper.

Finally, instead of successive impulses, it is possible to enter a number in the counter "parallel", ie in all toggle stages of the counter at the same time. The inputs P, which are combined with an enable line F via the AND gates 10, 20, 30, 40 shown for the first decimal, are used for this purpose. As soon as a signal appears on the release line F, the flip-flops that are in their zero position are set according to the parallel input.

The internal structure of the individual levels basically corresponds to this Scheme according to Fig. 2. The actual flip-flop 17 is equipped with a set input E, a clear input E, an output A and a complementary output Ä provided. A binary input EB is also provided. Successive pulses on binary As is known, input of a bistable flip-flop circuit causes the overturning in each case in the other switching state.

The parallel input P is combined with the enable line F via an AND gate, which is denoted by 11 in FIG. It corresponds to the AND gates 10 to 40 in FIG. 1. Furthermore, an input CW is provided for code throwing, which is combined with the output of the AND gate 11 in an OR gate 12. The output signal of the OR gate 12 is fed to the set input of the flip-flop 17. It corresponds to the inputs 111, 211, 311, 411 in FIG. 1. The OR gate 12 can be implemented simply by merging the corresponding lines via resistors, as is indicated in FIG. 1.

An AND gate 13 is used for entering and releasing the decimal number intended. The corresponding inputs in stage 1 (Fig. 1) are 113 and 112.

The downward signal at terminal R and the downward counting pulses each of which is supplied by the preceding flip-flop are in an AND gate 14 summarized, while forward signal and forward counting pulses to an AND gate 15th are led. Occupy the outputs of AND gates 13, 14 and 15 Inputs of an OR gate 16, whose output signal corresponds to the binary input of the flip-flop 17 is fed.

At input stage 1 of the counter a decision is made regarding Up or down counting is not necessary as this toggle switch works with each Impulse has to change its state, regardless of whether it is counted forwards or backwards target. Therefore, one of the AND gates 14 or 15 (inputs 102 and 103).

In the flip-flops 2, 3 and 4, the inputs 212, 213 and 312, 313, 412, 413 the inputs of the AND gate 14 in Fig. 2, the inputs 202, 203, 302, 303, 402, 403 the inputs of the AND gate 15 in FIG. At the steps 2, 3 and 4, the and gates 14 and 15 are required, but this is not applicable Gate 13.

Finally, an OR gate 18 is assigned to each stage, its inputs be occupied by the cancellation signal and the code throwing signal. The outcome of the Or gate is connected to the reset input F of the flip-flop 17. The Oder gate 18 can in turn be realized by resistors.

The locking of the individual multivibrators by the signals V and R has the effect, as can be deduced from FIG. 1, that in the case of successive pulses at input 1 the tetrads in the decimal places in the sense of counting up and down can be changed, in addition, at the required time with help the gates 5 and 6 the code throwing is carried out.

In the circuit according to FIG. 1 with non-gates, which is based on the Aiken code, the following signals are fed to the gates: The signals A1, 7131 A4 and R = V for the up counting to the gate 5, the signals A1, A3 to the gate 6 , Ä4 and V = R for counting down. Gate 5 intervenes in the switching state of levels 2 and 3, namely at set input 211 of level 2 and at clear input 301 of level 3. Complementary are the effects of the output signal from gate 6 at clear input 201 of level 2 and at set input 311 level 3.

in Fig. 3 these relationships are indicated again schematically.

In the case of the 3 excess code (see FIG. 4), the gate 5 receives the signals ; il, λ3, λ4 and R, the gate 6 the signals A1, A3 and A4 and V. The output signals are fed to inputs 211 and 301 or 201 and 311.

In the case of binary-with-15-Co, de (cf. FIG. 5), gate 5 receives the signals Ä1, A3, Ä4 and R, the gate 6 the signals A1, 51,3, Ä4 and V. The outputs work to inputs 211 and 311 or 201 and 301.

For other decimal codes, the required input signals and the location of the action in the second and third stages can be derived.

From Fig. 3 and 4 it can be seen immediately that both the input signals of the two gates as well as the place of influence on the second and third stage are complementary to each other. This is a consequence of the fact that Aiken- and 3 excess codes are complementary codes. You have opposite the binary-with-1.5 code the advantage that the number stored in the counter can be processed in arithmetic units can. In addition, the Aiken code enables the individual levels of the counter to have weights assign the composition directly in a subsequent digital-to-analog converter of the corresponding analog value.

The invention therefore makes it possible for the respective present The purpose of using a code that appears to be favorable and and counting backwards. This is achieved by the special feature of the invention, from the switching states of the first, third and fourth stage in a simple manner to derive a signal to influence the second and third stage via gates.

Claims (4)

PATENT CLAIMS: 1. Tetradically encoded, from bistable flip-flops Decimal counter with two outputs each for up and / or down counting in a selectable tetradic code, identified by at least one gate (5, 6), which shows the switching state of the third and fourth bistable multivibrator before Code throwing as preparation and the switching status of the first bistable multivibrator used for triggering after the next impulse to change the switching status of the second and to change the third bistable multivibrator according to the code. 2. Counter after Claim 1, characterized by a non-gate whose inputs depend on the complementary signals the tetrad to be occupied. 3. Counter according to claim 1, characterized in that that two gates are used for counting up and down, which are additionally provided by the Forward and backward signals are occupied. 4. Counter according to claim 3 with two non-gates, characterized in that it is additionally dependent on the complementary signals from pre and Reverse signal are busy.