CN203930814U - A kind of CPU board card based on PCIE interface and configurable switch - Google Patents

Abstract

The utility model discloses a CPU board based on a PCIE interface and a configurable switch. CPU board. The technical solution is: its structure includes CPU, 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, clock chip, gold finger, CPU and 2 PHY chips, Flash memory, RAM memory, JTAG The interface, RTC, EEPROM, power supply, and clock chips are interconnected. The CPU is connected to two PHY chips through the MII, and the two PHY chips are connected to the gold finger through the Transformer. The CPU is connected to the gold finger through the PCIE bus and the UART bus.

Description

A CPU board based on a PCIE interface and a configurable switch

technical field

The utility model relates to a CPU board, specifically a CPU board based on a PCIE interface and a switch can be configured.

Background technique

The central processing unit (CPU, English: Central Processing Unit) is one of the main equipment of the electronic computer and the core accessory in the computer. Its function is mainly to interpret computer instructions and process data in computer software. All operations in the computer are the core components that the CPU is responsible for reading instructions, decoding instructions, and executing instructions.

A switch (English: Switch, meaning "switch") is a network device used for electrical signal forwarding. It can provide an exclusive electrical signal path for any two network nodes connected to the switch.

PCIE, namely PCI-Express, is the latest bus and interface standard. Its main advantage is the high data transmission rate, the current highest 16X 2.0 version can reach 10GB/s, and there is still considerable development potential.

In the computer field, the motherboard, sound card, graphics card, etc. are collectively referred to as a board. The CPU board in the prior art does not have a CPU board with a modular configurable switch, which is quite inconvenient to use.

Utility model content

The technical task of the utility model is to provide a standardized, modularized and easy-to-install switch CPU board based on a PCIE interface and a configurable switch for the above deficiencies.

The technical solution adopted by the utility model to solve its technical problems is: a CPU board card based on PCIE interface and configurable switch, including CPU, 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply , clock chip, gold finger, CPU is interconnected with 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, and clock chip respectively, and the CPU is connected to 2 PHY chips and 2 PHY chips through MII It is connected to the golden finger through the Transformer, and the CPU is connected to the golden finger through the PCIE bus and the UART bus.

The CPU is connected to 2 PHY chips respectively through SGMII.

The Flash memory is two 128M Flash memories, which are all interconnected with the CPU.

The RAM memory is two 256M RAM memories, which are all interconnected with the CPU.

The CPU is interconnected with RTC and EEPROM through the I2C bus.

Noun analysis:

The full English name of RTC is Real-Time Clock, which translates to a real-time clock chip. RTC is the pulse generated by the clock circuit composed of the crystal oscillator and related circuits on the CPU board.

EEPROM (Electrically Erasable Programmable ROM, Electrically Erasable Programmable Read-Only Memory) is a user-changeable read-only memory (ROM) that can be erased and reprogrammed by applying a higher than normal voltage.

I2C bus: English full name Inter-Integrated Circuit, translated as integrated circuit bus, used to connect micro CPU and its peripheral chips.

JTAG is also an international standard test protocol (IEEE 1149.1 compatible), mainly used for chip internal testing. The standard JTAG interface is 4 lines: JTAG [1] TMS, TCK, TDI, TDO, respectively mode selection, clock, data input and data output lines. The definition of the relevant JTAG pins is: TCK is the test clock input; TDI is the test data input, and the data is input to the JTAG interface through the TDI pin; TDO is the test data output, and the data is output from the JTAG interface through the TDO pin; TMS is the test mode selection , TMS is used to set the JTAG interface in a specific test mode; TRST is the test reset, input pin, active low.

Flash memory is a kind of memory chip, and the data inside can be modified through a specific program. FLASH in the field of electronics and semiconductors often means Flash Memory, which is usually called "flash memory", and its full name is Flash EEPROM Memory.

RAM memory: the English full name is random access memory, that is, random access memory. The content of the storage unit can be taken out or stored at will as needed, and the speed of access has nothing to do with the location of the storage unit. This kind of memory will lose its storage content when the power is turned off, so it is mainly used to store short-term use programs.

PHY chip (Physical Layer chip, that is, a physical layer chip): refers to a chip that interfaces with external signals. The physical layer provides transmission media and interconnection devices for data communication between devices, and provides a reliable environment for data transmission.

The connecting finger is the connecting part between the memory stick and the memory slot, and all signals are transmitted through the connecting finger. Gold fingers are composed of many golden-yellow conductive contacts. Because the surface is gold-plated and the conductive contacts are arranged like fingers, they are called "gold fingers". Gold fingers are actually coated with a layer of gold on the copper clad laminate through a special process, because gold has strong oxidation resistance and strong conductivity.

PCIE bus: It is a general bus specification, including not only the display interface, but also various application interfaces such as CPU, PCI, HDD, and Network.

UART bus: UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver/Transmitter) is a kind of asynchronous serial port communication protocol. The working principle is to transmit each character of the transmitted data one by one.

SGMII: Abbreviation for Serial Gigabit Media Independent Interface, that is, Serial Gigabit Media Independent Interface.

MII, or Media Independent Interface, is an Ethernet industry standard defined by IEEE-802.3. It includes a data interface, and a management interface between the MAC and the PHY. The data interface consists of two independent channels for the transmitter and receiver. Each channel has its own data, clock and control signals. A total of 16 signals are required for the MII data interface. The management interface is a two-signal interface: one is a clock signal and the other is a data signal. Through the management interface, upper layers can monitor and control the PHY.

Transformer: Transformer.

Compared with the prior art, a kind of CPU board based on PCIE interface and configurable switch of the present utility model has the following advantages:

1. Configure two PHY chips to provide two 100M network ports, easy to install switches;

2. Two 128M Flash memories and two 256M RAM memories provide sufficient memory for system processing;

3. It also includes a set of PCIE bus and UART bus to provide users with more configuration options;

4. Not only has advantages in cost and flexibility, but also can be used on multiple platforms, reducing project development time.

Description of drawings

Below in conjunction with accompanying drawing, the utility model is further described.

Accompanying drawing 1 is a kind of structural connection block diagram of the CPU plate card based on PCIE interface and configurable switch.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the utility model is further described.

Example 1:

A kind of CPU board card of the utility model based on PCIE interface and configurable switch, its structure comprises CPU, 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, clock chip, golden finger, CPU It is interconnected with 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, and clock chips respectively. The CPU is connected to 2 PHY chips through MII. Connect to golden finger through PCIE bus and UART bus.

Example 2:

A kind of CPU board card of the utility model based on PCIE interface and configurable switch, its structure comprises CPU, 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, clock chip, golden finger, CPU It is interconnected with 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, and clock chips respectively. The CPU is connected to 2 PHY chips through MII. Connect to golden finger through PCIE bus and UART bus.

The CPU is connected to 2 PHY chips respectively through SGMII.

The Flash memory is two 128M Flash memories, which are all interconnected with the CPU.

The RAM memory is two 256M RAM memories, which are all interconnected with the CPU.

The CPU is interconnected with RTC and EEPROM through the I2C bus.

Through the above specific implementation methods, those skilled in the art can easily realize the utility model. However, it should be understood that the present utility model is not limited to the above two specific implementation manners. On the basis of the disclosed embodiments, those skilled in the art can arbitrarily combine different technical features, so as to realize different technical solutions.

Claims (5)

1. A CPU board based on a PCIE interface and a configurable switch, characterized in that it includes CPU, 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, clock chip, gold finger, CPU respectively It is interconnected with 2 PHY chips, Flash memory, RAM memory, JTAG interface, RTC, EEPROM, power supply, and clock chips. The CPU is connected to the 2 PHY chips through MII. The PCIE bus and UART bus are connected to the golden finger. 2. A kind of CPU board based on PCIE interface and configurable switch according to claim 1, it is characterized in that CPU is respectively connected to 2 PHY chips through SGMII. 3. a kind of CPU plate card based on PCIE interface and configurable switch according to claim 1, is characterized in that Flash memory is 2 Flash memory of 128M, all interconnects with CPU. 4. A kind of CPU plate card based on PCIE interface and configurable switch according to claim 1, characterized in that the RAM memory is 2 RAM memories of 256M, all interconnected with CPU. 5. A kind of CPU board based on PCIE interface and configurable switch according to claim 1, characterized in that CPU is interconnected with RTC and EEPROM by I2C bus.