CN1954510A - Apparatus and method for encoding and decoding block low density parity check codes with a variable coding rate - Google Patents

Abstract

An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code.

Description

Apparatus and method for encoding and decoding block low density parity check code with variable encoding rate

technical field

The present invention relates generally to a mobile communication system, and in particular to an apparatus and method for encoding and decoding a block Low Density Parity Check Code (LDPC) with a variable encoding rate.

Background technique

With the rapid development of mobile communication systems, it is necessary to develop a technology capable of transmitting bulk data approaching the capacity of a wired network even in a wireless environment. In order to meet the increasing demand for high-speed, large-capacity communication systems capable of processing and transmitting various data such as images and radio data in addition to voice-oriented services, it is necessary to The transmission efficiency of the system is increased to thereby improve the overall system performance. However, the mobile communication system inevitably generates errors during data transmission due to noise, interference, and fading according to channel conditions due to its characteristics. The generation of errors causes the loss of a large amount of information data.

In order to avoid the loss of information data due to the generation of errors, various error control schemes are currently used, and are based in part on channel characteristics, to thereby improve the reliability of mobile communication systems. The most typical error control schemes use error correcting codes.

FIG. 1 is a diagram illustrating the structure of a transmitter/receiver in a conventional mobile communication system. Referring to FIG. 1 , a transmitter 100 includes an encoder 111 , a modulator 113 and a radio frequency (RF) processor 115 , and a receiver 150 including a radio frequency processor 151 , a demodulator 153 and a decoder 155 .

In the transmitter 100, the transmission information data 'u' - if generated - is supplied to the encoder 111. The encoder 111 generates encoded symbols 'c' by encoding information data 'u' using a predetermined encoding scheme, and outputs the encoded symbols 'c' to the modulator 113. The modulator 113 generates a modulated symbol 's' by modulating the coded symbol 'c' using a predetermined modulation scheme, and outputs the modulated symbol 's' to an RF (Radio Frequency) processor 115 . The RF processor 115 radio-processes the modulated symbol 's' output from the modulator 113, and transmits the radio-processed signal through the air via the antenna ANT.

’来作为最后解码的信息数据。The signal transmitted over the air by the transmitter 100 in this way is received at the receiver 150 via its antenna ANT, and the signal received via said antenna is supplied to the radio frequency processor 151 . The RF processor 151 RF-processes the received signal, and outputs the RF-processed signal 'r' to the demodulator 153 . The demodulator 153 demodulates the radio frequency processed signal 'r' output from the radio frequency processor 151 using a demodulation scheme corresponding to the modulation scheme applied in the modulator 113, and outputs the demodulated signal 'x' to the decoder 155 . The decoder 155 decodes the demodulated signal 'x' output from the demodulator 153 using a decoding scheme corresponding to the encoding scheme applied in the encoder 111, and outputs the decoded signal 'x'

' as the last decoded information data.

In order for the receiver 150 to decode the information data 'u' transmitted by the transmitter 100 without error, a high-performance encoder and decoder are required. In particular, since the wireless channel environment should be considered due to the characteristics of the mobile communication system, more serious attention should be paid to errors that would occur due to the wireless channel environment.

The most typical error correction codes include turbo codes and LDPC (Low Density Parity Check, Low Density Parity Check) codes.

It is well known that turbo codes are superior in performance gain over convolutional codes traditionally used for error correction during high speed data transmission. The turbo code is beneficial in that it can effectively correct errors caused by noise generated in a transmission channel, thereby improving the reliability of data transmission. LDPC codes can be decoded using an iterative decoding algorithm based on a sum-product algorithm in a factor graph. Because the decoder for LDPC codes uses an iterative decoding algorithm based on the sum-product algorithm, it is less complex than the decoder for turbo codes. In addition, it is easy to implement a decoder for an LDPC code using a parallel processing decoder compared to a decoder for a turbo code.

Shannon's channel coding theorem states that reliable communication is possible only at data rates that do not exceed the channel capacity. However, Shannon's channel coding theorem does not propose a detailed channel coding/decoding method for supporting data rates up to the maximum signal capacity limit. In general, although a random code with a large block size shows performance close to the channel capacity limit of Shannon's channel coding theorem, when using the MAP (Maximum A Posteriori) or ML (Maximum Likelihood, maximum likelihood) decoding method, the actual It is impossible to implement the described decoding method due to its heavy computational load.

The turbo code was proposed by Berrou, Gjavieux and Thitimaishima in 1993. And show superior performance close to the channel capacity limit of Shannon's channel coding theorem. Proposal of turbo codes triggered active research on iterative decoding and graphical representation of codes, and LDPC codes proposed by Gallager in 1962 received new attention in the research. Cycles exist in the factor graphs of turbo codes and LDPC codes, and iterative decoding in factor graphs of LDPC codes in which cycles exist is known to be suboptimal. Moreover, it has been proved experimentally that LDPC codes have good performance through iterative decoding. LDPC codes known to have the highest performance so far show a difference of only about 0.04 [dB] in the channel capacity limit of Shannon's channel coding theorem with a bit error rate fBER) 10 ^-5 , using a block size of 10 ⁷ . In addition, although an LDPC code defined in a Galois Field (GF) with q>2 increases complexity in its decoding process, it is much superior in performance to a binary code. However, there is no satisfactory theoretical account of successful decoding by iterative decoding algorithms for LDPC codes defined in GF(q).

The LDPC code proposed by Gallager is defined by a parity check matrix in which main elements have a value of 0 and secondary elements other than elements with a value of 0 have values other than 0, such as a value of 1. In the following description, it will be assumed that non-zero values are 1 values.

For example, an (N, j, k) LDPC code is a linear block code with block length N and is defined by a sparse parity check matrix in which each column has j elements of value 1, Each row has k elements with value 1, and all elements except the one with value 1 have value 0.

An LDPC code in which the weight of each column in the parity check matrix is fixed to 'j' and the weight of each row in the parity check matrix is fixed to 'k' is called a "regular LDPC code" as described above. ". Here, the "weight" indicates the number of elements having a value other than 0 among elements constituting the parity check matrix. Unlike regular LDPC codes, LDPC codes in which the weight of each column in the parity check matrix and the weight of each row in the parity check matrix are not fixed are called "irregular LDPC codes". It is generally known that irregular LDPC codes are superior in performance to regular LDPC codes. However, in the case of irregular LDPC codes, since the weighting of each column and the weighting of each row in the parity check matrix are not fixed, that is, they are irregular, and therefore, must be correctly adjusted in the parity check matrix The weight of each column and the weight of each row in the parity check matrix in order to ensure the superior performance.

FIG. 2 is a diagram illustrating a parity check matrix of a conventional (8, 2, 4) LDPC code. Referring to FIG. 2 , the parity check matrix H of the (8,2,4) LDPC code consists of 8 columns and 4 rows, wherein the weight of each column is fixed to 2, and the weight of each row is fixed to 4. Since the weight of each column and the weight of each row in the parity check matrix are regular as described above, the (8, 2, 4) LDPC code illustrated in FIG. 2 becomes a regular LDPC code.

FIG. 3 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG. 2 . Referring to Fig. 3, the factor graph of (8, 2, 4) LDPC code is made up of 8 variable nodes and 4 check nodes, and described 8 variable nodes are x ₁ 300, x ₂ 302, x ₃ 304, x ₄ 306, x ₅ 308, x ₆ 310, x ₇ 312 and x ₈ 314, the four check nodes are 316, 318, 320 and 322. When the i-th row and the j-th column of the parity check matrix of the (8, 2, 4) LDPC code intersect with each other, there are elements with a value of 1, that is, non-zero values, at the variable node x _i and the j-th Branches are established between check nodes.

Since the parity check matrix of the LDPC code has a small weight as described above, it is possible to perform decoding by iterative decoding while continuously increasing the block length of the block code even in a block code having a long length , the block codes with longer lengths show performance close to the channel capacity limit of Shannon's channel coding theorem, such as turbo codes. MacKay and Neal have demonstrated that the iterative decoding process of LDPC codes using a streaming scheme approaches that of turbo codes in performance.

In order to generate a high-performance LDPC code, the following conditions should be satisfied.

(1) The cycle on the factor graph of the LDPC code should be considered

The term "cycle" refers to a cycle formed by edges connecting variable nodes to check nodes in the factor graph of the LDPC code, and the length of the cycle is defined as the number of edges constituting the cycle. A long cycle means that the number of edges connecting variable nodes to check nodes constituting the cycle in the factor graph of the LDPC code is large. On the contrary, a short cycle means that the number of edges connecting variable nodes to check nodes constituting a cycle in the factor graph of the LDPC code is small.

When the cycle in the factor graph of the LDPC code becomes longer, the performance efficiency of the LDPC code increases for the following reason. That is, when a long cycle is generated in the factor graph of the LDPC code, it is possible to prevent performance degradation such as an error floor that occurs when too many cycles having a short length exist on the factor graph of the LDPC code.

(2) Effective coding of LDPC codes should be considered

Compared with convolutional codes or turbo codes, LDPC codes are difficult to undergo real-time encoding because of their high encoding complexity. In order to reduce the coding complexity of LDPC codes, repetition accumulation (RA) codes have been proposed. However, RA codes also have limitations in reducing the encoding complexity of LDPC codes. Therefore, efficient encoding of LDPC codes should be considered.

(3) The degree distribution on the factor graph of the LDPC code should be considered

In general, irregular LDPC codes are superior in performance to regular LDPC codes because the factor graphs of irregular LDPC codes have various degrees. The term " degree " refers to the number of edges connected to variable nodes and check nodes in the factor graph of the LDPC code. Also, the phrase " degree distribution " of a group on a factor graph of an LDPC code refers to a ratio of the number of nodes having a certain degree to the total number of nodes. Richardson has demonstrated that LDPC codes with a specific degree distribution are superior in performance.

FIG. 4 is a diagram illustrating a parity check matrix of a conventional block LDPC code. Before giving the description of Fig. 4, it should be noted that block LDPC codes are new LDPC codes, for which not only efficient encoding but also efficient storage of parity check matrix and performance improvement are considered, and block LDPC codes are developed by generalizing LDPC codes that extend the structure of regular LDPC codes. Referring to FIG. 4, a parity check matrix of a block LDPC code is divided into a plurality of partial blocks, and a permutation matrix is mapped to each partial block. In FIG. 4, 'P' represents a permutation matrix having a size of N _s ×N _s , and the superscript (or index) a _pq of the permutation matrix P is 0≤a _pq ≤N _s −1 or a _pq =∞.

In addition, 'p' indicates that the corresponding permutation matrix is located in the pth row of the partial block of the parity check matrix, and 'q' indicates that the corresponding permutation matrix is located in the qth column of the partial block of the parity check matrix. That is, p ^apq represents a permutation matrix located in a partial block in which p-th row and q-th column of a parity check matrix composed of a plurality of partial blocks intersect with each other. That is, 'p' and 'q' distributions represent the number of rows and the number of columns of partial blocks corresponding to the information part in the parity check matrix.

FIG. 5 is a diagram illustrating a permutation matrix P of FIG. 4 . As shown in Fig. 5, the permutation matrix P is a square matrix having a size of N _s ×N _s , each of the N _s columns constituting the permutation matrix P has a weight of 1, and each of the N _s rows constituting the permutation matrix P Also has a weight of 1. Here, although the size of the permutation matrix is expressed as N _s ×N _s , it can also be expressed as N _s because the permutation matrix P is a square matrix.

In Fig. 4, the permutation matrix P with the superscript a _pq = 0, that is, the permutation matrix P ⁰ , represents the unit matrix I _Ns×Ns , and the permutation matrix P with the superscript a _pq = ∞, that is, the permutation matrix P ^∞ , represents 0 matrix. Here, I _Ns×Ns denotes an identity matrix having a size of N _s ×N _s .

In the entire parity check matrix of the block LDPC code illustrated in FIG. 4, since the total number of rows is N _s ×p and the total number of columns is N _s ×q (for p≤q), when the entire parity check matrix of the LDPC code When the empirical matrix has full rank, the coding rate can be expressed as equation (1) regardless of the size of the partial block:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

If a _pq ≠∞ for all p and q, the permutation matrix corresponding to the partial block is not a 0 matrix, and the partial block constitutes a regular LDPC code, wherein, in each permutation matrix corresponding to the partial block The weighted value of each column and the weighted value of each row in are p and q, respectively. Here, each permutation matrix corresponding to a partial block is called a "partial matrix".

Since there are (p-1) associated rows in the entire parity check matrix, the encoding rate is greater than that calculated by Equation (1). In the case of a block LDPC code, if the weighted position of the first row of each partial matrix constituting the entire parity check matrix is determined, the weighted position of the remaining (N _s −1) rows can be determined. Therefore, the size of the required memory is reduced to 1/N _s compared to the case of irregularly selecting weights to store information on the entire parity check matrix.

As mentioned above, the term "cycle" refers to a cycle formed by edges connecting variable nodes to check nodes in the factor graph of an LDPC code, and the length of the cycle is defined as the number of edges constituting the cycle .Long circulation means that the number of edges that connect variable nodes to check nodes that constitute the loop in the factor graph of LDPC codes is large.When the cycle in the factor graph of LDPC codes becomes long, the performance efficiency of LDPC codes improve.

On the contrary, when the cycle in the factor graph of the LDPC code is shortened, the error correction capability of the LDPC code is lowered because performance deterioration such as error floor occurs. That is, when there are a plurality of cycles with a short length in the factor graph of the LDPC code, after a small number of iterations, information about a specific node from which a cycle with a short length belongs is returned. When the number of iterations increases, the information is returned to the corresponding node more frequently, and thus the information cannot be updated correctly, thereby causing deterioration in the error correction capability of the LDPC code.

FIG. 6 is a diagram illustrating a cyclic structure of a block LDPC code whose parity check matrix is composed of 4 partial matrices. Before giving a description of FIG. 6, it should be noted that block LDPC codes are new LDPC codes for which not only efficient encoding but also efficient storage of parity check matrices and performance improvement are considered. The block LDPC code is also an LDPC code extended by generalizing the structure of a regular LDPC code. The parity check matrix of the block LDPC code illustrated in FIG. 6 includes 4 partial blocks, the diagonal lines indicate where elements having a value of 1 are located, and the parts other than the diagonal line indicate where elements having a value 0 are located. location. In addition, 'P' represents the same permutation matrix as that described in connection with FIG. 5 .

In order to analyze the cyclic structure of the block LDPC code illustrated in Fig. 6, the element with the value 1 in the i-th row of the permutation matrix P ^a is defined as a reference element, and the element with the value 1 in the i-th row is called as "0 point". Here, "partial matrix" refers to a matrix corresponding to a partial block. The 0 point is located in the i+ath column of the partial matrix P ^a .

An element having a value of 1 in the partial matrix P ^b located in the same row as the 0 point is referred to as "1 point". For the same reason as the 0 point, the 1 point is located in the i+bth column of the partial matrix ^Pb .

Next, an element having a value of 1 in the partial matrix ^Pc located in the same column as the 1 point is referred to as "2 point". Since the partial matrix ^Pc is a matrix obtained by shifting the corresponding column of the identity matrix I to the right by c relative to the modulo _Ns , the 2 points are located in the i+bc-th row of the partial matrix ^Pc .

In addition, an element having a value of 1 in the partial matrix ^Pd located in the same row as the 2 points is referred to as "3 points". The 3 points are located in the i+b-c+d column of the partial matrix ^Pd .

Finally, the element with the value 1 in the partial matrix P ^a located in the same column as the 3 points is called "4 points". The 4 points are located in the i+b-c+da row of the partial matrix P ^a .

In the cycle structure of the LDPC code illustrated in FIG. 6, if a cycle having a length of 4 exists, 0 points and 4 points are located at the same position. That is, the relationship between the 0 point and the 4 point is defined by Equation (2).

$\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&cong;</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; mod</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; or</span>}$

$\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; \&cong;</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; mod</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; )</span>$

..........(2)

Equation (2) can be rewritten as Equation (3)

$\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; \&cong;</span>\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; mod</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

As a result, when the relationship of Equation (3) is satisfied, a cycle having a length of 4 is generated. In general, when the 0 point and the 4p point are first identical to each other, the relation is given $i\&cong;i+p(b-c+d-e)\left(\mathrm{mod}{N}_{\mathrm{the\; s}}\right)$ , and satisfies the following relationship shown in Equation (4).

$\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&cong;</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; mod</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In other words, if the positive integer having the smallest value among the positive integers satisfying Equation (4) corresponding to given a, b, c, and d is defined as 'p', the cycle with length 4p becomes The cycle with the minimum length in the cycle structure of the block LDPC code illustrated in .

In conclusion, as mentioned above, for (a-b+cd)≠0, if gcd(N _s , a-b+cd)=1 is satisfied, then p=N _s . Here, gcd(N _s , a-b+cd) is a function for calculating the "greatest common divisor" of integers N _s and a-b+cd. Therefore, the cycle with length 4N _s becomes the cycle with minimum length.

The Richardson-Urbanke technique is used as an encoding technique for block LDPC codes. Because the Richardson-Urbanke technique is used as the encoding technique, the complexity of encoding can be minimized because the form of the parity check matrix becomes similar to that of a full lower triangular matrix.

FIG. 7 is a diagram illustrating a parity check matrix having a form similar to that of an all-lower triangular matrix. The parity check matrix illustrated in FIG. 7 is different in the form of the parity part from the parity check matrix having the form of an all lower triangular matrix. In FIG. 7, the superscript (or index) a _pq of the permutation matrix P of the information part is _{0≤apq≤Ns -} 1 or _apq =∞, as described above. The permutation matrix P with the superscript a _pq = 0 in the information part, that is, the permutation matrix P ⁰ , represents the unit matrix I _Ns×Nx , and the permutation matrix P with the superscript a _pq = ∞, that is, the permutation matrix P ^∞ represents 0 matrix. In FIG. 7, 'p' represents the number of rows of partial blocks mapped to the information part, and 'q' represents the number of columns of partial blocks mapped to the parity part. Also, the superscripts a _p , x, and y of the permutation matrix P mapped to the parity part represent indices of the permutation matrix. However, for convenience of illustration, different superscripts a _p , x and y are used to distinguish the parity part from the information part. That is, in FIG. 7, P ^a1 and P ^ap are also permutation matrices, and the superscripts a ₁ -a _p are sequentially indexed to the partial matrices located in the diagonal parts of the odd and even parts. In addition, P ^x and P ^y are also permutation matrices, and for convenience of explanation, they are indexed differently to distinguish the parity part from the information part. If the block length of the block LDPC code having the parity check matrix illustrated in FIG. 7 is assumed to be N, the encoding complexity of the block LDPC code increases linearly with respect to the block length N(0(N)).

The biggest problem with LDPC codes with the parity check matrix of Fig. 7 is that if the length of a partial block is defined as N _s , N _s check nodes whose degree in the factor graph of the block LDPC code is always 1 are generated. A check node with degree 1 cannot affect the performance improvement based on iterative decoding. Therefore, standard irregular LDPC codes based on the Richardson-Urbanke technique do not include check nodes with degree 1. Therefore, the parity check matrix of FIG. 7 is assumed as a basic parity check matrix in order to design the parity check matrix such that it enables efficient encoding while not including a check node having degree 1. In the parity check matrix of FIG. 7 constituted by partial matrices, the selection of partial matrices is a very important factor for performance improvement of block LDPC codes, so finding an appropriate selection criterion of the partial matrices also becomes an important factor.

For the convenience of the method for designing the parity check matrix of the block LDPC code and the method for encoding the block LDPC code, the parity check matrix illustrated in FIG. 7 is assumed to use 6 partial matrices as illustrated in FIG. 8 form.

FIG. 8 is a diagram illustrating the parity check matrix of FIG. 7, which is divided into 6 partial blocks. Referring to FIG. 8, the parity check matrix of the block LDPC code illustrated in FIG. 7 is divided into an information part 's', a first parity part _p1 , and a second parity part _p2 . Like the information part described in conjunction with FIG. 7, the information part 's' represents a part of the parity check matrix that is mapped to the actual information word during the process of encoding the block LDPC code, but for the convenience of illustration, the information part 's ' is represented as a different reference letter. Like the parity part described in conjunction with FIG. 7, the first parity part _p1 and the second parity part _p2 represent a part of the parity check matrix that is mapped to the actual parity during the processing of the encoding block LDPC code, and the parity Section is divided into two parts.

Partial matrices A and C correspond to partial blocks A (802) and C (804) of the information part 's', partial matrices B and D correspond to partial blocks B (806) and D (808) of the first parity part _p1 , Partial matrices T and E correspond to partial blocks T (810) and E (812) of the second parity part _p2 . Although the parity check matrix is divided into 7 partial blocks in FIG. 8, it should be noted that '0' is not an independent partial block, and because the partial matrix T corresponding to the partial block T (810) has a full lower triangular form, Therefore, an area in which a matrix of 0 is arranged on a diagonal basis is represented as '0'. The process of simplifying the encoding method using the partial matrix of the information part 's', the first parity part _p1 and the second parity part _p2 will be explained later with reference to FIG. 10 .

FIG. 9 is a diagram illustrating a transpose matrix of the partial matrix B shown in FIG. 8 , a partial matrix E, a partial matrix T, and an inverse matrix of the partial matrix T in the parity check matrix of FIG. 7 . Referring to FIG. 9 , the partial matrix B ^T represents the transpose matrix of the partial matrix B, and the partial matrix T ⁻¹ represents the inverse matrix of the partial matrix T. P ^(k1～k2) means $\underset{i=k_i}{\overset{k_2}{\mathrm{\&Pi;}}}{P}^{a_1}=P^{\underset{i=k_1}{\overset{k_2}{\mathrm{\&Sigma;}}}{a}_i}.$ The permutation matrix illustrated in Fig. 9, eg P ^a1 , may be an identity matrix. As mentioned above, if the superscript of the permutation matrix, i.e. _a1, is 0, then p ^a1 will be the identity matrix. Also, if the superscript of the permutation matrix, ie, _a1, increases by a predetermined value, the permutation matrix is cyclically shifted by the predetermined value, therefore, the permutation matrix p ^a1 will be the identity matrix.

FIG. 10 is a flowchart illustrating a procedure for generating a parity check matrix of a conventional block LDPC code. Before giving the description of Figure 10, it should be noted that in order to generate a block LDPC code, the codeword size and coding rate of the block LDPC code to be generated must be determined, and the parity must be determined according to the determined codeword size and coding rate the size of the matrix. If the codeword size of the block LDPC code is denoted as N and the encoding rate is denoted as R, the size of the parity check matrix becomes N(1-R)×N. Actually, the procedure for generating the parity check matrix of the block LDPC code illustrated in FIG. The parity check matrix of .

Referring to FIG. 10, in step 1011, the controller divides the parity check matrix having a size of N(1-R)×N into a total of p×q blocks, including p blocks on the horizontal axis and on the vertical axis q blocks, and then proceed to step 1013. Since each block has a size of N _s ×N _s , the parity check matrix includes N _s ×p columns and N _s ×q rows. In step 1013, the controller divides the p×q blocks divided from the parity check matrix into an information part 's', a first parity part _p1 and a second parity part _p2 , and then proceeds to steps 1015 and 1021.

In step 1015, the controller divides the information part 's' into non-zero blocks or non-zero matrices and zero blocks or zero matrices according to the degree of distribution for ensuring good performance of the block LDPC code, and then proceeds to step 1017. Since the degree of distribution for ensuring good performance of the block LDPC code has been described above, a detailed description thereof is omitted here. In step 1017, the controller determines the permutation matrix p ^apq in the non-zero matrix part in the block with a low degree in the block determined according to the degree of distribution for ensuring good performance of the block LDPC code, so as to maximize the block as described above The minimum loop length of the loop, and then proceed to step 1019. The permutation matrix should be determined according to a block cycle considering not only the information part 's' but also the first parity part _p1 and the second parity part _p2 .

In step 1019, the controller randomly determines the permutation matrix p ^apq in the non-zero matrix part in the block with a low degree in the block determined according to the degree of distribution for ensuring good performance of the block LDPC code, and then ends the procedure . Even when determining the permutation matrix p ^apq to be applied to non-zero matrix parts in a block with a height number, the permutation matrix p ^apq must be determined so as to maximize the minimum cycle length of the block cycle and according to not only the information part 's' Also the permutation matrix p ^apq is determined taking into account the block cycles of the first parity part p ₁ and the second parity part p ₂ . An example of the permutation matrix P ^apq arranged in the information section 's' of the parity check matrix is illustrated in FIG. 7 .

In step 1021 , the controller divides the first parity part p ₁ and the second parity part p ₂ into 4 part matrices B, T, D and E, and then proceeds to step 1023 . In step 1023 , the controller inputs non-zero permutation matrices P ^y and P ^a1 into two partial blocks among the partial blocks constituting the partial matrix B, and then proceeds to step 1025 . The structure for inputting the non-zero permutation matrices P ^y and p ^a1 to 2 sub-blocks among the sub-blocks constituting the sub-matrix B has been described with reference to FIG. 9 .

In step 1025, the controller inputs the identity matrix I to the diagonal sub-block of the sub-matrix T, and inputs a specific permutation matrix p ^a2 to the (i, i+1)th sub-block under the diagonal component of the sub-matrix T, P ^a3 , . . . , P ^am-1 , then go to step 1027. The method for inputting the identity matrix I to the diagonal sub-blocks of the sub-matrix T and inputting a specific permutation matrix to the (i, i+1)-th sub-block under the diagonal components of the sub-matrix T has been described with reference to FIG. 9 Structures of P ^a2 , P ^a3 , . . . , P ^am-1 .

In step 1027 , the controller inputs the partial matrix P ^x into the partial matrix D, and then proceeds to step 1029 . In step 1029, the controller only inputs the permutation matrix P ^am to the last partial block in the partial matrix E, and ends the procedure. The structure for inputting the 2 permutation matrices P ^am only to the last partial block among the partial blocks constituting the matrix E has been described with reference to FIG. 9 .

Contents of the invention

As mentioned above, known LDPC codes and turbo codes have high performance gains during high-speed data transmission, and can effectively correct errors caused by noise in the transmission channel, which is beneficial to improving the reliability of data transmission. However, LDPC codes are disadvantageous in coding rate. Among currently available LDPC codes, major LDPC codes have a coding rate of 1/2, and only the smallest LDPC codes have a coding rate of 1/3. The limitation on the coding rate exerts a fatal influence on high-speed, large-capacity data transmission. Although a density evolution scheme can be used to calculate the degree distribution for representing the best performance in order to achieve a lower coding rate for LDPC codes, it is difficult to realize an LDPC code with a degree distribution representing the best performance due to various constraints, which Some constraints such as loop structures in factor graphs and hardware implementations.

With the development of mobile communication systems, various schemes such as hybrid automatic repeat request (HARQ) and adaptive adaptation and coding (AMC) are used to improve resource efficiency. In order to use the HARQ and AMC schemes, the LDPC code should be able to support various coding rates. but. Since the LDPC code has limitations in the coding rate as described above, it is difficult for the LDPC code to support various coding rates.

In addition, the network uses a HARQ scheme, and an encoder must be used to create LDPC codes with various encoding rates. Therefore, there is a need for a scheme capable of creating LDPC codes with various coding rates using one encoder.

Accordingly, an object of the present invention is to provide an apparatus and method for encoding and decoding an LDPC code having a variable encoding rate in a mobile communication system.

Another object of the present invention is to provide an apparatus and method for encoding and decoding an LDPC code with a variable encoding rate whose encoding complexity is minimized in a mobile communication system.

According to one aspect of the present invention, there is provided a method for encoding a block Low Density Parity Check (LDPC) code having a variable encoding rate. The method includes the steps of: receiving an information word; and, according to a coding rate to be applied to a block LDPC code when generating the information word, converting the information word based on one of a first parity check matrix and a second parity check matrix Information words are coded as said block LDPC codes.

According to another aspect of the present invention, an apparatus for encoding a block Low Density Parity Check (LDPC) code having a variable encoding rate is provided. The apparatus includes an encoder for encoding the information word based on one of a first parity check matrix and a second parity check matrix according to a coding rate to be applied to a block LDPC code when generating the information word as the block LDPC code; a modulator for modulating the block LDPC code into modulated symbols using a modulation scheme; and a transmitter for transmitting the modulated symbols.

According to another aspect of the present invention, a method for decoding a block Low Density Parity Check (LDPC) code having a variable coding rate is provided. The method includes the steps of: receiving a signal; determining one of a first parity check matrix and a second parity check matrix according to a coding rate of a block LDPC code to be decoded; and decoding the received parity check matrix according to the determined parity check matrix signal in order to detect the LDPC code.

According to another aspect of the present invention, an apparatus for decoding a block Low Density Parity Check (LDPC) code having a variable coding rate is provided. The apparatus includes: a receiver for receiving a signal; and a decoder for determining one of a first parity check matrix and a second parity check matrix according to a coding rate of a block LDPC code to be decoded, and according to the The determined parity check matrix is used to decode the received signal in order to detect the block LDPC code.

Description of drawings

The above and other objects, features and advantages of the present invention will become clearer through the following detailed description in conjunction with the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating a transmitter/receiver in a conventional mobile communication system;

2 is a diagram illustrating a parity check matrix of a conventional (8, 2, 4) LDPC code;

FIG. 3 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG. 2;

4 is a diagram illustrating a parity check matrix of a conventional block LDPC code;

FIG. 5 is a diagram illustrating the permutation matrix P of FIG. 4;

6 is a diagram illustrating a cyclic structure of a block LDPC code whose parity check matrix includes 4 partial matrices;

FIG. 7 is a diagram illustrating a parity check matrix having a form similar to that of an all-lower triangular matrix;

FIG. 8 is a diagram illustrating the parity check matrix of FIG. 7 divided into 6 partial blocks;

9 is a diagram illustrating a transpose matrix of a partial matrix B, a partial matrix E, a partial matrix T, and an inverse matrix of a partial matrix T illustrated in FIG. 8;

10 is a flowchart illustrating a procedure for generating a parity check matrix of a conventional block LDPC code;

11 is a diagram illustrating a process of generating a parity check matrix using a shortening scheme according to one embodiment of the present invention;

12 is a diagram illustrating a process of generating a parity check matrix using a removal scheme according to one embodiment of the present invention;

13 is a diagram illustrating a process of generating a parity check matrix using a puncturing scheme according to one embodiment of the present invention;

14A-14D are diagrams for explaining the roles of punctured parity nodes in the decoding process of a codeword of a block LDPC code generated using a puncturing scheme according to an embodiment of the present invention;

15 is a diagram illustrating a process for generating a parity check matrix using a shortening scheme according to one embodiment of the present invention;

FIG. 16 is a diagram illustrating a parity check matrix of a variable coding rate block LDPC code according to an embodiment of the present invention;

FIG. 17 is a flowchart illustrating the process of encoding a variable encoding rate block LDPC code according to one embodiment of the present invention;

FIG. 18 is a block diagram illustrating an internal structure of a device for encoding a variable coding rate block LDPC code according to an embodiment of the present invention;

FIG. 19 is a block diagram illustrating an internal structure of a device for decoding variable coding rate block LDPC codes according to an embodiment of the present invention;

FIG. 20 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention;

21 is a diagram illustrating an internal structure of an encoding device for a variable encoding rate block LDPC code according to another embodiment of the present invention;

FIG. 22 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention;

FIG. 23 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention;

FIG. 24 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention;

FIG. 25 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention.

Detailed ways

Several preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for brevity.

The present invention proposes an apparatus and method for encoding and decoding a block Low Density Parity Check (LDPC) code with a variable encoding rate (hereinafter referred to as "variable encoding rate block LDPC code"). That is, the present invention proposes an apparatus and method for encoding and decoding a variable coding rate block LDPC code, wherein the length of the minimum cycle in the factor graph of the block LDPC code is maximized, and the length of the minimum cycle of the block LDPC code is minimized. Coding complexity, the degree distribution in the factor graph of the block LDPC code has an optimal value of 1, and supports variable coding rates. Although not independently described in the specification, the encoding and decoding apparatus for a variable encoding rate block LDPC code according to the present invention can be applied to the transmitter/receiver described with reference to FIG. 1 .

The next-generation mobile communication system has evolved into a packet service communication system, and the packet service communication system, which is a system for transmitting burst packet data to a plurality of mobile stations, has been designed to be suitable for large-capacity data transmission. In order to improve data throughput, a hybrid automatic repeat request (HARQ) scheme and an adaptive modulation and coding (AMC) scheme have been proposed. Since the HARQ scheme and the AMC scheme support variable coding rates, block LDPC codes supporting variable coding rates are required.

Like the design of traditional LDPC codes, the design of variable coding rate block LDPC codes is realized by designing the parity check matrix. However, in a mobile communication system, in order to provide a CODEC (codec) for variable coding rate block LDPC codes, that is, to provide block LDPC codes with various coding rates, the parity check matrix should include the The parity check matrix of the block LDPC code of rate. That is, one parity check matrix must be used to support at least two coding rates.

In the present invention, schemes for supporting at least two coding rates using one parity check matrix include a shortening scheme, a removing scheme, and a puncturing scheme. The shortening, removal and puncturing schemes are now explained.

The shortening scheme reduces the coding rate by fixing the number of rows in the parity check matrix and reducing the number of columns mapped to information words. The shortening scheme is used to obtain various coding rates for various codeword lengths.

FIG. 11 is a diagram illustrating a process for generating a parity check matrix using a shortening scheme according to one embodiment of the present invention. Referring to Fig. 11, H _i (R _i , N _i , K _i ) represents the parity check matrix of a block LDPC code with coding rate R _i , code word length N _i and information word length K _i , where i<j, N _i >N _j and K _i >K _j . It can be assumed that the first (K ₁ -K ₂ ) information bits of the (R ₁ , N ₁ , K ₁ )-block LDPC code are all fixed to 0, and it can only be deduced that the corresponding parity check matrix H ₁ ( R ₁ , N ₁ , K ₁ ) block LDPC code (hereinafter referred to as "(R ₁ , N ₁ , K ₁ )-block LDPC code") is changed to correspond to the parity check matrix H ₂ (R ₂ , N ₂ , K ₂ ) block LDPC code (hereinafter referred to as "(R ₂ , N ₂ , K ₂ )-block LDPC code") processing. Moreover, (R 1 , N 1 , K 1 ) can be simply generated by fixing all the preceding (K ₁ -K _i ) information bits of the ( _R1 , _N1 , _K1 )-block LDPC code to 0 - Block LDPC codes instead of (R2, N2, K2)-block LDPC codes.

Therefore, in an operation of generating a parity check matrix using the shortening scheme described above with reference to FIG. 11 , the coding rate of the corresponding block LDPC code can be expressed as shown in Equation (5).

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="N"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">N</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

For i<j, equation (5) can be expressed as shown in equation (6).

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span>}$

$<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span>}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; ></span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

It can be seen from Equation (6) that the coding rate obtained when the shortening scheme is used to generate the parity check matrix is lowered.

Assuming that the parity check matrix H ₁ (R ₁ , N ₁ , K ₁ ) has full rank in FIG. 11 , even if the parity check matrix is generated using the shortening scheme, the rows in the parity check matrix generated using the shortening scheme The number also remains constant. Therefore, the information word length is shortened while the parity check matrix remains unchanged, thereby reducing the coding rate. In general, if a column mapped to a parity part is removed from a predetermined parity check matrix, the resulting codeword set is completely different from that generated when the column mapped to the parity part is not removed. Therefore, the shortening scheme has the rationale of removing columns that are mapped to information words.

The removal scheme reduces the coding rate by fixing the number of columns and increasing the number of rows in the parity check matrix. Here, increasing the number of rows in the parity check matrix signifies increasing the number of check equations that should be satisfied by the codeword. Increasing the number of check equations reduces the number of codewords that satisfy the check equations. Hence, the "removal scheme" is so named because it removes codewords from the reference codeword set that cannot satisfy the check equation that increases due to the increase in the number of rows in the parity check matrix.

FIG. 12 is a diagram illustrating a process of generating a parity check matrix using a removal _scheme according to an embodiment of the present invention. Referring to FIG. 12, H _i (R _i , N) represents the Parity check matrix for block LDPC codes. Assuming that each parity check matrix has a full rank M _i in FIG. 12 , the encoding rate of a code generated for each parity check matrix can be expressed as shown in Equation (7).

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

As shown in equation (7), in general, the full rank M _i increases for 'i', resulting in a decrease of R _i . Alternatively, it is also possible to generate a parity check matrix with a high coding rate using a scheme that, unlike the removal scheme, has a very low value such as H ₄ (R ₄ , N) illustrated in FIG. 12 Coding rate parity check matrix to remove rows.

The puncturing scheme increases the coding rate by sending only a part of the generated parity instead of sending all the parity generated from the encoder as in the case of turbo codes. The puncturing scheme can also be considered unchanged in the parity check matrix, although it does not transmit all generated parity. Therefore, the puncturing scheme is different from a scheme of deleting or increasing columns and rows of a parity check matrix, like a shortening scheme or a removal scheme.

FIG. 13 is a diagram illustrating a process of generating a parity check matrix using a puncturing scheme according to one embodiment of the present invention. Referring to FIG. 13, a parity check matrix of a (N, K)=(1720, 860) block LDPC code having a coding rate 1/2 includes 20×40 partial blocks. The partial matrix corresponding to each of the partial blocks is a square matrix whose size is N _s ×N _s =43×43.

When a code word of a block LDPC code is divided into an information word and a parity word, the information word and the parity word may also be divided for each partial block. Therefore, the codeword of the block LDPC code can be expressed as shown in Equation (8).

c = ( u ₁ , u ₂ ,..., u ₂₀ _ p ₁ , p ₂ ,..., p ₂₀ ) ..........(8)

In Equation (8), u _i and p _i represent row vectors of size 1×43.

If an even block is punctured from the parity part in the parity check matrix illustrated in FIG. 13 , as shown in Equation (9), a codeword of a block LDPC code obtained by puncturing is expressed.

c _punc ＝( u ₁ , u ₂ ,..., u ₂₀ _ p ₁ , p ₃ , p ₅ ,..., p ₁₇ , p ₁₉ ) ..........(9)

In Equation (9), c _punc represents a codeword of a block LDPC code obtained by puncturing. As shown in Equation (9), the codeword becomes equal to the codeword of the block LDPC code having a coding rate of 2/3. That is, the use of the puncturing scheme changes the coding rate, but maintains the length of the information word.

In the process of decoding a codeword of a block LDPC code generated using the puncturing scheme, the original parity check matrix is used by considering punctured parity bits as eliminated bits. That is, if a log-likelihood ratio (LLR) value input from a channel transmitting punctured parity bits is always regarded as '0', the original parity check matrix may be used during decoding. Therefore, the puncturing node corresponding to parity never affects performance improvement or performance degradation due to iterative decoding in the decoding process, and serves only as a path through which messages sent from other nodes pass.

14A-14D are diagrams for illustrating roles of nodes corresponding to parity of puncturing in a decoding process of a codeword of a block LDPC code generated using a puncturing scheme according to one embodiment of the present invention. However, before describing FIGS. 14A-14D , the _ denotation illustrated in FIGS. 14A-14D corresponds to the truncation node thereafter, and the arrow indicates the direction in which the message is actually transmitted.

Referring to FIG. 14A, the LLR value '0' is input to the punctured parity node. Thereafter, in the first decoding process illustrated in FIG. 14B , the message input from the channel illustrated in FIG. 14A is supplied to the check node. In FIG. 14B, a variable node corresponding to parity is provided to a check node connected to an input message, ie, a symbol probability value. A variable node corresponding to parity provides an LLR value '0' to a connected check node.

The check node calculates a probability value to be provided to each variable node by performing a predetermined operation using the probability value input from the variable node connected to the check node, and supplies the calculated probability value to the corresponding variable node . The messages supplied to all nodes connected to the variable nodes corresponding to the parity punctured from the check node become '0', as shown in FIG. 14C. In addition, the messages supplied to the punctured variable nodes corresponding to parity are not '0', and the messages supplied to the punctured variable nodes corresponding to parity are independently supplied through their own paths , without affecting each other, as shown in Figure 14D. The following decoding process is the same as the conventional decoding process of the LDPC code, and the punctured variable nodes corresponding to parity discontinuously affect performance improvement due to decoding, and serve only as a transmission path of a message.

As mentioned above, in the puncturing scheme, an original encoder and decoder can be used for encoding and decoding. That is, in the puncturing scheme, encoding complexity and decoding complexity are almost constant regardless of encoding rate and block (codeword) length, information word length is fixed, and encoding rate is changed by changing only parity length. Therefore, the puncturing scheme has high reliability. Since a block LDPC code generated using a puncturing scheme varies in performance according to its puncturing pattern, the design of the puncturing pattern serves as an important factor.

Next, a method for actually generating a block LDPC code using the shortening scheme and the puncturing scheme is explained in detail. Like traditional block codes, block LDPC codes can also use a shortening scheme to change their coding rate. Therefore, an embodiment of the present invention uses a shortening scheme to change the coding rate of a block LDPC code.

FIG. 15 is a diagram illustrating a process of generating a parity check matrix using a shortening scheme according to one embodiment of the present invention. Referring to Fig. 15, if u ₆ , u ₇ ,..., u ₁₃ , u ₁₇ , u ₁₈ of the code word c of the block LDPC code corresponding to the parity check matrix described in Fig. 13 are all regarded as ' 0 ' , then yields the illustrated parity check matrix. The shortening scheme differs from the puncturing scheme because it removes part of the information portion from the parity check matrix. That is, because the parity check matrix generated by using the shortening scheme has a completely different encoding rate and degree of distribution from the initially provided parity check matrix, it must be based on the degree of distribution of the parity check matrix generated by using the shortening scheme to select the columns to remove from the initially provided parity check matrix. Therefore, the parity check matrix must be generated so that the parity check matrix initially given before using the shortening scheme, that is, the parent parity check matrix and the parity check matrix obtained after using the shortening scheme, that is, the child parity check matrix are both It is possible to have an optimized degree distribution.

In general, in the case of a limited length, a block LDPC code with a high coding rate showing high performance is larger in the average degree of a check code than a block LDPC code with a low coding rate showing high performance. Therefore, in order to use the shortening scheme to generate a block LDPC code with a low coding rate, it is necessary to reduce the average degree of a check node after using the shortening scheme.

In addition, because the use of the shortening scheme changes the degree distribution, in order to use the density evolution analysis scheme to design a variable coding rate block LDPC code with a good noise threshold, the degree distribution of the parent parity check matrix and the degree distribution of the use of the shortening scheme must be considered. The degree distribution of the sub-parity-check matrix. However, the puncturing scheme considers that the fenced variable nodes have been eliminated, rather than actually removing the fenced variable nodes. Therefore, the puncturing scheme can generate a block LDPC code with a high encoding rate without causing a change in the degree distribution of the parity check matrix as a whole.

Next, a method for generating a block LDPC code capable of supporting various coding rates, that is, variable coding rates using one parity check matrix, that is, a parent parity check matrix, will be described. Here, a block LDPC code with a fixed codeword length and a variable coding rate is explained. In addition, a method for generating a block LDPC code whose coding rate can be changed from 1/3 to 1/2 using a shortening scheme and a puncturing scheme will be explained as its block length, that is, a codeword An example of a fixed-length variable-rate block LDPC code, the method also allows a good noise threshold for the parent parity-check matrix and the child parity-check matrix generated from the parent parity-check matrix using a shortening scheme.

FIG. 16 is a diagram illustrating a parity check matrix of a variable coding rate block LDPC code according to one embodiment of the present invention. Referring to FIG. 16 , the illustrated parity check matrix includes 49 partial block columns and 28 partial block rows, and a partial matrix of size N _s ×N _s is mapped to each partial block constituting the parity check matrix. Here, the "partial matrix" means a variable coding rate block LDPC code mapped to each partial block, and the size of the partial block is N _s means a square matrix in which the partial matrix has a size of N _s ×N _s . Here, it should be noted that the size of the partial matrix is expressed by N _s ×N _s or N _s .

The coding rate of the parity check matrix illustrated in FIG. 16 can be expressed as shown in Equation (10).

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 49</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 28</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}{\mathrm{<span\; class="notranslate">\; 49</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

That is, the parity check matrix illustrated in FIG. 16 can be used as a block LDPC code with a coding rate of 3/7 and a codeword length of 49N, or a parity check matrix of a variable coding rate block LDPC code can be generated using Parity check matrix for shortening scheme or puncturing scheme. For example, a block LDPC code with a coding rate of 1/2 and a codeword length of 42N _s can be generated by using a shortening scheme to shorten the first partial block column to the seventh partial block column, corresponding to the eighth The partial matrices of the partial block column to the 21st partial block column are mapped to information words, and the partial matrices corresponding to the 22nd to 49th partial block column are mapped to parity.

As another example, a block LDPC code with a coding rate of 1/2 and a codeword length of 42N _s can be generated by mapping the partial matrices corresponding to the 1st partial block column to the 21st partial block column to the information words, and use the puncturing scheme to puncture the 7 sub-block columns in the 22nd sub-block column to the 49th sub-block column. In the above-mentioned example, it is possible to use the shortening scheme or the puncturing scheme to generate a plurality of block LDPC codes which are equal to each other in actual codeword length but different from each other in coding rate.

The most important factor that should be considered in generating block LDPC codes supporting variable coding rates is to design such that not only the parent parity check matrix but also the child parity check matrix should be good in noise threshold performance. Therefore, the degree distribution is optimized for the parity check matrix of the block LDPC code with a low coding rate, and the parity check matrix of the block LDPC code with a high coding rate is generated so that it includes the optimized parity check matrix, and the degree distribution is optimized .

That is, the parity check matrix illustrated in FIG. 16 can be generated by optimizing the degree of distribution of the parity check matrix of a block LDPC code having a coding rate of 1/3, and again lower than the parity check matrix including the optimization The check matrix and the parity check matrix of the block LDPC code with a coding rate 3/7 perform degree distribution optimization. In Fig. 16, for the convenience of designing the parity check matrix, the degree of variable nodes is limited to 4 types, namely 2, 3, 5 and 16, and the degrees of check nodes are limited to 3 types, namely 5, 6 and 7.

In Fig. 16, for the shortened block LDPC code with coding rate 1/3, the noise threshold is σ ^* =1.256(-0.219[dB]), and for the block LDPC code with coding rate 3/7, the noise threshold is σ ^* = 1.066 (0.114 [dB]), and the degree distribution of the block LDPC code is as follows (for the block LDPC code, Shannon limits are -0.495 [dB] and -0.122 [dB]).

- Degree distribution of shortened block LDPC codes with code rate 1/3:

λ ₂ =0.348, λ ₃ =0.174, λ ₅ =0.065, λ ₁₆ =0.413;

ρ ₅ =0.419, ρ ₆ =0.581

- Degree distribution of a block LDPC code with code rate 3/7:

λ ₂ =0.280, λ ₃ =0.202, λ ₅ =0.104, λ ₁₆ =0.414;

ρ ₆ =0.093

λ _i (i=2, 3, 5, 16) is the distribution of edges associated with variables with degree i, ρ _i (i=2, 3, 5, 16) is the distribution of edges associated with Check the distribution of edges associated with a node.

That is, to support variable coding rates, block LDPC codes with low coding rates and block LDPC codes with high coding rates must be designed in such a way that they all should have good noise thresholds: will first have low coding rates The result obtained by performing the optimization of the block LDPC code of is set as a constraint, and then the optimization is performed sequentially for the block LDPC code with the next high coding rate. Although the degrees of variable nodes are limited to the 4 types shown in Fig. 16 for convenience, it is possible to obtain a noise threshold with better performance if the number of allowed variable node degrees is increased.

Now explain when the number of check nodes is limited to M and the maximum degree of variable nodes is limited to _dv,max under the assumption that the coding rate is R ₁ <R ₂ <...<R _m and each parity check matrix The process of designing a variable coding rate block LDPC code when the size is M×N _i .

step 1

First, for the coding rate R ₁ , a density evolution scheme is used to perform degree distribution optimization. It will be assumed that among the distribution degrees obtained by performing the length distribution optimization, the ratio of variable nodes having a degree j (1≤j≤d _v,max ) to all variable nodes is f _1,j . The relation using Equation (11) exchanges the ratio of f _1,j and the distribution degree λ _1,j of an edge, and λ _1,j represents the ratio of the energy connected to a variable node with degree j to the total energy.

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="f"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">f</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; j</span>}}{\underset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&DoubleLeftRightArrow;</span>{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="f"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">f</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}}}{\underset{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="f"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">f</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; k</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

In Equation (11), 'k' has the same value as that of degree 'j', and check nodes are also considered in the same manner as variable nodes.

step 2

The degree distribution optimization is performed by setting the following additional constraints: _for l(2≤l≤m), f _{l−1, j} ×N _l−1 variable nodes have codeword length of R _i ) degree j in variable nodes. Check mode is also performed in the same manner as variable nodes.

By performing degree distribution optimization in the manner of steps 1 and 2, it is possible to design parity check matrices of block LDPC codes with various coding rates. It can be noted that, according to the required coding rate R _i , using the shortening scheme, the designed parity check matrix is the parity check matrix corresponding to the block LDPC code whose parity length is kept at M and the block length is changed to N _i . In addition, if the puncturing scheme is used together with the shortening scheme, it is possible to generate block LDPC codes with more various coding rates and block (codeword) lengths.

Assuming that for a coding rate R _i , the number of punctured parity bits is expressed as P _i (M), and the block length and coding rate of the generated block LDPC code are expressed as shown in Equation (12).

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="N\; i"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">N</figure-callout></span><figure-callout\; id="1"\; label="N\; i"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">i</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; I</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R\; i"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">R</figure-callout></span><figure-callout\; id="1"\; label="R\; i"\; filenames="A20058001536800601.png,A20058001536800631.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">i</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; ></span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

In order to generate a block LDPC code with a fixed block length, the number P _i of punctured parity bits is appropriately determined so as to hold N _i −P _i =N _l . In this case, the encoding rate can be expressed as shown in Equation (13).

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}^{<span\; class="notranslate">\; \text{'}</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

As mentioned above, the most important factor that should be considered in designing a parity check matrix of a variable coding rate block LDPC code is degree distribution optimization. If too many coding rates support variable coding rates, the check node degree increases, making the cycle characteristics worse. Therefore, the parity check matrix should be designed in consideration of all factors of the number of supportable coding rates, noise threshold to be obtained, and cycle characteristics.

FIG. 17 is a flowchart illustrating a process of encoding a variable coding rate block LDPC code according to one embodiment of the present invention. Before describing FIG. 17 , it should be assumed that a parity check matrix for a variable coding rate block LDPC code includes 6 partial matrices, as described with reference to FIG. 8 .

Referring to FIG. 17, in step 1710, the controller determines a coding rate change scheme to be applied to the parent parity check matrix according to a predetermined coding rate so as to generate a variable coding rate block LDPC code. Here, the "coding rate changing scheme" includes a shortening scheme and a puncturing scheme, and when the parent parity check matrix is used as it is, the coding rate changing scheme is not used. One or both of the shortening scheme and the puncturing scheme can be used to change the coding rate. Here, it is assumed that the encoding rate is changed using a shortening scheme or a puncturing scheme.

In step 1711, the controller receives the information word vector ' s ' to be encoded into the variable coding rate block LDPC code. Change the length of the message word variable ' s ' only when using the shortening scheme. It is assumed here that the length of the received information word variable ' s ' encoded into the variable coding rate block LDPC code is 'k'. In step 1713, the controller performs matrix multiplication (A s ) on the received information word variable ' s ' with the partial matrix A of the parity check matrix. Here, since the number of elements with the value 1 located in the partial matrix A is much smaller than the number of elements with the value 0, the information word vector s and the parity check can be realized with a smaller number of sum-product operations The matrix multiplication of the sub-matrix A of the test matrix (A s ).

In addition, in the partial matrix A, since the position of an element with a value of 1 can be expressed as the multiplication of the position of a non-zero block and the exponent of the truncation matrix of the block, compared with the random parity check matrix , the matrix multiplication can be performed in a very simple operation.

In step 1715, the controller performs a matrix multiplication (C s ) on the partial matrix C of the parity check matrix and the information word vector ' s '. For the partial matrices A and C used in steps 1713 and 1715, when the shortening scheme is applied to the parent parity check matrix, the same number of columns of the parent parity check matrix as the shortened part are not used. Therefore, the columns corresponding to the shortened parts are removed from the partial matrices A and C of the parent parity check matrix.

In step 1717, the controller performs matrix multiplication (ET ^-1 A s ) on the matrix ET ^-1 of the matrix multiplication result (A s ) of the information word vector ' s ' and the partial matrix A of the parity check matrix. Since the number of elements with the value 1 in the matrix ET ⁻¹ is small as described above, the matrix multiplication can be easily performed if the index of the puncturing matrix of the block is given.

In step 1719, the controller calculates the first parity vector p ₁ ( p ₁ =ET ⁻¹ A s +C) by adding ET ⁻¹ A and C s . Here, the addition operation is an exclusive OR (XOR) operation, and its result becomes 0 for an operation between bits having the same value and 1 for an operation between bits having different values. That is, the processing up to step 1719 is processing for calculating _the first parity vector P1 .

In step 1721, the controller multiplies the partial matrix B of the parity check matrix with the first parity vector P ₁ (B P ₁ ), and adds the multiplication result (B P ₁ ) to A s (A s +B P ₁ ). If the information word vector ' s ' and _the first parity vector P1 are given, they should be multiplied by the inverse matrix T ^-1 of the partial matrix T of _the parity check matrix to calculate the second parity vector P2 . Therefore, in step 1723, the controller multiplies the calculation result (A s +B P ₁ ) of step 1721 by the inverse matrix T ^-1 of the partial matrix T to calculate the second parity vector P ₂ ( P ₂ =T ^-1 ( A s +B P ₁ )).

As mentioned above, if the information word vector ' s ' of the variable coding rate block LDPC _code to be encoded is given, the first parity variable P1 and the second parity variable P2 can be calculated, and as a result, all _the codes can be obtained word vector. In step 1725, the controller uses _the information _word vector ' s ', the first parity variable P1 and the second parity variable P2 to generate a codeword vector ' c '.

In step 1727, the controller generates a block LDPC code corresponding to the coding rate by puncturing the parity of the codeword vector ' c ' according to a predetermined puncturing pattern, and then ends the procedure.

FIG. 18 is a block diagram illustrating an internal structure of an apparatus for encoding a variable coding rate block LDPC code according to an embodiment of the present invention. Referring to Fig. 18, the described device for encoding variable encoding rate block LDPC code comprises controller 1810, matrix A multiplier 1811, matrix C multiplier 1813, matrix ET ^-1 multiplier 1815, adder 1817, matrix B multiplier 1819, adder 1821, matrix T ^-1 multiplier 1823 and switches 1825, 1827 and 1829.

An input signal, ie, an information word vector ' s ' of length k to be encoded into a variable coding rate block LDPC code, is input to a switch 1825 , a matrix A multiplier 1811 , and a matrix C multiplier 1813 . When the variable encoding rate block LDPC code encoding device uses a shortening scheme, the controller 1810 changes the length 'k' of the information word vector ' s ' according to the corresponding encoding rate, and determines the variable encoding according to the corresponding encoding rate Codeword length and puncturing pattern of rate block LDPC codes.

The matrix A multiplier 1811 multiplies the information word vector ' s ' by the partial matrix A of the parent parity check matrix, and outputs the multiplication result to the matrix ET ⁻¹ multiplier 1815 and the adder 1821 . When the shortening scheme is applied to the parent parity check matrix as described with reference to FIG. 17 , matrix A and matrix C have a format in which columns corresponding to shortened parts are removed from matrix A and matrix C of the parent parity check matrix. The matrix ET ⁻¹ multiplier 1815 multiplies the signal output from the matrix A multiplier 1811 by the partial matrix ET ⁻¹ of the parent parity check matrix, and outputs the multiplication result to the adder 1817 .

The adder 1817 adds the signal output from the matrix ET ⁻¹ multiplier 1815 and the signal output from the matrix C multiplier 1813 , and outputs the addition result to the matrix B multiplier 1819 and the switch 1827 . Here, the adder 1817 performs an exclusive OR operation on a bit-by-bit basis. For example, if a vector x=(x ₁ , x ₂ , x ₃ ) of length 3 and a vector y=(y ₁ , y ₂ , y ₃ ) of length 3 are input to the adder 1817, then the adder 1817 XORs the length 3 vector x = (x ₁ , x ₂ , x ₃ ) and length 3 vector y = (y ₁ , y ₂ , y ₃ ) and the output length 3 vector z = (x ₁ _y ₁ , x ₂ _y ₂ , x ₃ _y ₃ ). Here, _ operation represents an exclusive OR operation, the result of which becomes 0 for an operation between bits having the same value, and becomes 1 for an operation between bits having different values. The signal output from the adder 1817 becomes the first parity vector P ₁ .

The matrix B multiplier 1819 multiplies the signal output from the adder 1817 , that is, the first parity vector P ₁ by the partial matrix B of the parent parity check matrix, and outputs the multiplication result to the adder 1821 . The adder 1821 adds the signal output from the matrix B multiplier 1819 and the signal output from the matrix A multiplier 1811 , and outputs the addition result to the matrix T−1 multiplier 1823 . The adder 1821 performs an exclusive OR operation on the signal output from the matrix B multiplier 1819 and the signal output from the matrix A multiplier 1811 like the adder 1817 , and outputs the exclusive OR operation result to the matrix T ⁻¹ multiplier 1823 .

The matrix T ⁻¹ multiplier 1823 multiplies the signal output from the adder 1821 by the inverse matrix T ⁻¹ of the partial matrix T of the parent parity check matrix, and outputs the multiplication result to the switch 1829 . The output of the matrix T ^-1 multiplier 1823 becomes the second parity vector P ₂ . Each on-off switch 1825, 1827, and 1829 is only turned on during its transmission time when its associated signal is transmitted. The switch 1825 is turned on at the transmission time _{of the} information word vector ' s ', the switch 1827 is turned on at the transmission time of the first parity vector P1 , and the switch 1829 is turned on at the transmission time of the second parity vector P2 Pass. When applying the puncturing scheme to the parent parity check matrix, the controller 1810 controls the switch 1627 and the switch 1629 to puncture the parity according to the corresponding encoding rate.

Although it will be described in detail below, because the embodiments of the present invention should be able to produce variable coding rate block LDPC codes, each matrix used in the variable coding rate block LDPC code coding device in Fig. 18 can be changed every time. The parity check matrix of the variable coding rate block LDPC code is changed. Therefore, although not independently shown in FIG. 18, when the parity check matrix of the variable coding rate block LDPC code is changed, the controller 1810 modifies the matrix.

All LDPC family codes can be decoded in a factor graph using the subproduct algorithm. The decoding scheme of the LDPC code can be roughly divided into a bidirectional transfer scheme and a flow transfer scheme. When performing a decoding operation using a bidirectional transfer scheme, each check node has a node processor, increasing decoding complexity in proportion to the number of check nodes. However, since all check nodes are updated at the same time, the decoding speed is significantly improved. In contrast, the streaming scheme has a single node processor, and the node processor updates information across all nodes in the factor graph. Therefore, the streaming scheme is low in decoding complexity, but the increase in the size of the parity check matrix, ie, the increase in the number of nodes, reduces the decoding speed.

However, if a parity check matrix is generated for each block like the variable coding rate block LDPC code with various coding rates proposed in the present invention, the same number of nodes as the number of blocks constituting the parity check matrix are used to process device. In this case, it is possible to realize a decoder which is lower in decoding complexity than the bidirectional transfer scheme and higher in decoding speed than the streaming transfer scheme.

FIG. 19 is a block diagram illustrating an internal structure of an apparatus for decoding a variable coding rate block LDPC code according to an embodiment of the present invention. Referring to Fig. 19, the decoding device for decoding variable coding rate block LDPC codes includes block controller 1910, variable node part 1900, adder 1915, deinterleaver 1917, interleaver 1919, controller 1921, memory 1923, adder 1925, check node section 1950 and hard decoder 1929. The variable node section 1900 includes a variable node decoder 1911 and switches 1913 and 1914 , and the check node section 1950 includes a check node decoder 1927 .

A signal received through a radio channel is input to the block controller 1910 . The controller 1910 determines the block size of the received signal, and if there is an information word part punctured in the encoding device corresponding to the decoding device, the block controller 1910 inserts '0' into the punctured information word part to The overall block size is adjusted and the resulting signal is output to the variable node decoder 1911. The block controller 1910 has pre-stored information of a method of applying a shortening scheme and a puncturing scheme to a parent parity check matrix at a predetermined corresponding encoding rate between a decoding device and its associated encoding device. Here, the information on the method of applying the shortening scheme and the puncturing scheme to the parent parity check matrix according to the corresponding encoding rate includes information on the number of shortened or punctured partial blocks and information on the number of shortened or punctured partial blocks location information. Therefore, the block controller 1910 removes from the received signal the part shortened according to the coding rate applied in the encoding means, inserts the LLR value '0' into the punctured part, and outputs to the variable node decoder 1911 resulting signal.

The variable node decoder 1911 calculates the probability value of the signal output from the controller 1910 , updates the calculated probability value, and outputs the updated probability value to the switches 1913 and 1914 . The variable node decoder 1911 connects the variable nodes according to the parity check matrix preset in the decoding device for the variable coding rate block LDPC code, and for as many as the number of 1s connected to the variable nodes Input values and output values perform update operations. The number of 1s connected to the variable nodes is equal to the weight of each of the columns included in the parity check matrix. The internal operation of the variable node decoder 1911 differs according to the weight of each of the columns included in the parity check matrix. However, when the switch 1913 is turned on, the switch 1914 is turned on to output the output signal of the variable node decoder 1911 to the adder 1915 .

The adder 1915 receives the signal output from the variable node decoder 1911 and the output signal of the interleaver 1919 in the previous iterative decoding process, and subtracts the output signal in the previous iterative decoding process from the output signal of the variable node decoder 1911 The output signal of the interleaver 1919, and the subtraction result is output to the deinterleaver 1917. If the decoding process is an initial decoding process, the output signal of the interleaver 1919 should be considered to be 0.

The deinterleaver 1917 deinterleaves the signal output from the adder 1915 according to a predetermined interleaving scheme, and outputs the deinterleaved signal to the adder 1925 and the check node decoder 1927 . The deinterleaver 1917 has an internal structure corresponding to the parity check matrix because the output value corresponding to the deinterleaver 1917 for the input value of the interleaver 1919 differs according to the position of an element having a value of 1 in the parity check matrix .

The adder 1925 receives the output signal of the check node decoder 1927 in the previous iterative decoding process and the output signal of the deinterleaver 1917, and subtracts from the output signal of the check node decoder 1927 in the previous iterative decoding process The output signal of the deinterleaver 1917, and the subtraction result is output to the interleaver 1919. The check node decoder 1927 connects the check nodes according to the parity check matrix set in advance in the decoding apparatus for block LDPC codes, and performs update operation. The number of 1s connected to a check node is equal to the weight of each row making up the parity check matrix. Therefore, the internal operation of the check node decoder 1927 differs according to the weight of each row constituting the parity check matrix.

The interleaver 1919 interleaves the signal output from the adder 1925 according to a predetermined interleaving scheme under the control of the controller 1921 , and outputs the interleaved signal to the adder 1915 and the variable node decoder 1911 . The controller 1921 reads information associated with the interleaving scheme stored in the memory 1923 in advance, and controls the interleaving scheme of the interleaver 1919 and the deinterleaving scheme of the deinterleaver 1917 according to the read interleaving scheme information. Similarly, if the decoding process is an initial decoding process, the output signal of the deinterleaver 1917 should be considered to be 0.

By iteratively performing the above-described processing, the decoding device performs error-free reliable decoding. After performing iterative decoding a predetermined number of times, the switch 1914 turns off the connection between the variable node decoder 1911 and the adder 1915, and the switch 1913 turns on the connection between the variable node decoder 1911 and the hard decoder 1929. connected to provide the hard decoder 1929 with the signal output from the variable node decoder 1911, the hard decoder 1929 performs hard determination on the signal output from the variable node decoder 1911, and outputs the hard determination result, and the hard decoder 1929 The output value of becomes the final decoded value.

FIG. 20 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention. Specifically, FIG. 20 illustrates a parity check matrix of a block LDPC code having a codeword length of 2000 and a coding rate of 4/5. Here, the size of each block in the parity check matrix is 40×40, and the value written in each of the blocks illustrated in FIG. 20 , ie, partial blocks, represents a variable coding rate block The exponent of the LDPC code.

As shown in FIG. 20, the information part of the information word mapped to the parity-check matrix is divided into 4 sub-parts, and only the code word mapped to the part corresponding to the part indicated by the arrow according to the corresponding coding rate is transmitted , thereby making it possible to support code rates 1/3, 1/2, 2/3, 3/4 and 4/5. Codewords (N, K) of each of coding rates 1/3, 1/2, 2/3, 3/4, and 4/5 are expressed as follows:

(N, K) = (600, 200), (800, 400), (1200, 800), (1600, 1200), (2000, 1600)

FIG. 21 is a diagram illustrating an internal structure of an encoding apparatus for a variable encoding rate block LDPC code according to another embodiment of the present invention. Referring to FIG. 21 , an encoding device for a variable encoding rate block LDPC code includes a 0 inserter 2100 , a block LDPC encoder 2110 , a puncturer 2120 and a controller 2130 . The encoding apparatus for variable encoding rate block LDPC code illustrated in FIG. 21 has a structure capable of using a conventional variable encoding rate block LDPC encoding apparatus without any modification in such a manner that only 0 The interpolator 2100 is added to the variable coding rate block LDPC coding apparatus using the parent parity check matrix as it is. Therefore, the encoding device of the variable encoding rate block LDPC code in FIG. 21 can reduce its hardware complexity by only including the 0 inserter 2100.

Before inputting an input information bitstream into an encoding device for a variable encoding rate block LDPC code, information on a corresponding encoding rate and a size of the input information bitstream is provided to the controller 2130 . Then, the controller 2130 outputs the information on the coding rate to the 0 inserter 2100 and the puncturer 2120 , and outputs the codeword length information based on the size information of the input information bitstream to the block LDPC encoder 2110 . Thereafter, the input information bit stream is input to the 0 inserter 2100 .

The 0 inserter 2100 inserts '0' into the input information bitstream according to encoding rate information output from the controller 2130, and outputs the 0-inserted input information bitstream to the block LDPC encoder 2110. The size of the information word output from the 0 inserter 2100 is equal to the size of the information word (1600 bits) in the parity check matrix illustrated in FIG. 20 .

It is assumed here that the block LDPC encoder 2110 receives a (2000, 1600) code, ie, a 1600-bit input information bit stream, and outputs 2000 coded symbols. If the block LDPC encoder 2110 is used as a (1600, 1200) block LDPC encoder with a coding rate of 3/4, then the 0 inserter 2100 receives a 1200-bit input information bit stream, and inserts into the 1200-bit input information bit stream 400 '0' bits, and output a total of 1600 bits. If the block LDPC encoder 2110 is used as a (1200, 800) block LDPC encoder with a coding rate of 2/3, then the 0 inserter 2100 receives an 800-bit input information bit stream, and inserts into the 800-bit input information bit stream 800 '0' bits, and output a total of 1600 bits. If the block LDPC encoder 2110 is used as a (800, 400) block LDPC encoder with a coding rate of 1/2, then the 0 inserter 2100 receives a 400-bit input information bit stream, and inserts into the 400-bit input information bit stream 1200 '0' bits, and output a total of 1600 bits. If the block LDPC encoder 2110 is used as a (600, 200) block LDPC encoder with a coding rate of 3/4, then the 0 inserter 2100 receives a 200-bit input information bit stream, and inserts into the 200-bit input information bit stream 1400 '0' bits, and a total of 1600 bits are output.

The 1600 bit stream output from the 0 inserter 2100 is input to the block LDPC encoder 2110, and the block LDPC encoder 2110 performs (2000, 1600) block LDPC encoding on the 1600 bit stream. The block LDPC encoder 2110 encodes the 1600 bit stream output from the 0 inserter 2100 according to the parity check matrix described with reference to FIG. 20 , and outputs 2000 encoded symbols. The 2000 coded symbols output from the block LDPC encoder 2110 are input to the truncation unit 2120, and the truncation unit 2120 punctures the 2000 symbols corresponding to the coding rate provided from the controller 2130 The information corresponds to the same number of encoding symbols.

For example, if the encoding device acts as a (1600, 1200) encoding device having a coding rate of 3/4, the puncturer 2120 receives 2000 encoding symbols, punctures 400 encoding symbols therefrom, and outputs a total of 1600 encoding symbols Yuan. If the encoding device acts as a (1200, 800) encoding device having a coding rate of 2/3, the puncturer 2120 receives 2000 encoded symbols, punctures 800 encoded symbols therefrom, and outputs a total of 1200 encoded symbols. If the encoding device acts as a (800, 400) encoding device having a coding rate 1/2, the puncturer 2120 receives 2000 encoded symbols, punctures 1200 encoded symbols therefrom, and outputs a total of 800 encoded symbols. If the encoding device acts as a (600, 200) encoding device having a coding rate 1/3, the puncturer 2120 receives 2000 encoded symbols, punctures 1400 encoded symbols therefrom, and outputs a total of 600 encoded symbols.

FIG. 22 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention. Specifically, FIG. 22 illustrates a parity check matrix of a block LDPC code having a codeword length of 2000 and a coding rate of 4/5. Here, the size of each block in the parity check matrix is 40×40, and the value written in the block illustrated in FIG. 22 , that is, each of the partial blocks represents the index of the permutation matrix.

Referring to Fig. 22, the information part that is mapped to the information word of the parity check matrix is divided into 4 sub-parts, and only transmits the code word that is mapped to the part corresponding to the part indicated by the arrow according to the corresponding coding rate, whereby Makes it possible to support code rates 1/3, 1/2, 2/3, 3/4 and 4/5. The difference between the parity check matrix illustrated in FIG. 22 and the parity check matrix illustrated in FIG. 20 is that they have different matrix distributions. Specifically, the parity check matrix illustrated in FIG. 22 has a structure in which the average row weight is 19.7, and the girth of the minimum number of cycles is 6. Codewords (N, K) of each of coding rates 1/3, 1/2, 2/3, 3/4, and 4/5 are expressed as follows:

(N, K) = (600, 200), (800, 400), (1200, 800), (1600, 1200), (2000, 1600)

FIG. 23 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention. Specifically, FIG. 23 illustrates a parity check matrix supporting a coding rate of 2/3. A block LDPC code having an encoding rate of 1/2 can be generated by shortening a portion divided by a first row in a parity check matrix using a shortening scheme.

FIG. 24 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention. Specifically, FIG. 24 illustrates a parity check matrix supporting a coding rate of 3/4. A block LDPC code having a coding rate of 2/3 can be generated by shortening the part divided by the first row in the parity check matrix by using a shortening scheme, and can be shortened by using the shortening scheme by the first row in the parity check matrix The second row is divided to generate a block LDPC code with a coding rate of 1/2.

FIG. 25 is a diagram illustrating a parity check matrix for a variable coding rate block LDPC code according to one embodiment of the present invention. Specifically, FIG. 25 illustrates a parity check matrix supporting a coding rate of 3/4. A block LDPC code having a coding rate of 2/3 can be generated by shortening the part divided by the first row in the parity check matrix by using a shortening scheme, and can be shortened by using the shortening scheme by the first row in the parity check matrix The second row is divided to generate a block LDPC code with a coding rate of 1/2.

As described above, the present invention proposes a variable coding rate block LDPC code in a mobile communication system, thereby improving the flexibility of the block LDPC code. In addition, the present invention produces an efficient parity check matrix, thereby minimizing the coding complexity of variable coding rate block LDPC codes. In particular, the present invention enables generation of block LDPC codes capable of supporting various encoding rates, thereby minimizing hardware complexity.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that forms may be made without departing from the spirit and scope of the invention as defined in the appended claims. and various changes in details.

Claims (107)

1. the method for block low density parity check (LDPC) code of being used to encode with variable coding rate, described method comprises step:

Receive information word; And

Based on one of first parity matrix and second parity matrix described information word is encoded to described LDPC sign indicating number according to when producing described information word, being applied to described encoding rate in the LDPC sign indicating number.

2. according to the method for claim 1, also comprise step:

Use modulation scheme that described LDPC sign indicating number is modulated to modulated symbol; And

Send modulated code element.

3. according to the method for claim 2, wherein, first parity matrix is produced makes described LDPC sign indicating number have the parity matrix of predictive encoding rate.

4. according to the method for claim 3, wherein, described first parity matrix comprises the message part that is mapped to information word and is mapped to the odd even part of parity word.

5. according to the method for claim 4, wherein, described first parity matrix comprises a plurality of part pieces, the part piece of first quantity in described a plurality of part pieces is mapped to message part, and the part piece of second quantity in described a plurality of part pieces, except the part piece of described first quantity is mapped to the odd even part.

6. according to the method for claim 5, wherein, on the man-to-man basis predetermined permutation matrix is being mapped to each of reservations piecemeal in described part piece.

7. according to the method for claim 6, wherein, the described step that information word is encoded to piece LDPC sign indicating number comprises step:

Determine one of first parity matrix and second parity matrix according to encoding rate;

Produce first signal by first's matrix multiple with described information word and determined parity matrix;

Produce secondary signal by second portion matrix multiple with described information word and determined parity matrix;

Multiply each other by matrix product and to produce the 3rd signal the inverse matrix of the third part matrix of first signal and determined parity matrix and the 4th part matrix;

Produce the 4th signal by secondary signal being added to described the 3rd signal;

By described the 4th signal times is produced the 5th signal with the 5th part matrix of determined parity matrix;

By secondary signal and the 5th signal plus are produced the 6th signal;

Produce the 7th signal by the 4th inverse of a matrix matrix multiple with the 6th signal and determined parity matrix; And

Multiplexing described information word, be defined as the 4th signal of first parity word and be defined as the 7th signal of second parity word, so that described information word, first parity word and second parity word are mapped to piece LDPC sign indicating number.

8. according to the method for claim 7, wherein, described first matrix and described second portion matrix are to be mapped to the message part that is associated with information word in determined parity matrix.

9. according to the method for claim 8, wherein, described third part matrix and described the 4th part matrix are the part matrixs that is mapped to first odd even part that is associated with parity word, and described the 5th part matrix and the 6th part matrix are the part matrixs that is mapped to second odd even part that is associated with described parity word.

10. according to the process of claim 1 wherein, determine that according to encoding rate the step of one of first parity matrix and second parity matrix comprises step:

If determine to use second parity matrix according to encoding rate, then cut one of scheme and be applied to first parity matrix and produce second parity matrix by shortening scheme and grid.

11., wherein, obtain second parity matrix by the part piece that uses the shortening scheme to shorten the predetermined quantity in the part piece of first quantity in first parity matrix according to the method for claim 10.

12. according to the method for claim 11, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

13. according to the method for claim 12, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be listed as the 7th part piece row by the first's piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 8th part piece is listed as the 21st part piece row, and will be mapped to odd even corresponding to the part matrix that the 22nd part piece is listed as the 49th part piece row.

14. according to the method for claim 13, wherein, first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

15. according to the method for claim 10, wherein, second parity matrix is the parity matrix that obtains by the part piece that uses grid to cut the predetermined quantity in the part piece that the scheme grid cut second quantity in first parity matrix.

16. according to the method for claim 15, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

17. according to the method for claim 16, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be mapped to information word by the part matrix that will be listed as the 21st part piece row, and use the grid scheme of cutting to come grid to cut to be listed as 7 predetermined part pieces row in the 49th part piece row at the 22nd part piece corresponding to first's piece of first parity matrix.

18. according to the method for claim 17, wherein, described first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

19. method according to claim 18, wherein, the part piece row that cut by grid are included in the 23rd part piece row in first parity matrix, the 27th part piece row, the 31st part piece row, the 35th part piece row, the 39th part piece row, the 43rd part piece row and the 47th part piece row.

20. according to the method for claim 11, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

21. according to the method for claim 20, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sProduce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

22. according to the method for claim 11, wherein, when encoding rate is 4/5, and the codeword length of piece LDPC sign indicating number is 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

23. according to the method for claim 22, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sThe time, produce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row; And

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

24. according to the method for claim 11, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

25. according to the method for claim 24, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 32N _sThe time, produce second parity matrix by following manner: be listed as the 15th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 16th part piece is listed as the 31st part piece row, and will be mapped to odd even corresponding to the part matrix that the 32nd part piece is listed as the 47th part piece row.

26. according to the method for claim 11, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

27. according to the method for claim 26, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to odd even corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to odd even corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

28. according to the method for claim 11, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

29. according to the method for claim 28, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to odd even corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to odd even corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

30. the device of block low density parity check (LDPC) code with variable coding rate of being used to encode, described device comprises:

Encoder is used for based on one of first parity matrix and second parity matrix described information word being encoded to described LDPC sign indicating number according to the encoding rate that will be applied to described LDPC sign indicating number when producing described information word;

Modulator is used to use modulation scheme that described LDPC sign indicating number is modulated to modulated symbol; And

Transmitter is used to send modulated code element.

31. according to the device of claim 30, wherein, first parity matrix is produced makes described LDPC sign indicating number have the parity matrix of predictive encoding rate.

32. according to the device of claim 31, wherein, described first parity matrix comprises the message part that is mapped to information word and is mapped to the odd even part of parity word.

33. device according to claim 32, wherein, described first parity matrix comprises a plurality of part pieces, the part piece of first quantity in described a plurality of part pieces is mapped to message part, and the part piece of second quantity in described a plurality of part pieces, except the part piece of described first quantity is mapped to the odd even part.

34., wherein, on the man-to-man basis predetermined permutation matrix is being mapped to each of reservations piecemeal in described part piece according to the device of claim 33.

35. according to the device of claim 34, wherein, described encoder comprises:

Controller is used for determining one of first parity matrix and second parity matrix according to encoding rate;

First matrix multiplier is used for the first's matrix multiple with described information word and determined parity matrix;

Second matrix multiplier is used for the second portion matrix multiple with described information word and determined parity matrix;

The 3rd matrix multiplier is used for and will multiplies each other from the matrix product of the inverse matrix of the third part matrix of the signal of first matrix multiplier output and determined parity matrix and the 4th part matrix;

First adder is used for the signal from the output of second matrix multiplier is added to from the signal of the 3rd matrix multiplier output;

The 4th matrix multiplier is used for and will multiplies each other from the signal of first adder output and the 5th part matrix of determined parity matrix;

Second adder is used for signal and the signal plus of exporting from the 4th matrix multiplier from the output of second matrix multiplier;

The 5th matrix multiplier, being used for will be from the signal of second adder output and the 4th inverse of a matrix matrix multiple of determined parity matrix;

A plurality of switches, be used for multiplexing described information word, be defined as first parity word first adder output signal and be defined as the output signal of the 5th matrix multiplier of second parity word so that described information word, first parity word and second parity word are mapped to piece LDPC sign indicating number.

36. according to the device of claim 30, wherein, described first matrix and described second portion matrix are the part matrixs that is mapped to the message part that is associated with information word in determined parity matrix.

37. device according to claim 36, wherein, described third part matrix and described the 4th part matrix are the part matrixs that is mapped to first odd even part that is associated with parity word, and described the 5th part matrix and the 6th part matrix are the part matrixs that is mapped to second odd even part that is associated with described parity word.

38. according to the device of claim 37, wherein, if determine to use second parity matrix according to encoding rate, then controller cuts one of scheme and is applied to first parity matrix and produces second parity matrix by shortening scheme and grid.

39., wherein, obtain second parity matrix by the several portions piece that uses the shortening scheme to shorten in the part piece of first quantity in first parity matrix according to the device of claim 38.

40. according to the device of claim 39, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

41. according to the device of claim 40, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be listed as the 7th part piece row by the first's piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 8th part piece is listed as the 21st part piece row, and will be mapped to odd even corresponding to the part matrix that the 22nd part piece is listed as the 49th part piece row.

42. according to the device of claim 41, wherein, first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

43. according to the device of claim 39, wherein, second parity matrix is by using grid to cut the parity matrix that the several portions piece in the part piece that the scheme grid cut second quantity in first parity matrix obtains.

44. according to the device of claim 43, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

45. according to the device of claim 44, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be mapped to information word by the part matrix that will be listed as the 21st part piece row, and use the grid scheme of cutting to come grid to cut to be listed as 7 predetermined part pieces row in the 49th part piece row at the 22nd part piece corresponding to first's piece of first parity matrix.

46. according to the device of claim 45, wherein, described first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

47. device according to claim 46, wherein, the part piece row that cut by grid are included in the 23rd part piece row in first parity matrix, the 27th part piece row, the 31st part piece row, the 35th part piece row, the 39th part piece row, the 43rd part piece row and the 47th part piece row.

48. according to the device of claim 39, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

49. according to the device of claim 48, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to odd even corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sProduce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

50. according to the device of claim 39, wherein, when encoding rate is 4/5, and the codeword length of piece LDPC sign indicating number is 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

51. according to the device of claim 50, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sThe time, produce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row; Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

52. according to the device of claim 39, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

53. according to the device of claim 52, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 32N _sThe time, produce second parity matrix by following manner: be listed as the 15th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 16th part piece is listed as the 31st part piece row, and will be mapped to parity word corresponding to the part matrix that the 32nd part piece is listed as the 47th part piece row.

54. according to the device of claim 39, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

55. according to the device of claim 54, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

56. according to the device of claim 39, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

57. according to the device of claim 56, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

58. the method for block low density parity check (LDPC) code with variable coding rate of being used to decode, described method comprises step:

Received signal;

Encoding rate according to the piece LDPC sign indicating number that will decode is determined one of first parity matrix and second parity matrix; And

The signal of decoding and being received according to determined parity matrix is so that detect described LDPC sign indicating number.

59. according to the method for claim 58, wherein, first parity matrix is produced makes described LDPC sign indicating number have the parity matrix of predictive encoding rate.

60. according to the method for claim 59, wherein, described first parity matrix comprises the message part that is mapped to information word and is mapped to the odd even part of parity word.

61. method according to claim 60, wherein, described first parity matrix comprises a plurality of part pieces, the part piece of first quantity in described a plurality of part pieces is mapped to message part, and the part piece of second quantity in described a plurality of part pieces, except the part piece of described first quantity is mapped to the odd even part.

62., wherein, on the man-to-man basis predetermined permutation matrix is being mapped to each of reservations piecemeal in described part piece according to the method for claim 61.

63., wherein, thereby comprise step according to the determined parity matrix step that the signal that received detects piece LDPC sign indicating number of decoding according to the method for claim 62:

Determine scheme of deinterleaving and interleaving scheme according to determined parity matrix;

Detect the probable value of the signal that is received;

Deduct the signal that produces formerly the decoding processing by probable value and produce first signal from the signal that received;

The use scheme of deinterleaving first signal that deinterleaves;

The probable value of the signal that detection is deinterleaved;

Deduct the signal that deinterleaves by probable value and produce secondary signal from the signal that deinterleaves; And

Use the interleaving scheme secondary signal that interweaves, thereby and the signal that is interleaved of iterative decoding detect piece LDPC sign indicating number.

64., wherein, obtain second parity matrix by the part piece that uses the shortening scheme to shorten the predetermined quantity in the part piece of first quantity in first parity matrix according to the method for claim 63.

65. according to the method for claim 64, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

66. according to the method for claim 65, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be listed as the 7th part piece row by the part 1 piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 8th part piece is listed as the 21st part piece row, and will be mapped to odd even corresponding to the part matrix that the 22nd part piece is listed as the 49th part piece row.

67. according to the method for claim 66, wherein, first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

68. according to the method for claim 63, wherein, second parity matrix is the parity matrix that obtains by the part piece that uses grid to cut the predetermined quantity in the part piece that the scheme grid cut second quantity in first parity matrix.

69. according to the method for claim 68, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

70. according to the method for claim 69, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be mapped to information word by the part matrix that will be listed as the 21st part piece row, and use the grid scheme of cutting to come grid to cut to be listed as 7 predetermined part pieces row in the 49th part piece row at the 22nd part piece corresponding to the part 1 piece of first parity matrix.

71. according to the method for claim 70, wherein, described first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

72. method according to claim 71, wherein, the part piece row that cut by grid are included in the 23rd part piece row in first parity matrix, the 27th part piece row, the 31st part piece row, the 35th part piece row, the 39th part piece row, the 43rd part piece row and the 47th part piece row.

73. according to the method for claim 64, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

74. method according to claim 73, wherein, when encoding rate is 1/3 and the codeword length of piece LDPC sign indicating number when being 15Ns, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sProduce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

75. according to the method for claim 64, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

76. according to the method for claim 75, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sThe time, produce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

77. according to the method for claim 64, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

78. according to the method for claim 77, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 32N _sThe time, produce second parity matrix by following manner: be listed as the 15th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 16th part piece is listed as the 31st part piece row, and will be mapped to parity word corresponding to the part matrix that the 32nd part piece is listed as the 47th part piece row.

79. according to the method for claim 64, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

80. according to the method for claim 79, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

81. according to the method for claim 64, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

82. according to the method for claim 81, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

83. the device of block low density parity check (LDPC) sign indicating number with variable coding rate of being used to decode, described device comprises:

Receiver is used for received signal; And,

Decoder is used for determining one of first parity matrix and second parity matrix according to the encoding rate of the piece LDPC sign indicating number that will decode, and the signal of decoding and being received according to determined parity matrix, so that detect described LDPC sign indicating number.

84. according to the device of claim 83, wherein, first parity matrix is produced makes described LDPC sign indicating number have the parity matrix of predictive encoding rate.

85. according to the device of claim 84, wherein, described first parity matrix comprises the message part that is mapped to information word and is mapped to the odd even part of parity word.

86. device according to claim 85, wherein, described first parity matrix comprises a plurality of part pieces, the part piece of first quantity in described a plurality of part pieces is mapped to message part, and the part piece of second quantity in described a plurality of part pieces, except the part piece of described first quantity is mapped to the odd even part.

87., wherein, on the man-to-man basis predetermined permutation matrix is being mapped to each of reservations piecemeal in described part piece according to the device of claim 86.

88. according to the device of claim 87, wherein, described decoder comprises:

First controller is used for determining one of first parity matrix and second parity matrix according to the encoding rate of the piece LDPC sign indicating number that will decode;

The variable node decoder device is used for connecting the probable value that variable node detects the signal that is received by the weighting according to the every row that comprise at determined parity matrix;

First adder is used for the signal that produces from the signal from variable node decoder device output deducts formerly decoding processing;

Deinterleaver is used to use definitely according to determined parity matrix deinterleave scheme and deinterleave from the signal of first adder output;

The check-node decoder is used for connecting check-node by the weighting according to the every row that comprises at determined parity matrix and detects from the probable value of the signal of described deinterleaver output;

Second adder is used for deducting from the signal of described deinterleaver output from the signal of self checking node decoder device output;

Interleaver is used to use the signal that definite interleaving scheme interweaves and exports from second adder according to determined parity matrix, and to variable node decoder device and first adder output interleaved signal; And

Second controller is used for controlling the scheme of deinterleaving and interleaving scheme according to determined parity matrix.

89. according to the device of claim 88, wherein, second parity matrix is the parity matrix that obtains by the part piece that uses the shortening scheme to shorten the predetermined quantity in the part piece of first quantity in first parity matrix.

90. according to the device of claim 89, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

91. according to the device of claim 90, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be listed as the 7th part piece row by the part 1 piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 8th part piece is listed as the 21st part piece row, and will be mapped to parity word corresponding to the part matrix that the 22nd part piece is listed as the 49th part piece row.

92. according to the device of claim 91, wherein, first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

93. according to the device of claim 88, wherein, second parity matrix is the parity matrix that obtains by the part piece that uses grid to cut the predetermined quantity in the part piece that the scheme grid cut second quantity in first parity matrix.

94. according to the device of claim 93, wherein, when encoding rate be 3/7 and the codeword length of piece LDPC sign indicating number be 49N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

95. according to the device of claim 94, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 42N _sThe time, produce second parity matrix by following manner: be mapped to information word by the part matrix that will be listed as the 21st part piece row, and use the grid scheme of cutting to come grid to cut to be listed as 7 predetermined part pieces row in the 49th part piece row at the 22nd part piece corresponding to the part 1 piece of first parity matrix.

96. according to the device of claim 95, wherein, described first parity matrix and second parity matrix are the optimised parity matrixs of its distribution number of degrees.

97. device according to claim 96, wherein, the part piece row that cut by grid are included in the 23rd part piece row in first parity matrix, the 27th part piece row, the 31st part piece row, the 35th part piece row, the 39th part piece row, the 43rd part piece row and the 47th part piece row.

98. according to the device of claim 89, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

99. according to the device of claim 98, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sProduce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

100. according to the device of claim 89, wherein, when encoding rate be 4/5 and the codeword length of piece LDPC sign indicating number be 50N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

101. according to the device of claim 100, wherein, when encoding rate be 1/3 and the codeword length of piece LDPC sign indicating number be 15N _sThe time, produce second parity matrix by following manner: be listed as the 34th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 35th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 12N _sThe time, produce second parity matrix by following manner: be listed as the 29th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 30th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 30N _sThe time, produce second parity matrix by following manner: be listed as the 19th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 20th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row;

Wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 40N _sThe time, produce second parity matrix by following manner: be listed as the 9th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 10th part piece is listed as the 39th part piece row, and will be mapped to parity word corresponding to the part matrix that the 40th part piece is listed as the 49th part piece row.

102. according to the device of claim 89, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

103. according to the device of claim 102, wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 32N _sThe time, produce second parity matrix by following manner: be listed as the 15th part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 16th part piece is listed as the 31st part piece row, and will be mapped to parity word corresponding to the part matrix that the 32nd part piece is listed as the 47th part piece row.

104. according to the device of claim 89, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

105. according to the device of claim 104, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row;

Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

106. according to the device of claim 89, wherein, when encoding rate be 3/4 and the codeword length of piece LDPC sign indicating number be 48N _sThe time, first parity matrix is expressed as:

Wherein, piece is represented the part piece, and number tag is represented the index of corresponding permutation matrix, does not have the piece of number tag to represent the part piece that null matrix is mapped to, and I is that the index of its corresponding permutation matrix of expression is the index of 0 unit matrix, N _sThe size of expression permutation matrix.

107. according to the device of claim 106, wherein, when encoding rate be 2/3 and the codeword length of piece LDPC sign indicating number be 36N _sThe time, produce second parity matrix by following manner: be listed as the 11st part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 12nd part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row; Wherein, when encoding rate be 1/2 and the codeword length of piece LDPC sign indicating number be 24N _sThe time, produce second parity matrix by following manner: be listed as the 23rd part piece row by the 0th part piece that uses the shortening scheme to shorten first parity matrix, to be mapped to information word corresponding to the part matrix that the 24th part piece is listed as the 35th part piece row, and will be mapped to parity word corresponding to the part matrix that the 36th part piece is listed as the 47th part piece row.

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