CN1688014A - Preparing method and application of heterobonded wafer - Google Patents

Abstract

A preparation method and an application of a hetero-bonded wafer relates to the photoelectronic component integration and application filed. Two direct linkage hetero-bonded materials at low temperature are a silicon wafer prepared for ROIC and GaAs wafer for IP films separately, first of all the surface of silicon wafer is smoothed and cleaned in terms of Cu interlink flatness technology in 0.25mum ULSI, then the GaAs wafer with the same clean and smooth surface is aligned, pre-bonded and processed under low temperature with said silicon wafer till they are bonded together directly to get the hetero-bonded material, then its thickness is reduced to 20-30mum and the rest GaAs is selected and etched with ICP high density reacting ions to the ending layer to be etched by a wet process to get the hetero-bonded wafer.

Description

Preparation method and application of heterogeneous bonded wafer

Technical field

The present invention relates to a preparation method and application of a heterogeneous bonding wafer, to be precise, it relates to a low-temperature direct heterogeneous bonding of an infrared detector (IP) material and a silicon-based readout integrated circuit (ROIC) to prepare a heterogeneous bonding Wafer methods and applications for hetero-bonded wafers. It belongs to the technical field of optoelectronic equipment integration and application.

Background technique

Due to the application of infrared focal plane (IRFPA) technology in many fields such as military, environmental protection, civil, industrial and medical, the demand for large-scale IRFPA is constantly growing. However, large-scale IRFPA consists of large-scale quantum wells, HgCdTe and other types of infrared detector photosensitive elements and ROICs, which are directly or indirectly interconnected through indium columns grown separately to form a complete IRFPA. The quality of its inverted interconnection directly affects the final performance and reliability of the IRFPA. In order to reduce the stress on the solder joint-indium column and improve the reliability of the device, methods such as substrate thinning, substrate removal, increasing the height of the indium column, and filling epoxy materials have been developed, but the above methods inevitably increase the complexity of the process. To a certain extent, there is still considerable stress at the solder joints, which increases the probability of failure of the IRFPA photosensitive element.

The current IRFPA upside-down interconnection preparation method has the following problems:

1. IP-ROIC adopts the method of direct reverse interconnection or indirect reverse interconnection, under the action of repeated thermal cycle load of 300-30K cycles, the three materials of indium column, GaAs substrate of detector array and silicon-based ROIC The thermal expansion coefficient (CTE) does not match, and the large stress change causes the viscoplastic deformation of the indium column, the solder joints of the indium column fall off, crack, etc., resulting in the performance degradation or even failure of the IRFPA.

2. There are two major difficulties in heteroepitaxial monolithic integration or partial heteroepitaxial monolithic integration: 1) Silicon and GaAs and other III-V compound materials have a 4% lattice mismatch, resulting in high fault density. 2) The thermal expansion coefficient of GaAs is twice that of silicon, and two-dimensional stress will be generated on the surface of GaAs after the epitaxial growth is completed.

In order to overcome the ills brought about by the mixed packaging of IP with GaAs substrate and silicon-based ROIC and the use of heterogeneous epitaxy, it is necessary to develop a wafer-level, monolithic integration of heterogeneous materials with a certain scale that is compatible with standard CMOS and BiMOS processes technology.

Contents of Invention

The first technical problem to be solved by the present invention is to introduce a method for preparing heterogeneously bonded wafers. The method has the advantages of low manufacturing cost, high mechanical strength and good reliability of the product.

The technical scheme of the present invention to solve the above-mentioned technical problems is: the two heterogeneous materials directly bonded at low temperature are silicon wafers prepared with ROIC and GaAs wafers prepared with IP thin films. Mechanical planarization process to make the surface of the silicon wafer smooth, flat and clean; then, at low temperature, align and pre-bond the GaAs wafer with the same smooth, flat and clean surface and the silicon wafer , low-temperature heat treatment, until the two heterogeneous wafers are directly bonded together to obtain a heterogeneous bond; then thin the thickness of the heterogeneous bond GaAs to 20-30 μm; then use ICP high-density reactive ion selection Etch the remaining GaAs to the stop layer; finally use wet etching to remove the stop layer to obtain the product, a heterogeneous bonded wafer. ULSI is an acronym for 'Ultra Large Scale Integration'.

The technical solution of the present invention will now be described in detail in conjunction with the accompanying drawings. A method for preparing heterogeneous bonding wafers. Two heterogeneous wafers to be bonded are respectively a silicon wafer prepared with ROIC and a GaAs wafer prepared with IP thin film. Operation steps:

The first step chemical mechanical planarization

First put the silicon wafer into the PECVD vacuum chamber, and grow Si ₃ N ₄ and SiO ₂ films in sequence on the side prepared with ROIC according to the process conditions of the double-layer Damascus structure copper wiring in 0.25 μm ULSI, and then, Take out the processed silicon wafer, and perform chemical mechanical planarization on its bonding surface according to the chemical mechanical planarization process of copper interconnection in 0.25 μm ULSI, so that the bonding surface is smooth, clean and flat To be bondable, that is, the smoothness reaches the sub-nanometer level;

Step 2 Surface treatment of wafers to be heterogeneously bonded

Surface treatment of the silicon wafer processed through the first step: in a vacuum chamber, use inductively coupled plasma reactive ion etching to carry out oxygen plasma activation on the surface of the silicon wafer processed through the first step, and the surface treatment of the GaAs wafer: put The GaAs wafer is immersed in a saturated _SeS solution to remove the intrinsic oxide layer on the surface of the GaAs wafer and generate a dense sulfide layer; it is characterized in that,

Step 3 Low temperature direct heterogeneous bonding

Under the conditions of ultra-clean room, ultra-vacuum, room temperature and microscope, align the GaAs wafer with the silicon wafer processed in the second step, pre-bond at 150°C for 0.5-3 hours, and attach the two wafers , at room temperature to 400°C, low temperature heat treatment for 0.5 to 3 hours, and the two wafers continue to stick together for 5 to 20 hours to complete low temperature direct bonding to obtain a heterogeneous bond;

Step 4 Thinning GaAs in Heterobonds

Use the conventional GaAs thinning process to thin the GaAs thickness of the heterogeneous bond obtained in the third step to 20-30 μm, and then use ICP high-density Reactive ion etching of the remaining GaAs wafer to the stop layer;

The fifth step is to terminate the layer

Use wet etching to remove the termination layer exposed on the surface of the heterogeneous bond after the fourth step treatment, ultrasonically wash with deionized water until the pH value of the washing water is neutral, dehydrate, and blow dry with nitrogen to obtain the product, heterogeneous bond Chip.

The second technical problem to be solved by the present invention is to provide the product prepared by the above method, the application of heterogeneous bonded wafers, that is, to provide a method for making IRFPA of IP-ROIC with heterogeneous bonded wafers.

The technical solution of the present invention for solving the above-mentioned technical problems is described in detail as follows.

A kind of method for making the IRFPA of IP-ROIC with heterogeneous bonded wafer, it is characterized in that, use standard IC process to make the IRFPA of IP-ROIC in heterogeneous bonded wafer: use IP standard process to the IRFPA of heterogeneous bonded wafer Conduct photolithography and dry etching on the electrode surface, pattern positioning, and expose the lower electrode area; use the ULSI standard process to open the lead hole; use the PECVD process to passivate the IP quantum well side wall area; use photolithography, electron beam evaporation or sputtering The upper electrode, the lower electrode and the lead are made by the laser technology, and the IRFPA of the IP-ROIC made of the heterogeneous bonded wafer is obtained.

Outstanding advantage of the present invention is:

1. The bonding conditions of Si/GaAs heterogeneous wafers are not affected by the crystal properties of the two materials to be bonded, which is an effective way to solve the lattice mismatch, and can be reduced by pre-bonding and low-temperature heat treatment. Thermal stress on the bonding surface of two heterogeneous wafers.

2. Silicon with light weight, high thermal conductivity and ultra-high mechanical strength is an ideal support for GaAs. The GaAs wafer prepared with IP film and the silicon wafer prepared with ROIC are directly heterogeneously bonded at low temperature, and the cost is low, which is the best way to obtain low price The fundamental guarantee of IRFPA of IP-ROIC.

3. Compatible with standard IC technology, simple operation, easy implementation, no cross-contamination problem.

Description of drawings

FIG. 1 is a schematic cross-sectional view of two heterogeneous wafers to be bonded placed in alignment. The upper and lower wafers are GaAs wafer prepared with IP thin film and silicon wafer prepared with ROIC respectively. In the GaAs wafer, 1 is the substrate, 2 is the termination layer, 3 is the IP lower electrode layer, 4 is the IP thin film, and 5 is the IP upper electrode layer. In the silicon wafer, 6 is the ROIC circuit, and 7 is the silicon substrate.

Fig. 2 is a schematic cross-sectional view of Si ₃ N ₄ and SiO ₂ thin films deposited and grown on a silicon wafer prepared with ROIC. ₈ of them are _Si3N4 and _SiO2 films.

Fig. 3 is a schematic cross-sectional view of a heterobond.

FIG. 4 is a schematic cross-sectional view of removing heterobonds from the GaAs substrate 1 .

Fig. 5 is a schematic cross-sectional view of a hetero-bonded wafer.

Detailed ways

The technical solution of the present invention will now be described in detail in conjunction with the accompanying drawings and embodiments. The embodiment is operated completely according to the above-mentioned operation steps.

Example 1 Preparation of Heterogeneous Bonded Wafer by Direct Heterogeneous Bonding at Low Temperature

The diameter of two heterogeneous wafers to be bonded is 1-8 inches. The two heterogeneous wafers to be bonded are respectively a silicon wafer prepared with ROIC and a GaAs wafer prepared with IP thin film. The smoothness of the bonding surface of the silicon wafer does not meet the bonding requirements. The bonding surface of the GaAs wafer is in the shape of a mirror surface, which has met the bonding requirements.

First put the silicon wafer into the PECVD vacuum chamber, and grow Si ₃ N ₄ and SiO ₂ thin films 8 sequentially on the side prepared with ROIC according to the process conditions of 0.25 μm ULSI double-layer damascene copper wiring. See Figure 2. Take out the silicon wafer, fix it in a special chemical mechanical planarization equipment according to the chemical mechanical planarization process of copper interconnection in 0.25 μm ULSI, and perform chemical mechanical planarization treatment on its bonding surface. SOG abrasives with a weight ratio of solvent to silicon oxide of 4:1, the particle size of the abrasives is 0.03-0.14 μm, ultrasonically cleaned with deionized water for 15-25 minutes, so that the bonding surface of the silicon wafer reaches a mirror surface, Clean, flat and bondable, i.e. with a sub-nanometer finish.

Put the above-mentioned processed silicon wafer into a vacuum chamber, and perform oxygen plasma activation on it by ICP reactive ion etching. The GaAs wafer is soaked in a saturated _SeS solution for 30 minutes to remove the intrinsic oxide layer on the GaAs surface and form a dense sulfide bonding active layer.

In the ultra-clean room, ultra-vacuum, room temperature and microscope, the GaAs wafer is first aligned with the silicon wafer whose bonding surface is mirror-like, as shown in Figure 1, pre-bonded at 150 ° C for 0.5 hour, and then the two The wafers are adhered to each other, and the two heterogeneous wafers are subjected to low-temperature heat treatment at room temperature to 400° C. for 2 hours, and then adhered to two heterogeneous wafers for 15 hours to complete low-temperature direct bonding to obtain a heterogeneous bond. See Figure 3.

Fix the heterogeneous bonding compound obtained above in a special thinning device, with the substrate 1 facing down, and the abrasive used is SOG abrasive with a weight ratio of solvent to silicon oxide of 4:1, and the particle size of the abrasive is The size is 0.5-1.5 μm, and the substrate 1 is thinned to 25 μm. Put the above-treated heterogeneous bond into the ICP reactor, with the bottom of the substrate 1 facing up, and remove the remaining substrate 1 until the stop layer is etched under the etching conditions of GaAs/stop layer etching ratio ≥ 1000 2. See Figure 4.

Take the heterogeneous bond from the ICP reactor, put it into the stop layer corrosion solution, rinse off the stop layer, expose the IP lower electrode layer 3, wash with deionized water for 15 minutes, dehydrate, and blow dry with nitrogen , to obtain a product, a heterogeneous bonded wafer. See Figure 5.

Example 2 Making IRFPA of IP-ROIC with Heterogeneous Bonded Wafer

Use standard IC technology to make IP-ROIC IRFPA on heterogeneous bonded wafers: use IP standard technology to perform photolithography, dry etching, and pattern positioning on the electrode surface of heterogeneous bonded wafers to expose the lower electrode area; The ULSI standard process is used to open the lead hole; the PECVD process is used to passivate the IP quantum well side wall area; the upper electrode, the lower electrode and the lead are produced by photolithography, electron beam evaporation or sputtering process, and the IP produced by the heterogeneous bonding wafer is obtained. -IRFPA for ROIC.

Claims (5)

1, a kind of preparation method of heterobonded wafer, two heterogeneous wafers for the treatment of bonding are respectively that preparation has the silicon wafer of ROIC and the GaAs wafer that preparation has the IP film, operating procedure:

First step chemical-mechanical planarization

Earlier described silicon wafer is put into the PECVD vacuum chamber, the process conditions that connect up according to double-deck damascene structure copper among the 0.25 μ m ULSI have the one side of the ROIC Si that grows in order in its preparation ₃N ₄And SiO ₂Film, then, take out treated described silicon wafer, with its chemical-mechanical planarization technology according to the copper-connection among the 0.25 μ m ULSI, its bonding face is carried out chemical mechanical planarization, this bonding face is smooth, cleaning, smooth to bonding but make, and promptly fineness reaches the degree of Subnano-class;

Second step was treated the surface treatment of the wafer of heterogeneous bonding

The surface treatment of the silicon wafer of handling through the first step: in vacuum chamber, use the inductively coupled plasma reactive ion etching, oxygen plasma activation, the surface treatment of GaAs wafer: the saturated SeS of GaAs wafer are carried out in surface to the silicon wafer handled through the first step ₂Solution soaks, and removes the native oxide layer on the GaAs wafer surface, generates fine and close sulfurized layer; It is characterized in that,

The direct heterogeneous bonding of the 3rd step low temperature

Under clean room, ultravacuum, room temperature and microscopical condition, with GaAs wafer and the silicon wafer contraposition of handling through second step, gave bonding under 150 ℃ 0.5～3 hour, described two wafers are close to, under room temperature～400 ℃, Low Temperature Heat Treatment 0.5～3 hour, described two plates continues to be close to 5～20 hours, finish low-temperature-direct-bonding, get heterogeneous key compound;

GaAs in the heterogeneous key compound of the 4th step attenuate

Go on foot thickness to 20～30 μ m of the GaAs of the heterogeneous key compound that obtains with conventional GaAs reduction process attenuate the 3rd, then under the selective etching condition of etching ratio 〉=1000 of GaAs/ stop layer, with the remaining GaAs wafer of ICP high density reactive ion etching to stop layer;

The 5th step was removed stop layer

Be exposed to the stop layer on heterogeneous key compound surface after handling with wet method etching off the 4th step, the deionized water supersound washing is neutral to the pH value of washings, dehydration, and nitrogen dries up, and obtains product, heterobonded wafer.

2, preparation method according to claim 1 is characterized in that, two treat bonding the diameter of heterogeneous wafer be 1～8 inch.

3, preparation method according to claim 1, it is characterized in that, the abrasive material that is adopted when in the first step bonding face of described silicon wafer being carried out chemical mechanical planarization is that the weight ratio of solvent and silica is 4: 1 a SOG abrasive material, the particle of abrasive material is of a size of 0.03～0.14 μ m, with time of deionized water ultrasonic cleaning be 15～25 minutes.

4, preparation method according to claim 1, it is characterized in that, the abrasive material that is adopted during with the wafer of the described GaAs of conventional GaAs reduction process attenuate in the 4th step is that the weight ratio of solvent and silica is 4: 1 a SOG abrasive material, and the particle of abrasive material is of a size of 0.5～1.5 μ m.

5, a kind of method of making the IRFPA of IP-ROIC with the heterobonded wafer of the described method preparation of claim 1, it is characterized in that, make the IRFPA of IP-ROIC at heterobonded wafer of the IC technology of standard: the electrode surface of heterobonded wafer is carried out photoetching, dry etching with the IP standard technology, the figure location exposes the bottom electrode zone; Leave fairlead with the ULSI standard technology; With pecvd process passivation IP quantum well sidewall areas; Make top electrode, bottom electrode and lead-in wire with photoetching, electron beam evaporation or sputtering technology, the IRFPA of the IP-ROIC that handy heterobonded wafer is made.

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