CN1290070C - Plasma display panel and its drive method - Google Patents

Abstract

Disclosed is a PDP driving method having a misfiring erase period between reset and address periods. Large amounts of positive and negative charges are respectively formed on scan and sustain electrodes because of an unstable reset operation in the reset period. Because of the charges, discharging can occur between the scan and sustain electrodes in the sustain period even without addressing in the address period. In the misfiring erase period, a voltage is applied between the scan and sustain electrodes to generate discharging and respectively form negative and positive charges on the scan and sustain electrodes. An erase pulse is then applied to erase the negative and positive charges respectively formed on the scan and sustain electrodes.

Description

Plasma display panel and its driving method

technical field

The present invention relates to a plasma display panel (PDP) and its driving method, in particular to a PDP driving method, which can prevent discharge cells not selected in the address period from being discharged in the sustain period.

Background technique

A PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. A PDP may include more than a few million counts of pixels in matrix form, where the number of pixels depends on the size of the PDP. The structure of the PDP will now be described with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a partial perspective view of a PDP, and FIG. 2 schematically shows an electrode arrangement of the PDP.

As shown in FIG. 1, the PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. The scan electrodes 4 and the sustain electrodes 5 are formed in pairs on the glass substrate 1 in parallel, and the dielectric layer 2 and the protective film 3 cover the scan electrodes 4 and the sustain electrodes. A plurality of address electrodes 8 are formed on the glass substrate 6 , and the address electrodes 8 are covered with an insulating layer 7 . Isolation ribs 9 are formed on the insulating layer 7 between the address electrodes 8 , and phosphors 10 are formed on the surface between the insulating layer 7 and the isolation ribs 9 . Glass substrates 1 and 6 are disposed facing each other and have a discharge space between glass substrates 1 and 6 , enabling scan and sustain electrodes 5 to cross address electrodes 8 . As shown, a discharge cell 12 is formed in the discharge space 11 between the address electrode 8 and the intersection of a pair of scan electrodes 4 and sustain electrodes 5 .

As shown in FIG. 2, the electrodes of the PDP have an n×m matrix form. The address electrodes A1 to Am are arranged in a column direction, and n scan electrodes Y1 to Yn and n sustain electrodes X1 to Xn are arranged in a row direction.

Usually, a single frame is divided into multiple sub-fields in the PDP, and the image to be displayed is represented by the combination of the sub-fields. As shown in FIG. 3, each sub-field has a reset period (reset), an address period, and a sustain period. In the reset period, the wall charge formed in the previous sustain discharge is eliminated and the wall charge is established, so that the next addressing can be performed stably. In the address period, the activated cell and the switched-off cell are selected, and wall charges are accumulated on the activated cell (ie, the addressed cell). In the sustain period, a sustain discharge is performed to display an actual image on the addressed cells.

FIG. 3 shows driving waveforms of a conventional PDP. As shown, the reset period includes an erase period (a), a ramp-up period (b), and a ramp-down period (c).

In the erasing period (a), an erasing ramp voltage gradually rising from 0 volts (V) to Ve volts (V) is applied to the sustain electrode X. In this way, the wall charges formed on the sustain electrode X and the scan electrode Y are gradually eliminated. The wall charges referred to herein refer to charges accumulated on the electrodes and corresponding electrodes formed closest to the walls (eg, dielectric layers) of the discharge cells. Wall charges do not actually contact the electrodes themselves, but are described herein as being "formed on", "stored on" and/or "accumulated on" said electrodes. In addition, the wall voltage referred to here refers to the potential present on the wall of the discharge cell due to the wall charges.

In the ramp-up period (b), the address electrode A and the sustain electrode X are maintained at 0V, and a ramp waveform gradually rising from Vs volts to Vset volts is applied to the scan electrode Y. When the ramp waveform rises, a first fine reset is generated from the scan electrode Y to the address electrode A and the sustain electrode X in all discharge cells. Thus, negative wall charges are stored on the scan electrode Y, while positive charges are stored on the address electrode A and the sustain electrode X at the same time.

In the ramp-down period (c), while the sustain electrode X is held at Ve volts, a ramp waveform gradually falling from Vs volts to 0V is supplied to the scan electrodes Y. When the ramp waveform falls, the second fine reset occurs in all discharge cells. As a result, the negative wall charges of the scan electrode Y decrease, and the positive wall charges of the sustain electrode X decrease.

When the reset period operates normally, the wall charges of the scan electrode Y and the sustain electrode X are eliminated, but unstable discharge may occur due to unstable reset. Unstable discharges include: the first case in which the discharge is generated by a self-elimination phenomenon that occurs when the voltage of the scan electrode Y drops to Vset after a strong discharge in the ramp-up period, and the second case in which the strong discharge occurs during the ramp-up period and the ramp-down period, and a third case where a strong discharge occurs during the ramp-down period.

In the first case, the cancellation function is performed according to self-cancellation. However, in the second case, positive wall charges are generated on the scan electrode Y and negative wall charges are generated on the sustain electrode X due to the strong discharge during the ramp-down period. In this case, if the wall voltage Vwxy1 caused by the wall charges formed on the scan electrode Y and the sustain electrode X satisfies Equation 1, a sustain discharge can be generated in the sustain period even when no addressing occurs in the address period .

V _wxy1 +V _s >V _f (1)

Here Vwxy1 is the wall voltage formed between the scan electrode Y and the sustain electrode X due to the strong discharge in the ramp-down period; Vs is the voltage difference between the scan electrode Y and the sustain electrode X due to the sustain pulse provided in the sustain period ; And Vf is the discharge trigger voltage between the scan electrode Y and the sustain electrode X.

Therefore, when the conventional driving method of FIG. 3 is used in the PDP, due to the strong discharge in the ramp-down period of the reset period, sustain discharge may occur in those discharge cells that are not triggered.

Contents of the invention

In an exemplary embodiment of the present invention, false triggering due to strong discharge during the reset period is reduced or prevented.

To prevent or minimize such false triggering, charges formed by unstable reset operations are removed.

In an exemplary embodiment of the present invention, there is provided a method of driving a PDP, the PDP includes a plurality of first electrodes and second electrodes formed in parallel on a first substrate, and a plurality of electrodes connected to the first and second electrodes A third electrode intersecting and formed on the second substrate, wherein the adjacent first, second and third electrodes define each of a plurality of discharge cells. The method includes: setting a plurality of discharge cells in the first reset period; further setting these discharge cells in the second reset period; selecting at least one discharge cell from the plurality of discharge cells in the address period; The at least one discharge cell sustains discharge, wherein the discharge is induced between the first and second electrodes during the second reset period.

In another exemplary embodiment, the further setting includes providing discharge elimination pulses to the plurality of discharge cells under a predetermined condition. The discharge elimination pulse has discharge and elimination functions.

In still another exemplary embodiment, the predetermined condition includes a case where abnormal charges are formed in the first reset period, and the abnormal charges formed in the first reset period are discharged and eliminated in response to a discharge elimination pulse.

In yet another exemplary embodiment, the abnormal charges include first and second charges respectively formed on the first and second electrodes in the first reset period, and the voltage caused by the first and second charges is sufficient Discharge cells not selected in the address period are maintained in the sustain period.

In a further exemplary embodiment, the second reset period includes a first period and a second period, and the further setting comprises: supplying the first voltage to the first electrode during the first period, and A second voltage is provided to the second electrode during the period.

In yet a further exemplary embodiment, said first voltage, plus a voltage caused by said first and second charges, is sufficient to generate a discharge between said first and second electrodes.

In yet a further exemplary embodiment, charge is accumulated on said first and second electrodes in response to a discharge in a first period, and said second voltage is used to dissipate charges on said first electrode in a second period. Charge formed in one phase.

In another exemplary embodiment, the second voltage gradually changes from the third voltage to the fourth voltage.

In yet another exemplary embodiment, said second voltage plus the voltage caused by the charge formed during the first period is sufficient to generate another discharge between said first and second electrodes, and responds during the second period to The charges accumulated in the first and second electrodes during the another discharge are less than a predetermined amount of charges.

In yet another exemplary embodiment, when the first voltage is supplied to the first electrode during the second reset period, the second voltage is supplied to the second electrode.

In a further exemplary embodiment, the first voltage is supplied to the first electrode for a predetermined period, and the voltage difference between the first and second voltages, plus the voltage caused by the first and second charges, is sufficient A discharge is generated between the first and second electrodes, and charges accumulated on the first and second electrodes in response to the discharge for a predetermined period are less than a predetermined amount of charges.

In yet a further exemplary embodiment, the range of the predetermined amount is to prevent unselected discharge cells from sustaining discharge in the sustain period.

In a further exemplary embodiment, the first voltage changes gradually from the third voltage to the fourth voltage.

In a further exemplary embodiment, at least a plurality of discharge cells are set again in at least one additional reset period. In another exemplary embodiment of the present invention, there is provided a method of driving a PDP including a plurality of first and second electrodes formed in parallel on a first substrate, and a plurality of electrodes connected to the first and second electrodes. The electrodes intersect and form a third electrode on the second substrate, wherein the adjacent first, second and third electrodes define each of a plurality of discharge cells. The method includes: when a predetermined condition is provided in the reset period, setting a plurality of discharge cells; the setting includes generating discharge and eliminating, which includes: providing a predetermined condition to these discharge cells under the reset period. a discharge pulse for generating a discharge between the first and second electrodes, and supplying these discharge cells with an erasing pulse for erasing charges formed on the first and second electrodes in response to the discharge; or under a predetermined condition An erasing pulse for generating a discharge and erasing charges between the first and second electrodes is supplied to the plurality of discharge cells.

In still another exemplary embodiment, the predetermined condition includes a case that abnormal charges have been formed in the reset period.

In yet another exemplary embodiment, the abnormal charges include first and second charges respectively formed on the first and second electrodes during the reset period, and the voltage caused by the first and second charges is sufficient to make the The discharge cells not selected in the address period are sustain-discharged in the sustain period.

In a further exemplary embodiment of the present invention, a PDP includes: a first substrate; a plurality of first and second electrodes respectively formed on the first substrate substantially in parallel; a second substrate interposed by a predetermined interval; a plurality of third electrodes intersecting the first and second electrodes and formed on the second substrate; A drive circuit that provides a drive signal to the discharge unit, wherein the drive circuit supplies a first voltage to the first electrode and a second voltage to the second electrode between the reset and address periods, and the first and second voltages will Abnormal charges among charges formed in the reset period are eliminated, wherein discharge is induced between the first and second electrodes during the removal of abnormal charges.

In a further exemplary embodiment, the drive circuit supplies at least the first voltage to the first electrode and the second voltage to the second electrode again between the reset and address periods.

Description of drawings

The drawings illustrate exemplary embodiments of the present invention in conjunction with the description, and together with the description, explain the principle of the present invention.

Fig. 1 is a partial perspective view of a PDP;

Fig. 2 shows an electrode arrangement of a PDP;

Fig. 3 is a driving waveform diagram of a conventional PDP;

4 is a driving waveform diagram of a PDP according to an exemplary embodiment of the present invention;

5A to 5D are wall charge distribution diagrams with respect to the driving waveforms of FIG. 4, respectively;

6A to 6C are wall charge distribution diagrams when an unstable reset operation occurs in the driving waveform of FIG. 4, respectively;

7 and 8 respectively show a PDP drive waveform in another exemplary embodiment of the present invention; and

9 to 20 are respectively a driving waveform diagram of a PDP in a further exemplary embodiment of the present invention.

Detailed ways

In the detailed description that follows, certain exemplary embodiments of the invention are shown and described, simply by way of illustration. As will be realized, the described exemplary embodiments may be changed in various different ways, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.

FIG. 4 is a driving waveform diagram of a PDP according to an exemplary embodiment of the present invention. 5A to 5D are diagrams of wall charge distribution with respect to driving waveforms of FIG. 4, respectively. 6A to 6C are respectively diagrams of wall charge distribution when a strong discharge occurs in a ramp-down period of a reset period in the drive waveform of FIG. 4 . 7 and 8 respectively show PDP driving waveforms in another exemplary embodiment of the present invention.

As shown in FIG. 4 , the driving waveform according to an exemplary embodiment of the present invention includes a reset period 100 , a misfiring removal period 200 , an address period 300 , and a sustain period 400 . The reset period 100 includes a clear period 110 , a ramp-up period 120 , and a ramp-down period 130 .

In the erasing period 110 of the reset period 100, the charges formed and maintained in the sustaining period of a previous subfield are eliminated. During the ramp-up period 120, wall charges are formed on the scan electrode Y, the sustain electrode X, and the address electrode A. Referring to FIG. In the ramp-down period 130, part of the wall charges formed in the ramp-up period 120 is eliminated so that addressing can be easily performed.

In the false trigger elimination period 200, the wall charges of the scan electrode Y and the sustain electrode X formed by the unstable strong discharge in the ramp-down period 130 are eliminated. In this way, a charge state capable of normally emitting light can be formed by further setting the discharge cells. Therefore, the false trigger elimination period 200 can also be regarded as a second reset period, which is used as a supplement to the reset period 100 .

In the address period 300, a discharge cell in which a sustain discharge occurs is selected from a plurality of discharge cells. In the sustain period 400 , sustain pulses are sequentially supplied to the scan electrode Y and the sustain electrode X for sustaining the discharge cells selected in the address period 300 .

The PDP includes a scan/sustain drive circuit for supplying a drive voltage to the scan electrode Y and the sustain electrode X, and an address drive circuit for supplying a drive voltage to the address electrode A in the corresponding periods 100 and 400 .

Referring to FIGS. 5A to 5D , a normal reset operation that is normally generated in response to the driving waveform according to the exemplary embodiment of FIG. 4 will now be described in detail.

During the sustain period of a previous subfield, negative wall charges accumulate on the scan electrode Y and positive wall charges accumulate on the sustain electrode X due to the sustain discharge between the scan electrode Y and the sustain electrode X. In the erasing period 110, when the scan electrode Y is maintained at a reference voltage, a ramp waveform gradually rising from the reference voltage to Ve volts is supplied to the sustain electrode X. The reference voltage is set to 0V in the exemplary embodiment of FIG. 4 . Thus, the wall charges formed on the sustain electrode X and the scan electrode Y are gradually eliminated.

Next, in the ramp-up period 120, when the sustain electrode X is maintained at the reference voltage, a ramp waveform gradually rising from Vs volts to Vset is applied to the scan electrode Y. In this case, Vs is smaller than the discharge trigger voltage Vf between the scan electrode Y and the sustain electrode X, and Vset is larger than the discharge trigger voltage Vf. Fine resetting from the scan electrode Y to the address electrode A and the sustain electrode X occurs when the ramp waveform rises, respectively. As a result, negative wall charges accumulate on the scan electrode Y, while positive wall charges accumulate on the address electrode A and the sustain electrode X, as shown in FIG. 5A.

In the ramp-down period 130, a ramp waveform gradually falling from Vs to the reference voltage is supplied to the scan electrode Y while the sustain electrode X is maintained at Ve. Fine resetting occurs in all discharge cells when the ramp waveform falls. As a result, as shown in FIG. 5B , the negative wall charges of the scan electrode Y and the positive wall charges of the sustain electrode X decrease. Likewise, the positive wall charge of the address electrode A is also controlled to a value suitable for the addressing operation.

In the false trigger elimination period 200, a square wave pulse having Vs volts is supplied to the scan voltage Y while the sustain electrode X is maintained at the reference voltage. In this case, when the charges are normally eliminated in the ramp-down period 130, the wall charges formed between the scan electrode Y and the sustain electrode X become a negative voltage -Vwxy2 with respect to the scan electrode Y. The voltage between the scan electrode Y and the sustain electrode X becomes (Vs-Vwxy2), which is not greater than the discharge trigger voltage Vf; therefore, discharge does not occur. Therefore, as shown in FIG. 5C, the wall charge distribution in the discharge cell remains as in FIG. 5B.

Next, in the false trigger erasure period 200, while the scan electrode Y is held at the reference voltage, an erasure ramp waveform gradually rising from the reference voltage to Ve is supplied to the sustain electrode X. Since the charge distribution on the scan electrode Y and the sustain electrode X has the same period as before, and no discharge occurs due to the erasing ramp waveform, the wall charges remain as shown in FIG. 5B as shown in FIG. 5D.

In the address period 300, scan pulses are sequentially supplied to the scan electrodes Y to select the discharge cells, and the address pulses are supplied to a desired address electrode A among the address electrodes A, which is the same as the scan pulse supplied to the scan pulses. The electrodes Y intersect. A discharge occurs between the scan voltage Y and the address electrode A according to the voltage difference formed by the scan pulse and the address pulse. When the discharge between the scan electrode Y and the address electrode A starts to form wall charges on the scan electrode Y and the sustain electrode X, the discharge between the scan electrode Y and the sustain electrode X occurs.

In the sustain period 400, sustain pulses are sequentially supplied to the scan electrode Y and the sustain electrode X. Referring to FIG. The sustain pulse causes the voltage difference between scan electrode Y and sustain electrode X to alternate between Vs and -Vs. Vs is less than the discharge trigger voltage between the scan electrode Y and the sustain electrode X. When addressing is performed according to the address period 300, when the wall voltage Vwxy3 is formed between the scan electrode Y and the sustain electrode X, discharge occurs in the scan electrode Y and the sustain electrode X due to the wall voltages Vwxy3 and Vs.

Next, referring to FIGS. 6A to 6C , the case where a strong discharge occurs in the ramp-down period 130 of the PDP driving waveform according to the exemplary embodiment of FIG. 4 will be described in detail.

When a strong discharge occurs due to an unstable reset operation in the ramp-down period 130, positive charges accumulate on the scan electrode Y and negative charges accumulate on the sustain electrode X as shown in FIG. 6A. In this case, the wall voltage Vwxy1 formed by the wall charges generated on the scan electrode Y and the sustain electrode X satisfies the aforementioned Equation 1. Therefore, unless the charges are eliminated/reduced in the inserted false trigger elimination period 200, sustain discharge is generated in the sustain period even when no addressing occurs in the address period.

When Vs is supplied to the scan electrode Y and the reference voltage is supplied to the sustain electrode X in the false trigger elimination period 200, due to the wall voltage Vwxy1 and Vs between the scan electrode Y and the sustain electrode X, the voltage between the scan electrode Y and the sustain electrode X The voltage (Vwxy1+Vs) between X becomes larger than the discharge trigger voltage Vf. Accordingly, a discharge occurs between the scan electrode Y and the sustain electrode X, and a large amount of negative charges accumulates on the scan electrode Y and a large amount of positive charges accumulates on the sustain electrode X as shown in FIG. 6B.

Next, in the latter part of the false trigger erasing period 200, an erasing ramp waveform gradually rising from the reference voltage to Ve is supplied to the sustain electrode X to perform an erasing operation. As shown in FIG. 6C, due to the ramp waveform, the wall charges formed on the scan electrode Y and the sustain electrode X are eliminated, and the wall voltage between the scan electrode Y and the sustain electrode X becomes small. Accordingly, the sum of the wall voltage of Vs volts supplied between the scan electrode Y and the sustain electrode X and during the sustain period 300 becomes smaller than the discharge trigger voltage Vf. Therefore, when no addressing occurs during the address period 300, no discharge occurs during the sustain period 400. Referring to FIG.

In the exemplary embodiment of FIG. 4, Vs volts are supplied to the scan electrode Y and Ve is supplied to the sustain electrode X in the false trigger elimination period 200 to simplify the driving circuit. However, differently from this, different voltages may be supplied to the scan electrode Y and the sustain electrode X when the discharge condition in the false trigger elimination period 200 is satisfied. In addition, in the exemplary embodiment of FIG. 4 , the reference voltage is set to 0V, but in other embodiments, the reference voltage can also be set to -Vs/2 and/or other suitable voltages.

Referring to FIG. 7, the driving voltage supplied to the scan electrode Y and the sustain electrode X in the corresponding periods 100, 200, 300 and 400 is generally reduced to Vs/2. Therefore, the voltage level for the driving circuit becomes small, and low-voltage components can be used for the driving circuit. In another embodiment, the voltages for the respective periods 100 to 400 may be different. For example, referring to FIG. 8, in the erasing period 110, the voltage supplied to the sustain electrode X is maintained at the voltage Ve, and a ramp waveform gradually falling from the sustain voltage to the reference voltage is supplied to the scan electrode Y. Thus, the voltage difference between the sustain electrode X and the scan electrode Y in the erasing period 110 has a slope similar to the PDP voltage waveform diagram of FIG. 4 .

In the exemplary embodiment of FIG. 4 , the discharge voltage and the cancellation ramp waveform are used in the false trigger cancellation period 200 . Other waveforms may be used in other embodiments. Referring to FIGS. 9 to 13 , certain exemplary embodiments using the PDP voltage waveform different from FIG. 4 in the false trigger elimination period 200 (also referred to as the second reset period) will now be described.

9 to 13 are PDP driving waveform diagrams according to other exemplary embodiments of the present invention, respectively.

Referring to FIG. 9 , the driving waveforms are similar to those in FIG. 4 except that a circular waveform is used instead of the ramp waveform in the false trigger elimination period 200 . In the portion before the false trigger elimination period 200, a square-wave pulse having Vs volts is supplied to the scanning electrode Y. In the portion following the false trigger elimination period 200, the sustain electrode X is supplied with a circular voltage rising from the reference voltage to Ve volts in a convexly curved form (ie, with a decreasing slope).

After the strong discharge occurs in the ramp-down period 130 , when Vs is supplied in the preceding period of the false trigger elimination period 200 , the discharge occurs. Therefore, negative charges are accumulated on the scan electrode Y, and positive charges are accumulated on the sustain electrode X. Referring to FIG. These charges are eliminated in the latter part of the false trigger elimination period 200 due to the circular voltage rising to Ve volts.

Referring to FIG. 10, different from the waveforms of FIG. 4, in the false trigger elimination period 200, a square wave pulse is supplied to the sustain electrode X, and a ramp waveform is supplied to the scan electrode Y. Referring to FIG. Specifically, when the scan electrode Y is held at Vs volts in the preceding period of the false trigger elimination period 200, a square wave pulse having a reference voltage is supplied to the sustain electrode X. Since the voltage difference between the scan electrode Y and the sustain electrode X is kept at Vs volts as in the exemplary embodiment of FIG. 4, when an excessive discharge occurs in the ramp-down period 130, Discharge occurs between them. When the sustain electrode X is held at Ve volts in the latter part of the false trigger elimination period 200, a ramp waveform falling from Vs to the reference voltage is supplied to the scan electrode Y. Charges formed by the discharged scan electrode Y and sustain electrode X in the preceding period of the false trigger elimination period 200 are eliminated due to the ramp waveform. In another embodiment, a circular waveform similar to that used in the exemplary embodiment of FIG. 9 may be used in place of the ramp waveform.

Referring to FIG. 11 , a driving waveform according to another exemplary embodiment is similar to that in FIG. 4 except that a narrow pulse is provided instead of a canceling ramp voltage in the latter part of the false trigger canceling period 200 . Specifically, when the scan electrode Y is maintained at the reference voltage at the end of the false trigger elimination period 200, a narrow pulse of Ve volts is supplied to the sustain electrode X.

When a strong discharge occurs in the ramp-down period 130, a discharge occurs between the scan electrode Y and the sustain electrode X in the preceding period of the false trigger erasure period 200, and the state of the wall charges becomes as shown in FIG. 6B. In this case, when the reference voltage is supplied to the scan electrode Y and the Ve voltage is supplied to the sustain electrode X, since the wall charge distribution of FIG. 6B and the voltage difference between the scan electrode Y and the sustain electrode X The wall voltage Vwxy4 is formed, and the discharge occurs between the scan electrode Y and the sustain electrode X. However, due to the narrow width of the Ve voltage pulse supplied to the sustain electrode X, the charges formed by the discharge are not collected on the scan electrode Y and the sustain electrode X, but are eliminated. Therefore, the state of the wall charges becomes as shown in FIG. 6C.

A similar modification to the waveform of FIG. 10 can be used for the waveform of FIG. 11 . That is, when the scan electrode Y is maintained at Vs volts in the early part of the false trigger erasure period 200, a square-wave pulse varying from Ve volts to the reference voltage is supplied to the sustain electrode X. Next, while the sustain electrodes X are held at Ve volts in the latter part of the false trigger erasure period 200, a narrow pulse varying from Vs volts to the reference voltage is supplied to the scan electrodes Y.

In the exemplary embodiments of FIGS. 4 and 7-11, the discharge occurs during the false trigger elimination period, and the charges formed by the discharge are eliminated later. On the other hand, in the exemplary embodiments of FIGS. 12 and 13, a waveform in which discharging and erasing are simultaneously performed in the false trigger erasure period is used. In the exemplary embodiment of FIGS. 12 and 13 , as described in the previous exemplary embodiments, the false trigger elimination period supplements the reset period and may serve as a second reset period.

Referring to FIG. 12, in another embodiment, a narrow pulse is supplied only to the scan electrode Y during the false trigger elimination period 200. Referring to FIG. Specifically, a narrow pulse of Vs volts is supplied to the scan electrode Y while the sustain electrode X is held at the reference voltage during the false trigger elimination period. When a strong discharge occurs in the ramp-down period 130, and the state of charge becomes as shown in FIG. 6A, because the voltage difference Vs between the scan electrode Y and the sustain electrode X and the wall between the scan electrode Y and the sustain electrode X Voltage Vwxy1, the discharge occurs between the scan electrode Y and the sustain electrode X. Due to the narrow width of the pulse supplied to the scan electrode Y, charges formed by the discharge are not accumulated to the scan electrode Y and the sustain electrode X, but are eliminated.

Referring to FIG. 13 , in yet another exemplary embodiment, a ramp waveform is provided only to the scan electrode Y in the false trigger elimination period 200 . That is, while the sustain electrode X is held at the reference voltage, a ramp waveform gradually rising from the reference voltage to Vs volts is supplied to the scan electrode Y. Then, when charges are formed on the scan electrode Y and the sustain electrode X as in FIG. 6A, fine discharging occurs between the scan electrode Y and the sustain electrode X, and the charges are eliminated.

In the above exemplary embodiment, a false trigger elimination period 200 is added between the reset period 100 and the address period 300 . In some cases, due to the characteristics of the discharge cell, charges formed by the abnormal reset operation cannot be eliminated by a single false trigger elimination operation. In this case, the false trigger elimination period 200 between the reset period 100 and the address period 300 is repeated n times, where n is an integer greater than or equal to 2. The first to (n-1)th false trigger elimination operations can be regarded as priming operations, and the nth false trigger elimination operation can be regarded as a normal false trigger elimination operation. The process of repeatedly performing the false trigger canceling operation will now be described in detail with reference to FIGS. 14 to 16 .

14 to 16 illustrate PDP driving waveforms according to another exemplary embodiment. For ease of description, the false trigger elimination period is illustrated as repeating twice in the figure. However, the number of times of the false trigger elimination period is not limited to two actually, and the false trigger elimination period may be repeated more than twice.

Referring to FIG. 14, the false trigger elimination period 200 of FIG. 4 is repeated twice with a first false trigger elimination period 210 and a second false trigger elimination period 220, therefore, when the charge formed by the abnormal reset operation is in the first false trigger elimination period When not completely eliminated in 210 , the first false trigger elimination period 210 can be regarded as a preliminary period, and the above-mentioned charges are normally eliminated in the second false trigger elimination period 220 . Furthermore, the circular waveforms or narrow pulses of FIGS. 9 and 11 may be used in place of the ramp waveforms during at least one of the false trigger cancellation periods 210 and 220, respectively.

Referring to FIG. 15 , the false trigger elimination period 200 of FIG. 13 is repeated twice between the reset period 100 and the address period 300 with a first false trigger elimination period 210 and a second false trigger elimination period 220 . In this case, a circular waveform may be used in place of the ramp waveform during at least one of the first and second false trigger cancellation periods 210 and 220 .

Referring to FIG. 16, the false trigger elimination period 200 of FIG. 10 is repeated twice between the reset period 100 and the address period 300 with first and second false trigger elimination periods 210 and 220, respectively. In this case, the circular waveform or narrow pulse of FIG. 12 may be used in place of the ramp waveform during at least one of the first and second false trigger cancellation periods 210 and 220 .

As explained with reference to FIGS. 14 to 16, the false trigger elimination period of the same elimination method can be repeated twice or more, wherein the first false trigger elimination operation can be regarded as a primary operation, and the last false trigger elimination operation can be regarded as a primary operation. Normal false trigger elimination operation. However, different from this, it is also possible that the charge is not eliminated in the false trigger erasing period, but a strong discharge occurs once, thereby forming an abnormal charge. A method of eliminating this abnormal charge will now be described with reference to FIGS. 17 to 20 .

17 to 20 illustrate PDP driving waveforms according to still another exemplary embodiment.

Referring to Fig. 17, the false trigger elimination period includes a first false trigger elimination period 210, which is basically the same as the false trigger elimination period 200 of Fig. 4, and a second false trigger elimination period 220, which is basically the same as the false trigger elimination period of Fig. 13 Period 200 is the same. In this case, a strong discharge may occur in the first false trigger elimination period 210 due to the rising ramp waveform supplied to the sustain electrode X. Referring to FIG. If so, the charge will not be eliminated in the charge state of Figure 6(b), but will reach the charge state of Figure 6(a). In this case, the scan electrode Y is supplied with a rising ramp waveform in the second false trigger elimination period 220 to eliminate the charge in the charge state of FIG. 6( a ).

Likewise, a narrow pulse or circular waveform that performs substantially the same function as a ramp waveform may be used in place of the ramp waveform during at least one of the false trigger cancellation periods 210 and 220 . Therefore, a waveform having a cancel function is supplied to the sustain electrode X and the scan electrode Y to perform the false trigger cancel operation in FIG. 17 .

Referring to Fig. 18, the false trigger elimination period includes a first false trigger elimination period 210, which is basically the same as the false trigger elimination period 200 of Fig. 10, and a second false trigger elimination period 220, which is basically the same as the false trigger elimination period of Fig. 13 Period 200 is the same. When a strong discharge occurs due to the falling ramp waveform supplied to the scan electrode Y in the first false trigger eliminating period 210 , the charge may be eliminated by the rising ramp waveform supplied to the scan electrode Y in the false trigger eliminating period 220 . Likewise, a narrow pulse or circular waveform that performs substantially the same function as a ramp waveform may be used in place of the ramp waveform during at least one of the false trigger cancellation periods 210 and 220 . Therefore, a waveform having a cancel function is supplied to the scan electrode Y to perform the false trigger cancel operation in FIG. 18 .

19, the false trigger elimination period includes a first false trigger elimination period 210, which is similar to the false trigger elimination period 200 of FIG. 13, and a second false trigger elimination period 220, which is similar to the false trigger elimination period 200 of FIG. In the false trigger elimination period 210, the voltage supplied to the sustain electrode X does not rise to Ve unlike in the latter part of the false trigger elimination period 200 of FIG. 13 . In addition, the square wave pulse provided to invert the polarity of the charges formed on the scan electrode Y and the sustain electrode X in the false trigger elimination period 200 of FIG. 4 does not appear in the second false trigger elimination period 220 . Therefore, when a strong discharge occurs in the first false trigger elimination period 210 due to providing the scan electrode Y with a rising ramp waveform in order to reach the charge state of FIG. The rising ramp pulse supplied to the sustain electrode X removes the charges. Likewise, a narrow pulse or circular waveform that performs substantially the same function as a ramp waveform may be used in place of the ramp waveform during at least one of the false trigger cancellation periods 210 and 220 . Therefore, a waveform having a cancel function is supplied to the scan electrode Y and the sustain electrode X to perform the false trigger cancel operation in FIG. 19 .

Referring to FIG. 20 , the false trigger elimination period includes a first false trigger elimination period 210 similar to the false trigger elimination period 200 of FIG. 13 , and a second false trigger elimination period 220 similar to the false trigger elimination period 200 of FIG. 10 . The square-wave pulse provided to invert the polarity of the charges formed on the scan electrode Y and the sustain electrode X in the false trigger elimination period 200 of FIG. 13 is not in the first false trigger elimination period 210 . In addition, the voltage rise from Vs to Ve supplied to the sustain electrode X in the preceding period of the false trigger elimination period 200 of FIG. 10 does not occur in the second false trigger elimination period 220 . Therefore, when a strong discharge occurs in the first false trigger elimination period 210 due to providing the scan electrode Y with a rising ramp waveform in order to reach the charge state of FIG. The falling ramp pulse supplied to the scan electrode Y eliminates the charges. Likewise, a narrow pulse or circular waveform that performs substantially the same function as a ramp waveform may be used in place of the ramp waveform during at least one of the false trigger cancellation periods 210 and 220 . Therefore, a waveform having a cancel function is supplied to the scan electrode Y to perform the false trigger cancel operation in FIG. 20 .

In the above exemplary embodiments, the method of repeating the false trigger eliminating operation for multiple times has been described with reference to FIGS. 14 to 20 . For ease of illustration, each of the waveforms of FIGS. 14 to 20 is exemplified as first and second false trigger cancellation periods/operations. However, in practice the false trigger elimination period/operation may be performed more than twice. The additional false trigger cancellation operations of FIGS. 14 to 20 can be considered as additional settings or additional resets.

According to an exemplary embodiment of the present invention, when a strong discharge occurs due to an unstable reset operation in a reset period and a large amount of charges are formed on the scan electrodes and the sustain electrodes, the charges may be eliminated. Therefore, sustain discharge can be prevented from being generated in unselected discharge cells.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the present invention is not limited to these disclosed exemplary embodiments but, on the contrary, is included within the spirit and scope of the appended claims various modifications and/or equivalent configurations.

Claims (62)

1. method that drives plasma display panel, described plasma display panel comprises a plurality of first electrode and second electrodes that are formed on abreast on first substrate, intersect with a plurality of and first and second electrodes and be formed on third electrode on second substrate, wherein contiguous described first, second and third electrode have been determined each of a plurality of discharge cells, and this method comprises:

Reset first and interim this a plurality of discharge cell to be provided with;

At the second interim described a plurality of discharge cell that further is provided with of resetting;

In address period, from these a plurality of discharge cells, select at least one discharge cell; With

Interimly make described at least one discharge cell keep discharge keeping,

Wherein, discharge second is reset and interimly to be caused between this first and second electrode at this.

2. method according to claim 1, wherein said further setting are included under the predetermined condition provides discharge to eliminate pulse to described a plurality of discharge cells, and described discharge is eliminated pulse and had discharge and eliminate function.

3. method according to claim 2, wherein said predetermined condition are included in this first situation of the unusual electric charge of interim formation of resetting, and are discharged in response to this discharge elimination pulse and eliminate at this first described unusual electric charge of resetting interim formation.

4. method according to claim 3, wherein said abnormal electrical lotus is included in interim first and second electric charges that are respectively formed on described first and second electrodes of this first replacement, and is enough to keeping the interim non-selected discharge cell in the address period that maintains by the voltage that first and second electric charges cause.

5. method according to claim 4, the wherein said second replacement phase comprises the first phase and the second phase, and described further setting comprises:

In the described first phase, provide first voltage to described first electrode; With

In the described second phase, provide second voltage to described second electrode.

6. method according to claim 5, wherein said first voltage adds the voltage that is caused by first and second electric charges, is enough to produce between this first and second electrode this discharge.

7. method according to claim 6, wherein said first voltage have with this keeps the interim essentially identical voltage level of the voltage that is used to discharge that offers this first electrode.

8. method according to claim 6, wherein in response to the discharge in the described first phase, electric charge is accumulated on first and second electrodes, and described second voltage is used for eliminating the described electric charge that forms in the described second phase in the described first phase.

9. method according to claim 8, wherein said second voltage gradually becomes the 4th voltage from tertiary voltage.

10. method according to claim 8, wherein said second voltage adds the voltage that is caused by the electric charge that forms in this first phase, be enough to produce between this first and second electrode second discharge, and

The electric charge that is accumulated in this first and second electrode in response to this second discharge in this second phase is less than the scheduled volume of an electric charge.

11. method according to claim 10, the scope of wherein said scheduled volume prevent that non-selected discharge cell from keeping interim being kept.

12. method according to claim 4 wherein second is reset interimly when first voltage being offered described first electrode at this, and second voltage is offered described second electrode.

13. method according to claim 12 wherein offers described first electrode to described first voltage in a scheduled period,

Voltage difference between described first and second voltages adds the voltage that is caused by described first and second electric charges, is enough to produce between described first and second electrodes this discharge, and

The electric charge that is accumulated in this scheduled period on this first and second electrode in response to this discharge is less than an electric charge scheduled volume.

14. method according to claim 13, the scope of wherein said scheduled volume prevent to maintain and keep interim non-selected discharge cell.

15. method according to claim 13, wherein said first voltage have and are keeping the interim essentially identical voltage level of voltage that this first electrode is used to discharge that offers.

16. method according to claim 13, wherein said first voltage gradually becomes the 4th voltage from tertiary voltage.

17. method according to claim 1 further is included at least one additional interim setting that at least once more these a plurality of discharge cells is added of replacement.

18. method according to claim 17, wherein each described second replacement phase and this at least one additional replacement phase comprise a first phase and a second phase, and in described further setting and described additional setting the each comprises:

In the described first phase, provide first voltage to described first electrode; With

In the described second phase, provide second voltage to described second electrode.

19. method according to claim 18, wherein said first voltage have and are keeping the interim essentially identical voltage level of voltage that described first electrode is used to discharge that offers.

20. method according to claim 18, wherein said first voltage gradually becomes the 4th voltage from tertiary voltage.

21. method according to claim 20, wherein said the 4th voltage have and are keeping the interim essentially identical voltage level of voltage that this first electrode is used to discharge that offers.

22. method according to claim 18, wherein said second voltage gradually becomes the 6th voltage from the 5th voltage.

23. method according to claim 22, wherein said the 6th voltage have than keeping the interim higher voltage level of voltage that described second electrode is used to discharge that offers.

24. method according to claim 17, wherein each this second replacement phase and this at least one additional replacement phase comprise a first phase and a second phase, and in described further setting and described additional setting the each comprises at least one step in the middle of following: provide first voltage to first electrode in the first phase; With in the second phase, provide second voltage to second electrode.

25. method according to claim 24 wherein gradually becomes the 4th voltage and at least one additional interim second voltage of replacement gradually becomes the 6th voltage from the 5th voltage at this at second interim first voltage of resetting from tertiary voltage.

26. method according to claim 25, wherein said the 6th voltage have than keeping the interim higher voltage level of voltage that described second electrode is used to discharge that offers.

27. method according to claim 25, wherein the 4th voltage has and is keeping the interim essentially identical voltage level of voltage that this first electrode is used to discharge that offers.

28. method according to claim 24 wherein gradually becomes the 4th voltage and at least one additional interim first voltage of replacement gradually becomes tertiary voltage from the 4th voltage at this at this second interim this first voltage of resetting from tertiary voltage.

29. method according to claim 28, wherein said tertiary voltage have and are keeping the interim essentially identical voltage level of voltage that this first electrode is used to discharge that offers.

30. method according to claim 28, wherein said the 4th voltage have and are keeping the interim essentially identical voltage level of voltage that this first electrode is used to discharge that offers.

31. method that drives plasma display panel, described plasma display panel comprises a plurality of first electrode and second electrodes that are formed on abreast on first substrate, intersect with a plurality of and first and second electrodes and be formed on third electrode on second substrate, wherein contiguous described first, second and third electrode have been determined each of a plurality of discharge cells, and this method comprises:

When resetting interimly when a predetermined condition is provided, this a plurality of discharge cell is provided with, described setting comprises and produces discharge and eliminate, comprising:

Under the predetermined condition of the phase of replacement, provide a discharge pulse, be used between described first and second electrodes, producing discharge to described a plurality of discharge cells; With

Provide one to eliminate pulse to described a plurality of discharge cells, be used to eliminate the electric charge that on described first and second electrodes, forms in response to discharge.

32. method according to claim 31, wherein said predetermined condition are included in the interim situation that has formed unusual electric charge of this replacement.

33. method according to claim 32, wherein said abnormal electrical lotus be included in this replacement interim be respectively formed on described first and second electrodes first and second electric charges and

The voltage that is caused by this first and second electric charge is enough to make in address period non-selected discharge cell keeping the interim discharge of keeping.

34. method according to claim 33, wherein the described setting to described a plurality of discharge cells comprises: when this second electrode remains on second voltage, provide a discharge pulse with first voltage to this first electrode, the voltage difference between this first and second voltage wherein, add the voltage that causes by this first and second electric charge, be enough between described first and second electrodes, produce discharge.

35. method according to claim 34, the wherein said elimination pulse that provides be included in described first electrode when remaining on tertiary voltage to this second electrode provide from the 4th voltage rise to gradually the 5th voltage the elimination pulse and

The 5th and tertiary voltage between voltage difference, add that the discharge that produces by the discharge pulse that provides is formed on the voltage that the electric charge on this first and second electrode causes, be enough between this first and second electrode, produce another time discharge.

36. method according to claim 34, the described elimination pulse that provides be included in described first electrode when remaining on tertiary voltage to described second electrode provide from the 4th voltage drop to gradually the 5th voltage the elimination pulse and

Voltage difference between the 3rd and the 5th voltage adds that the discharge that produces by the discharge pulse that provides is formed on the voltage that the electric charge on this first and second electrode causes, is enough to produce between this first and second electrode another time discharge.

37. method according to claim 34, the described elimination pulse that provides be included in the elimination pulse that is used for scheduled period that described first electrode provides to described second electrode when remaining on tertiary voltage with the 4th voltage and

The 4th and tertiary voltage between voltage difference, add that the discharge that produces by the discharge pulse that provides is formed on the voltage that the electric charge on this first and second electrode causes, be enough between this first and second electrode, produce another time discharge and

The electric charge that is accumulated in this first and second electrode in scheduled period that comes from the electric charge that is formed by this first and second interelectrode discharge is less than an electric charge scheduled volume.

38. according to the described method of claim 37, the scope of wherein said scheduled volume prevents to discharge between this first and second electrode for when keeping interimly when identical with the voltage level that offers this first and second electrode respectively basically voltage level is offered this first and second electrode.

39. method that drives plasma display panel, described plasma display panel comprises a plurality of first electrode and second electrodes that are formed on abreast on first substrate, intersect with a plurality of and first and second electrodes and be formed on third electrode on second substrate, wherein contiguous described first, second and third electrode have been determined each of a plurality of discharge cells, and this method comprises:

When reset interim when a predetermined condition is provided, described a plurality of discharge cell is provided with, described setting comprises producing discharges and elimination, comprising: under predetermined condition, provide one to eliminate pulse, be used between this first and second electrode, producing discharge and eliminate electric charge to described a plurality of discharge cells.

40. according to the described method of claim 39, wherein this predetermined condition is included in the interim situation that has formed unusual electric charge of resetting.

41. according to the described method of claim 40, wherein this abnormal electrical pocket draw together first and second electric charges that are respectively formed on this first and second electrode and

The voltage that is caused by first and second electric charges is enough to make in address period non-selected discharge cell keeping the interim discharge of keeping.

42. according to the described method of claim 41, the wherein said elimination pulse that provides is included in the elimination pulse with second voltage that is used for scheduled period that this second electrode provides to this first electrode when remaining on first voltage,

Voltage difference between this second and first voltage adds the voltage that is caused by this first and second electric charge, be enough between this first and second electrode to produce discharge and

The electric charge that is accumulated in this first and second electrode in this scheduled period that comes from the electric charge that is formed by this first and second interelectrode discharge is less than an electric charge scheduled volume.

43. according to the described method of claim 42, wherein when keeping interimly when identical with the voltage level that offers this first and second electrode respectively basically voltage level is offered first and second electrodes, the scope of described scheduled volume prevents to discharge between this first and second electrode.

44., wherein when this second electrode remains on first voltage, provide an elimination pulse that tapers to tertiary voltage from second voltage to this first electrode according to the described method of claim 41.

45. according to the described method of claim 44, wherein the voltage difference between the 3rd and first voltage adds the voltage that is caused by this first and second electric charge, is enough to produce between this first and second electrode discharge.

46. a plasma display panel comprises:

First substrate;

Be formed on a plurality of first and second electrodes on described first substrate respectively substantially parallel;

Also accompany second substrate of a predetermined space betwixt towards described first substrate;

Intersect with described first and second electrodes and be formed on a plurality of third electrodes on described second substrate; With

Be used for providing the driving circuit of drive signal to the discharge cell of determining by contiguous described first, second and third electrode,

Wherein this driving circuit provides first voltage to described first electrode between replacement and address period, provide second voltage to described second electrode, and will eliminate at the unusual electric charge in the interim electric charge that forms of resetting by described first and second voltages, and wherein discharge and in the elimination process of this unusual electric charge, between this first and second electrode, cause.

47. according to the described plasma display panel of claim 46, wherein this abnormal electrical pocket is drawn together first and second electric charges that are respectively formed on described first and second electrodes, and wherein said first and second electric charges are enough to make in address period non-selected discharge cell keeping interim generation discharge.

48. according to the described plasma display panel of claim 47, wherein said driving circuit in the first phase to described first electrode first voltage is provided and in the second phase to described second electrode provide second voltage and

When resetting this first and second electric charge of interim formation, the electric charge elimination that in the first phase, this discharge takes place between described first and second electrodes and in the second phase, will form by the discharge in the first phase in response to second voltage in response to first voltage.

49. according to the described plasma display panel of claim 48, wherein, in this first phase, when described second electrode remains on tertiary voltage this driving circuit to described first electrode provide first voltage and

This first and tertiary voltage between voltage difference and the voltage that causes by this first and second electric charge together, be enough between described first and second electrodes, produce this discharge.

50. according to the described plasma display panel of claim 49, wherein, in this second phase, driving circuit provides second voltage to described second electrode when described first electrode remains on the 4th voltage,

This second voltage gradually from the 5th change in voltage to the six voltages and

Voltage difference between the 6th and the 4th voltage adds the voltage that the electric charge that forms by discharge between described first and second electrodes causes, is enough to produce between described first and second electrodes second discharge.

51. according to the described plasma display panel of claim 49, wherein, in this second phase, driving circuit provides second voltage to described second electrode when described first electrode remains on the 4th voltage,

Voltage difference between this second and the 4th voltage adds the voltage that the electric charge that forms by discharge between described first and second electrodes causes, be enough between described first and second electrodes, produce second discharge and

The electric charge that is accumulated in described first and second electrodes in this second phase by described second electric charge that forms of discharge is less than an electric charge scheduled volume.

52. according to the described plasma display panel of claim 51, wherein when keeping interimly when identical with the voltage level that offers described first and second electrodes respectively basically voltage level is offered described first and second electrodes, the scope of described scheduled volume prevents to discharge between this first and second electrode.

53. according to the described plasma display panel of claim 47, wherein said driving circuit provides second voltage to described second electrode, provides first voltage to described first electrode, and in response to this first and second voltage this first and second electric charge is eliminated.

54. according to the described plasma display panel of claim 53, wherein said driving circuit is for providing first voltage scheduled period,

Voltage difference between this first and second voltage adds the voltage that is caused by this first and second electric charge, be enough between described first and second electrodes to produce this discharge and

Be less than an electric charge scheduled volume by the electric charge on described first and second electrodes of in scheduled period, being accumulated in of the electric charge that forms in this discharge between described first and second electrodes.

55. plasma display panel according to claim 54, wherein when keeping interimly when identical with the voltage level that offers this first and second electrode respectively basically voltage level is offered described first and second electrodes, the scope of described scheduled volume prevents to discharge between described first and second electrodes.

56. according to the described plasma display panel of claim 53, wherein second voltage gradually from tertiary voltage be changed to the 4th voltage and

Voltage difference between the 4th and first voltage adds the voltage that is caused by this first and second electric charge, is enough to produce between described first and second electrodes this discharge.

57. according to the described plasma display panel of claim 46, wherein driving circuit provides first voltage and provides second voltage to described second electrode to described first electrode at least once more between replacement and address period.

58. according to the described plasma display panel of claim 57, wherein at least one changes to the 4th voltage from tertiary voltage gradually in this first and second voltage.

59. according to the described plasma display panel of claim 57, wherein applying in the process this second voltage in the first time of this first and second voltage changes to the 4th voltage and applies in the process this first voltage gradually from the 5th change in voltage to the six voltages in the second time of this first and second voltage from tertiary voltage gradually.

60. according to the described plasma display panel of claim 57, wherein the first time of this first and second voltage apply in the process this first voltage gradually from tertiary voltage change to the 4th voltage and the second time of this first and second voltage apply in the process this first voltage gradually from the 4th change in voltage to tertiary voltage.

61. according to the described plasma display panel of claim 46, wherein this first voltage changes to the 4th voltage from tertiary voltage gradually in the first phase, with this second voltage in the second phase gradually from the 5th change in voltage to the six voltages, wherein first and second phases reset and address period between.

62. according to the described plasma display panel of claim 46, wherein this first voltage changes to the 4th voltage from tertiary voltage gradually in this first phase, with first voltage in the second phase gradually from the 4th change in voltage to tertiary voltage, wherein this first and second phase reset and address period between.

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