CN1262113C - Interference clearing circuit for TV receiver - Google Patents
Interference clearing circuit for TV receiver Download PDFInfo
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- CN1262113C CN1262113C CN 03111264 CN03111264A CN1262113C CN 1262113 C CN1262113 C CN 1262113C CN 03111264 CN03111264 CN 03111264 CN 03111264 A CN03111264 A CN 03111264A CN 1262113 C CN1262113 C CN 1262113C
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- 230000011664 signaling Effects 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 abstract 9
- 238000000034 method Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000004069 differentiation Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The present invention relates to an interference clearing circuit for a TV receiver, which comprises a clock counter, a reset controller, a horizontal synchronous signal generator, a clock signal multiplier, a synchronous signal counter and an AND gate, wherein the clock counter can use a high-frequency clock signal to count a vertical synchronization region, the counting time span of the clock counter can contain the interference, and a corresponding low region signal is output; the reset controller generates an effective reset signal at a falling edge in interference, and outputs the effective reset signal to the synchronous signal counter; the horizontal synchronous signal generator can convert a horizontal synchronous signal into a signal with 50 of a duty ratio; the clock signal multiplier can multiply output signals of the horizontal synchronous generator; the synchronous signal counter resets according to the reset signal output by the reset controller, then, counts the specified number of output signals of the clock signal multiplier, and outputs signals with low regions; the AND gate makes AND logic for the output signals of the clock counter and the synchronous signal counter, and outputs vertical synchronous region signals of which the interference states are cleared.
Description
Technical field
This is about in television receiver, removes the technology disturbing (glich) in the vertical synchronization interval of sneaking into.Furtherly, it is about removing a special invention of television receiver interfered circuit.Sort circuit will utilize vertical synchronizing signal, clock signal and horizontal-drive signal, go to remove to extract from multiple format pattern signal, be included in the interference in the vertical synchronizing signal.
Background technology
Usually, in the processing of TV signal, vertical synchronizing signal and horizontal-drive signal are used for gated sweep electron beam track in display frame.Soon periodically generate vertical synchronizing signal, so that electron beam down scans from last beginning; In addition, periodically generate horizontal-drive signal again, so that electron beam begins to scan from a left side to the right.
Below, with reference to Fig. 1, be example with 480 picture intelligences of going interlace modes, the process of utilizing conventional art to extract horizontal-drive signal and vertical synchronizing signal is described.
Shown in Fig. 1 (a), picture intelligence, especially luminance signal (Y) include horizontal-drive signal (H
Sync) and vertical synchronizing signal (V
Sync); This luminance signal (Y) is carried out amplitude limit (slicing) will obtain composite synchronizing signal shown in Fig. 1 (b).
If composite synchronizing signal is carried out the RC integration, will obtain the waveform shown in Fig. 1 (c).The reason of this integrated signal unevenness of picture (smooth) is that (VBi) inserted H in the vertical synchronization interval
SyncThe five equilibrium pulse in/2 cycles; Although the time is very short, this is owing to allow due to capacitor discharges.
The charging interval of capacitor will be longer than discharge time; Thereby as a whole,, will make charging voltage be reduced to threshold voltage V because capacitor has electric charge
Th1Or V
Th2Below.But, when charging voltage is reduced to threshold voltage V
Th1Or V
Th2In the time of following, the signal of vertical synchronization interval (VBi) will become as " low " of Fig. 1 (d) (or " height "); Therefore, from broad sense, before finish in the vertical synchronization interval of input luminance signal (Y) (VBi), just will generate the vertical synchronization interval.
But problem is the vertical synchronization interval (VBi) that generates and exists the factor that (glich) disturbed in a lot of generations.For example, the threshold voltage with vertical synchronization interval (VBi) is made as V
Th2, work as charging voltage simultaneously and be reduced to threshold voltage V
Th2Below, can make vertical synchronization interval (VBi) become " low " so; And if then rise to threshold voltage (V again
Th2) more than, and then be reduced to threshold voltage (V
Th2) below, will produce the interference shown in Fig. 1 (e) so.
For the traditional tv receiver, because it does not possess following function, that is: being used for removing one extracts from multiple format pattern signal, be included in the function of the interference in vertical synchronization interval, therefore be difficult to the form of input image signal that judges rightly, and be difficult to show without distortion original image.
Summary of the invention
The object of the present invention is to provide a kind of circuit that television receiver disturbs of removing, that is to say, it can utilize vertical synchronizing signal, clock signal and horizontal-drive signal, removes to extract from the picture intelligence of multiple form, is included in the interference in the vertical synchronizing signal.
The object of the present invention is achieved like this: it is characterised in that it is provided with clock counter, it can utilize high frequency clock signal that the vertical synchronization interval is counted, but the time span of counting comprises the place ahead of interference, and exports corresponding low wayside signaling; Be provided with reset controller, it generates effective reset signal at the trailing edge in vertical synchronization interval and the trailing edge of interference, and this signal is outputed to the synchronizing signal counter; Be provided with horizontal sync generator, it can be 0.50 signal level conversion synchronizing signal with duty ratio; Be provided with the clock signal multiplier, its can double output signal of horizontal sync generator; Be provided with the synchronizing signal counter, after it resets according to the reset signal by reset controller output, to the output signal of clock signal multiplier, the number of counting regulation, output is provided with low interval signal then; Be provided with AND gate, it will carry out and logic the output signal of clock counter and synchronizing signal counter, and the vertical synchronization wayside signaling that disturbs form is removed in output.
Effect of the present invention is, it can utilize vertical synchronizing signal, clock signal and horizontal-drive signal, removes by extracting a kind of interference that is included in the vertical synchronizing signal in the multiple format pattern signal, thereby can correctly judge the picture intelligence form of input, the steady operation of safeguards system.
Description of drawings
(a)-(f) of Fig. 1 utilizes conventional art to extract the oscillogram of synchronizing signal process.
Fig. 2 is the block diagram that television receiver is removed interfered circuit.
(a)-(k) of Fig. 3 illustrates the oscillogram of removing interfering process.
Fig. 4 is the oscillogram in the vertical synchronization interval of display simulation experimental result.
Symbol description about the main position of drawing
21: clock counter 22: reset controller
23: horizontal sync generator 24: the clock signal multiplier
25: synchronizing signal counter 26: AND gate
Embodiment
Fig. 2 is the circuit block diagram of the removing low-frequency disturbance of television receiver.As shown in the figure, it is made up of following components.That is: be provided with clock counter (21), it can utilize high frequency clock signal that the vertical synchronization interval is counted, but the time span of counting comprises aforesaid interference, and the corresponding low wayside signaling of output; Be provided with reset controller (22), it is at trailing edge and disturb the effective reset signal of generation, and this signal is outputed to synchronizing signal counter (25); Be provided with horizontal sync generator (23), it can convert horizontal-drive signal to duty ratio is 0.50 signal; Be provided with clock signal multiplier (24), its can double output signal of horizontal sync generator (23); Be provided with synchronizing signal counter (25), after resetting according to the reset signal by reset controller (22) output, it is to the output signal of clock signal multiplier (24), and the number of counting regulation is exported then and is provided with low interval signal; Be provided with AND gate (26), it will carry out and logic the output signal of clock counter (21) and synchronizing signal counter (25), and the vertical synchronization wayside signaling that disturbs form is removed in output.To effect of the present invention, with reference to the accompanying drawings 3 and Fig. 4 be described in detail as follows.
At first, Fig. 3 (a) is the accompanying drawing that contains vertical synchronization interval (VBi) signal of interference.As shown in the figure, aforesaid interference and interference described later always might take place.Therefore, for traditional 480i (interlace-interlacing scan) signal, once proposed much to be used for handling the special-purpose integrated device scheme of vertical synchronizing signal or horizontal-drive signal.But,, also do not propose to be used for handling the special-purpose integrated device scheme of vertical synchronizing signal or horizontal-drive signal for the 720p (prograssive-lines by line scan) or the 1080i signal of hd-tv.So, when the above-mentioned signal of input,, exist much clear inadequately part in the vertical synchronizing signal pattern that the integration composite synchronizing signal obtains.
Rough vertical synchronizing signal that becomes can produce following problem so if use removing to disturb.
Error can take place when judging the input image signal form.If check the horizontal-drive signal number in a vertical synchronization interval (VBi), just can learn it is the form of which image.For example, this quantity is 252.3, is the 480i signal; 720 is the 720p signal; 540 is the 1080i signal.But, if existing, vertical synchronization interval (VBi) disturb, and so, it is very short that one-period will become, and for example count value is 0 or 1.Thus, just can't judge it is which type of signal aspect.At this moment, will produce in the devices such as to show microprocessor at video, receive the problem of suitably processing by the picture intelligence of A/D converter (not identifying among the figure) output.
For this reason, the present invention has utilized vertical synchronizing signal, clock signal and horizontal-drive signal to remove the interference that is included in vertical synchronization interval (VBi), and this processing procedure is as follows.
At first, if the signal in input vertical synchronization interval (VBi), so will be by its trailing edge, clock counter (21) will reset.This clock counter (21) with utilizing the clock signal (CLK) of the 27MHz shown in (i) of Fig. 3 for example, generates as Fig. 3 (j) shown in, has removed a kind of signal (V of interference
Sync-Front).
Like this, clock counter (21) is with high-frequency drive, therefore if go to count whole vertical synchronization interval (VBi), will use very many logics so.So, the time span of counting is designed to the length that can fully comprise aforementioned interference.
The next one is to remove the process that aftermentioned is disturbed.Horizontal-drive signal (the H of Fig. 3 (b)
Sync) to be converted to duty ratio shown in Fig. 3 (c) by horizontal sync generator (23) be 50 signal, again by clock signal multiplier (24) with H
Sync/ 2 carry out frequency multiplication (shown in Fig. 3 (d)), are provided to synchronizing signal counter (25) then.Shown in Fig. 3 (g), (h), synchronizing signal counter (25) will be till beginning to count to certain number (as 9) from frequency doubling clock signal " 1 " during, generate one and have " low " wayside signaling (V
Front-Back).
Horizontal-drive signal (H is being provided
Sync) time, if in statu quo provide clock signal to synchronizing signal counter (25), and when the input picture intelligence be interleaved picture intelligence, so at signal (V
FrontOn-the point that Back) finishes, can not be by increase and decrease H
Sync/ 2 carry out replacing between field and the field, strange so as to distinguishing/idol (top/Bottom Field).For this reason, convert thereof into H at interval earlier
SyncGoing after/2 the signal provides again.
By above-mentioned method, vertical synchronization interval (VBi) rear side (rising edge-forward position) and horizontal-drive signal (H that disturbs could removed
Sync) keep correct relation, and can keep the differentiation of strange/idol field consistently.
Reset controller (22) will generate effective reset signal (RE2) at the trailing edge of vertical synchronization interval (VBi), and output to synchronizing signal counter (25), meanwhile begin to carry out the counting work of synchronizing signal counter (25).
But, shown in Fig. 3 (a), when the place ahead of vertical synchronization interval (VBi) takes place to disturb, in reset controller (22), shown in Fig. 3 (e), output is had continuously the reset signal (RE2) of 2 trailing edges.So synchronizing signal counter (25) will will reset continuously in first clock signal and second clock signal interval, just remove to begin counting then, and count down to till " 9 " always.(with reference to (g) of Fig. 3)
Under above-mentioned condition, the cause that produces the reset signal (RE2) shown in Fig. 3 (e) is, if so do not do, and the forward position of the trailing edge of vertical synchronization interval (VBi) and the frequency multiplication synchronizing signal shown in Fig. 3 (e) so, on the time of rising, with difference; And will can make the count value of synchronizing signal counter (25), or shift to an earlier date H according to which side slim lead
Sync/ 2 arrive " 9 ", or arrive " 9 " through the normal time, thus can't guarantee the terminal point in vertical synchronization interval (VBi) certain due to.
But, if by disturbing in the ending of vertical synchronization interval (VBi), the reset signal (RE2) of reset controller (22) begins to become effective, the count value of synchronizing signal counter (25) can't arrive " 9 " so, the terminal point of vertical synchronization interval (VBi) will can not occur thus.
In addition, for the valid interval of reset signal (RE2) being limited to preceding about half the length in vertical synchronization interval (VBi), synchronizing signal counter (25) will be exported control signal (CTL), shown in Fig. 3 (f).
Finally, by clock counter (21) output, the removing shown in Fig. 3 (j) interference signals (V
Sync-Front) with by synchronizing signal counter (25) output, the signal (V shown in Fig. 3 (h)
Front-Back), in AND gate (26), carry out " with " logic, will export one then shown in Fig. 3 (k), removed vertical synchronization interval (VBi) signal that disturbs.
Fig. 4 is the circuit that disturbs about removing, and is applicable to the analog result that the television receiver removing is disturbed.
Claims (5)
1, television receiver is removed interfered circuit, it is characterized in that it is provided with clock counter, and it can utilize high frequency clock signal that the vertical synchronization interval is counted, but the time span of counting comprises the place ahead of interference, and exports corresponding low wayside signaling; Be provided with reset controller, it generates effective reset signal at the trailing edge in vertical synchronization interval and the trailing edge of interference, and this signal is outputed to the synchronizing signal counter; Be provided with horizontal sync generator, it can be 0.50 signal level conversion synchronizing signal with duty ratio; Be provided with the clock signal multiplier, its can double output signal of horizontal sync generator; Be provided with the synchronizing signal counter, after it resets according to the reset signal by reset controller output, to the output signal of clock signal multiplier, the number of counting regulation, output is provided with low interval signal then; Be provided with AND gate, it will carry out and logic the output signal of clock counter and synchronizing signal counter, and the vertical synchronization wayside signaling that disturbs form is removed in output.
2,, it is characterized in that clock counter uses the 27MHz clock signal according to the said circuit of claim 1.
3,, it is characterized in that reset controller will be exported the reset signal that 2 trailing edges are arranged continuously when the place ahead in the vertical synchronization interval takes place to disturb according to the said circuit of claim 1.
4, according to the said circuit of claim 1, it is characterized in that counting to till 9 until the clock signal of frequency multiplication, the synchronizing signal counter can be exported " low " signal always.
5,, it is characterized in that the synchronizing signal counter is limited to the valid interval of the reset signal of exporting from reset controller about preceding half length in vertical synchronization interval according to the said circuit of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03111264 CN1262113C (en) | 2003-03-25 | 2003-03-25 | Interference clearing circuit for TV receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03111264 CN1262113C (en) | 2003-03-25 | 2003-03-25 | Interference clearing circuit for TV receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1533162A CN1533162A (en) | 2004-09-29 |
| CN1262113C true CN1262113C (en) | 2006-06-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03111264 Expired - Fee Related CN1262113C (en) | 2003-03-25 | 2003-03-25 | Interference clearing circuit for TV receiver |
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| CN (1) | CN1262113C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101742078B (en) * | 2008-01-31 | 2011-11-23 | 华为技术有限公司 | Synchronous clock extraction device and method therefor |
| JP5251926B2 (en) * | 2010-06-16 | 2013-07-31 | セイコーエプソン株式会社 | Imaging apparatus and timing control circuit |
| CN113535615B (en) * | 2020-04-14 | 2024-08-13 | 京东方科技集团股份有限公司 | Method, device, equipment and computer readable storage medium for resetting synchronous signal |
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