CN117634370A - Function verification method and platform for Verilog code - Google Patents

Abstract

The invention provides a functional verification method and a platform of Verilog codes, which relate to the technical field of digital integrated circuit verification and comprise the following steps: generating a verification incentive based on the verification purpose and the requirement; compiling a simulation script by utilizing Matlab, and realizing a Verilog code design function so as to obtain an expected simulation result and taking the expected simulation result as a reference; compiling an EDA simulation script by using Python, generating a simulation file corresponding to a Verilog code, and modifying and operating the simulation file based on requirements; writing a Testbench in an EDA simulation tool, configuring a Verilog code module interface and a control signal, and finishing verification excitation input and behavior simulation result output; respectively running Matlab and EDA simulation scripts to obtain expected simulation results and behavior simulation results; and comparing the expected simulation result with the behavior simulation result to verify the functional correctness of the Verilog code. The method can realize that verification processes such as excitation generation, simulation execution, result verification and the like are automatically executed on the premise of not opening the GUI of the EDA simulation tool, avoid repeated interaction and operation between developers and the GUI, and greatly improve the verification efficiency.

Description

A functional verification method and platform for Verilog code

Technical field

The invention relates to the technical field of digital integrated circuit verification, and in particular to a Verilog code function verification method and platform.

Background technique

Currently, the main idea for functional verification of Verilog code is to write Testbench using Electronic Design Automation (EDA) simulation tools to generate verification incentives, and compare the output of the Verilog code to be verified with the expected results, so as to achieve Functional verification purposes. The aforementioned method not only requires developers to interact and operate in the Graphical User Interface (GUI) of the EDA simulation tool for each verification, but also relies on manually writing Testbench to generate verification incentives and manually comparing the output of the Verilog code to be verified with expectations. result. This leads to problems such as low verification automation level, poor visibility, low verification use case coverage, and poor portability.

Contents of the invention

In view of this, the present invention provides a Verilog code function verification method and platform to solve the problems existing in the traditional Verilog code verification method such as low verification use case coverage, poor portability, low verification automation level, and poor visibility.

In order to achieve the above object, the first aspect of the present invention discloses a functional verification method of Verilog code, which features include the following steps:

Step 1: Verify incentive generation. Verification incentives are external inputs to the simulation, and corresponding verification incentives need to be generated based on the verification purpose and scenario requirements.

Step 2: Matlab simulation script writing. Use the software Matlab to write simulation scripts to simulate the expected functions of the Verilog code, and obtain the expected simulation results as a benchmark.

Step 3: EDA simulation script writing. Use the Python language to write EDA simulation scripts, call the Tool Command Language (TCL) to run the EDA simulation tool in the background to generate simulation files, and complete the modification and operation of the simulation files through the Python file function library.

Step 4: Testbench writing. Write Testbench in the EDA simulation tool and place it on top of the project to be verified. Testbench is used to configure the interface and control signals of the Verilog code module to be verified, and complete the input of verification stimuli and the output of behavioral simulation results.

Step 5: Run the Matlab simulation script and EDA simulation script. Run the Matlab simulation script and the EDA simulation script respectively, and obtain the expected simulation results and behavioral simulation results.

Step 6: Verification of functional correctness. Compare the expected simulation results with the behavioral simulation results to verify the functional correctness of the Verilog code.

Further, step 1 is to manually set control items such as the name, quantity, length, randomness, and limit of the verification incentives according to the purpose and needs of the simulation to generate incentives that meet the purpose and needs of the simulation.

Furthermore, in step 2, the Matlab simulation script contains three parts, namely reading of verification incentives, implementation of the expected functions of the Verilog code to be verified, and file writing of expected simulation results.

Further, the expected function of the Verilog code is the developer's definition of the role and output of the Verilog code module in order to meet development needs.

Further, in step 3, the EDA simulation script includes three parts, which are the generation, modification and execution of the simulation file.

Further, the simulation file is a batch process and execution file automatically generated when the EDA simulation tool executes the simulation. It is used to describe the name, path, simulation library and simulation settings of the simulation project to be simulated. By modifying the content of the simulation file, the to-be-simulated project can be modified. The simulation object can also control the interface display, simulation duration, waveform signal and other settings of the EDA simulation tool.

Preferably, the EDA simulation script calls the TCL command through Python to directly generate all simulation files required for simulation without running the simulation and without opening the EDA simulation tool GUI. Modify the content of the simulation file through Python's file editing function. If someone is on duty during the simulation, modify the content of the simulation file to a non-command line for continuous execution and do not exit the simulation after the execution is completed. The simulation interface can be displayed during the simulation and after the simulation is completed. Do not exit; if the simulation is unattended, modify the content of the simulation file to continuously execute the command line and exit the simulation after execution, so that the simulation interface will not be displayed during the simulation and the simulation will exit after completion. Execute the simulation file through Python's command line function to realize automatic running of the simulation.

Further, in step 4, Testbench is a virtual test platform in the EDA simulation tool. Testbench contains three parts, namely the reading of verification incentives, the configuration of the Verilog code module interface and control signals to be verified, and the behavioral simulation results. File writing.

Further, in step 5, first run the Matlab simulation script, and the script will automatically generate the expected simulation results and write them into a txt file; secondly, run the EDA simulation script, and the script will automatically generate the behavioral simulation results and write them into the txt file.

Further, in step 6, the expected simulation results and behavioral simulation results are respectively read from the txt file, and the expected simulation results are used as a benchmark to verify the correctness of the behavioral simulation results.

A second aspect of the present invention discloses a Verilog code function verification platform, which is implemented based on the Verilog code function verification method. A functional verification platform for Verilog code includes a front-end layer, a service layer and a data layer.

Further, the front-end layer includes a parameter configuration module, a verification mode selection module, a verification incentive configuration module and a verification result display module. Used to provide developers with display and interactive functions. The front-end layer performs data processing and logical analysis on input information such as parameters, modes, and incentive configurations input by developers, and obtains parameter configuration signals, verification mode control signals, and verification incentives, and sends them to the service layer. At the same time, the verification results uploaded by the data layer are received and displayed on the front end.

Further, the service layer includes a Matlab simulation module and an EDA simulation module. It is used to receive control signals such as parameter configuration signals, verification mode control signals, and verification excitations issued by the front-end layer, and complete Matlab and EDA simulations based on the received control signals to obtain expected simulation results and behavioral simulation results. Finally, the control signals, The expected simulation results and behavioral simulation results are sent to the data layer together.

Further, the data layer includes a verification module, a log printing module and a storage module. It is used to receive the control signals, expected simulation results and behavioral simulation results issued by the service layer, and perform functional verification based on the expected simulation results and behavioral simulation results. If the function verification is correct, the verification result will be uploaded to the front-end layer; if the function verification is incorrect, the verification result will be uploaded to the front-end layer and at the same time, log printing and data storage will be performed based on the control signal.

Further, the parameter configuration module is used to receive parameter configuration information, uniformly convert different types of parameters such as real numbers and paths into character-type parameter configuration signals, and finally send the parameter configuration signals to the EDA simulation module and log printing module. .

Further, the parameter configuration information is the developer's configuration information for parameters such as Testbench file name, Verilog code file path to be verified, and file storage path.

Further, the verification mode selection module is used to receive the verification mode configuration information and perform logical analysis, and output the verification mode control signal to the Matlab simulation module, EDA simulation module and log printing module.

Further, the verification mode configuration information is the developer's configuration information of the verification mode and number of verifications based on simulation purposes and needs. Among them, the verification mode includes three verification modes: automatic verification, code debugging and simulation file generation. The difference between the three verification modes is: 1. The automatic verification mode is an unattended verification mode. The developer does not check the verification results in real time, but only checks the historical verification records after all verifications are completed. All verifications in this mode are run through the command line. , the EDA simulation tool interface is not displayed; 2. The code debugging mode is the attended verification mode. Developers need to check the results of each verification in real time to check the functional correctness of the current Verilog code. The verification in this mode is in the EDA simulation tool During the process, the EDA simulation tool interface for each verification is displayed in real time; 3. The simulation file generation mode is to only generate simulation files without modifying and executing the simulation files. It is used to generate after the project to be verified or the Verilog code changes. Simulation files for new projects or code.

Further, the logic analysis is to set the mode control word and perform a 1:1 mapping with the verification mode. The mapping relationship is: automatic verification-0, code debugging-1, and simulation file generation-2. The mode control word and the number of verifications are collectively referred to as verification mode control signals.

Further, the verification incentive configuration module is used to receive incentive configuration information, generate verification incentives and output them to the Matlab simulation module, EDA simulation module and storage module.

Further, the incentive configuration information is the configuration information of the developers to verify the name, quantity, length, randomness, limit and other parameters of the incentives based on the purpose and needs of the simulation.

Further, the verification result display module is used to receive the verification results and perform front-end display. The verification result display module receives the verification results output by the verification module, and displays the current number of verifications, the cumulative number of errors, and the results of this verification in the front-end GUI.

Further, the Matlab simulation module is used to receive the verification mode control signal and verification excitation, analyze the simulation control word, execute the Matlab simulation script to generate expected simulation results, and output the expected simulation results to the verification module and log printing module.

Preferably, the Matlab simulation module embeds the Matlab simulation script described in step 2 to analyze the mode control word in the input verification mode control signal. If the mode control word is 0 or 1, execute the script content and output the expected simulation. Result: If the mode control word is 2, this Matlab simulation will be skipped.

Further, the EDA simulation module is used to receive parameter configuration signals, verification mode control signals and verification incentives, analyze the simulation control words, execute the EDA simulation script to generate behavioral simulation results, and output the behavioral simulation results to the verification module and log. Print module.

Preferably, the EDA simulation module embeds the EDA simulation script described in step 3 to analyze the mode control word in the input verification mode control signal. If the mode control word is 0 or 1 and the current verification is the first time, then Completely execute the script content and output the behavioral simulation results; if the mode control word is 0 or 1, but it is not the first verification, only the modification and running part of the simulation file of the script will be executed, and the behavioral simulation results will be output, and the simulation file will be skipped. Generate to improve verification speed; if the mode control word is 2, only the simulation file generation part of the script will be executed.

Further, the verification module is used to receive expected simulation results and behavioral simulation results. Use the expected simulation results as the benchmark to verify the correctness of the behavioral simulation results, and output the verification results to the verification result display module and storage module. The verification module compares and analyzes the behavioral simulation results with the benchmark. If the two are consistent, the verification flag signal is set to 1, the current number of verifications is increased by 1, and the cumulative number of errors remains unchanged; if the two are inconsistent, the verification flag signal is set to 0, and the current number of verifications remains unchanged. The number of times increases by 1, and the accumulated number of errors increases by 1. The verification flag signal, the current number of verifications, and the cumulative number of errors are output together as the verification results.

Further, the log printing module is used to receive parameter configuration signals, verification mode control signals, expected simulation results and behavioral simulation results, and complete log printing. The log printing module prints the input information for each verification to a txt file and stores it in a preset path.

Further, the storage module is used to receive verification incentives and verification results, and store verification incentives based on the verification results. The storage module analyzes each verification result. If the verification result is correct, the verification incentive will not be processed in any way; if the verification result is incorrect, the verification incentive will be stored in a txt file so that developers can reproduce the problem.

Beneficial technical effects of the present invention: On the one hand, the present invention uses software and languages such as Matlab and Python to write simulation scripts. By directly generating, modifying and running simulation files, it can achieve verification such as incentive generation, simulation execution and result verification. The automatic execution of the process avoids repetitive interactions and operations between developers and the EDA simulation tool GUI, greatly improving verification efficiency; on the other hand, the present invention builds a verification platform based on the front-end layer, service layer and data layer. Provides a front-end GUI interface that enables flexible configuration of parameters and incentive information and real-time display of verification results, greatly improving the visibility of verification and the convenience and flexibility of incentive control. The platform also provides three different verification modes, which can dynamically adjust the generation and content modification of simulation files to control the parameter settings of EDA simulation tools to meet different verifications such as single verification in manned scenarios or continuous verification in unmanned scenarios. If required, the platform can also automatically determine verification results and store logs and abnormal data incentives so that developers can reproduce abnormal data and troubleshoot problems. The automation level of verification is further improved.

Description of drawings

Figure 1 is a flow chart of a functional verification method of Verilog code.

Figure 2 is a structural block diagram of a functional verification platform for Verilog code.

Implementation

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and do not limit the present invention.

The embodiment of the present invention provides a method for functional verification of Verilog code, as shown in Figure 1, including:

Step 1: Verify incentive generation. Reasonably set parameters such as the name, quantity, length, randomness, and limit of the verification incentives to generate verification incentives that meet the verification purpose and scenario requirements.

Step 2: Matlab simulation script writing. Write a Matlab simulation script through the software Matlab to achieve reading verification incentives, generate expected simulation results that are consistent with the expected functions of the Verilog code, and write the expected simulation results into a txt file.

Step 3: EDA simulation script writing. Use Python language to write EDA simulation scripts with the help of Python language's rich file processing function library and TCL commands. To achieve the following functions: 1. Directly generate all simulation files required for simulation without running simulation and without opening the EDA simulation tool GUI interface; 2. Modify the content of the simulation file to control the name and path of the project to be verified, and The interface display, simulation duration, waveform signal and other parameters of the EDA simulation tool; 3. Execute the simulation file to realize automatic execution of the simulation.

Step 4: Testbench writing. Write Testbench in the EDA simulation tool and place Testbench on top of the project to be verified. The implementation configures interfaces and control signals for the Verilog code module to be verified, provides verification incentives, and outputs behavioral simulation results of the Verilog code.

Step 5: Run Matlab and EDA simulation scripts. Run the Matlab simulation script and EDA simulation script respectively, and the script will write the expected simulation results and behavioral simulation results into txt files respectively.

Step 6: Verification of functional correctness. Read the expected simulation results and behavioral simulation results from the txt file respectively, and use the expected simulation results as the benchmark to compare the differences between the two. If the behavioral simulation results are consistent with the benchmark, the Verilog code functions normally; if the behavioral simulation results are inconsistent with the benchmark, Then the Verilog code functions abnormally.

This embodiment also provides a Verilog code function verification platform, which is implemented based on the above-mentioned Verilog code function verification method. As shown in Figure 2, it includes: a front-end layer, a service layer and a data layer.

The front-end layer includes a parameter configuration module, a verification mode selection module, a verification incentive configuration module and a verification result display module. Provide display and interactive functions for developers, perform data processing and logical analysis on parameters, modes, incentive configuration and other information input by developers, obtain parameter configuration signals, verification mode control signals and verification incentives, and send them to the service layer. At the same time, the verification results uploaded by the data layer are received and displayed on the front end.

The service layer includes a Matlab simulation module and an EDA simulation module. It is used to receive control signals such as parameter configuration signals, verification mode control signals, and verification excitations issued by the front-end layer, and complete Matlab and EDA simulations based on the received control signals to obtain expected results and simulation results. Finally, the control signals and expected results are and simulation results are sent to the data layer together.

The data layer includes a verification module, a log printing module and a storage module. It is used to receive the control signals, expected simulation results and behavioral simulation results issued by the service layer, and perform functional verification based on the expected simulation results and behavioral simulation results. If the function verification is correct, the verification result will be uploaded to the front-end layer; if the function verification is incorrect, the verification result will be uploaded to the front-end layer, and log printing and data storage will be performed according to the control signal.

Further, the parameter configuration module is used to receive configuration information such as Testbench file name, Verilog code file path to be verified, and file storage path input by the developer, and convert it into a character-type parameter configuration signal.

Further, the verification mode selection module is used to receive the verification mode and verification times input by the developer, and set the mode control word and the verification mode for 1:1 mapping. The mapping relationship is: automatic verification-0, code debugging-1 , Simulation file generation-2.

Further, the verification incentive configuration module is used to receive the verification incentive name, quantity, length, randomness, limit and other configuration information input by the developer, and generate the corresponding verification incentive.

Further, the verification result display module is used to receive the verification results and perform front-end display.

Further, the Matlab simulation module is embedded with the Matlab simulation script described in step 2 to receive the verification mode control signal and verification stimulus. If the mode control word is 0 or 1, the script content is executed; if the mode control word is 2 , then skip this Matlab simulation.

Further, the EDA simulation module is embedded with the EDA simulation script described in step 3 to receive parameter configuration signals, verification mode control signals and verification excitations. If the mode control word is 0 or 1, and it is currently the first time Verify, then execute the script content completely; if the mode control word is 0 or 1, but it is not the first verification, only the modification and running part of the simulation file of the script will be executed, and the simulation file generation will be skipped; if the mode control word is 2, Then only the simulation file generation part of the script is executed.

Further, the verification module is used to receive expected simulation results and behavioral simulation results, and use the expected simulation results as a benchmark. If the behavioral simulation results are consistent with the benchmark, the verification flag signal is set to 1, the current number of verifications is increased by 1, and the accumulated errors The number of times remains unchanged; if the behavioral simulation results are inconsistent with the benchmark, the verification flag signal is set to 0, the current number of verifications is increased by 1, and the cumulative number of errors is increased by 1.

Further, the log printing module is used to receive parameter configuration signals, verification mode control signals, expected results and simulation results, write the input information of each verification into a txt file and store it in a preset path.

Further, the storage module is used to receive verification incentives and verification results. If the verification results are correct, no processing will be done to the verification incentives; if the verification results are incorrect, the verification incentives will be written into a txt file and stored in a preset path. .

The above embodiments are illustrative of specific implementations of the present invention, rather than limitations of the present invention. Those skilled in the relevant technical fields can also make various transformations and changes without departing from the spirit and scope of the present invention. Corresponding equivalent technical solutions, therefore all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims (7)

1. A method for functional verification of Verilog code, which is characterized by including the following steps: Step 1: In order to meet the verification purpose and needs, configure the name, quantity, length, randomness, limit and other parameters of the verification incentives, and generate the corresponding verification incentives; Step 2: Matlab simulation script writing, use the software Matlab to write the simulation script to implement the expected functions of the Verilog code to be verified and obtain the expected simulation results; Step 3: EDA simulation script writing, use Python language to write EDA simulation script to complete the generation, modification and execution of simulation files; Step 4: Testbench writing. Write Testbench in the EDA simulation tool to configure the interface and control signals of the Verilog code module to be verified, and complete the input of verification incentives and the output of behavioral simulation results; Step 5: Run the Matlab simulation script and EDA simulation script. Run the Matlab and EDA simulation scripts respectively, and obtain the expected simulation results and behavioral simulation results; Step 6: Functional correctness verification, compare the expected simulation results with the behavioral simulation results, and verify the functional correctness of the Verilog code. 2. A function verification method of Verilog code according to claim 1, the EDA simulation script function in step 3 includes the generation of simulation files, the modification of simulation files and the execution of simulation files, wherein: Generation of simulation files: Use the Python program to call TCL commands and call the EDA simulation tool through the command line to complete the generation of simulation files without opening the EDA simulation tool interface; Modification of simulation files: Based on actual verification requirements, edit the content of relevant simulation files through Python programs to control the interface display, simulation duration, waveform signal and other settings of the EDA simulation tool; Execution of simulation files: Execute relevant simulation files sequentially through the Python program. 3. A method for functional verification of Verilog code according to claim 1, in the step 4, Testbench includes the input of verification incentives, the configuration of the Verilog code module interface and control signal to be verified, and the output of behavioral simulation results, wherein: Input of verification stimulus: read the verification stimulus described in claim 1, and input the Verilog code module to be verified; Configuration of the interface and control signals of the Verilog code module to be verified: Configure the interface name, data type, bit width and symbol information of the Verilog code module to be verified, as well as the frequency and delay of the clock, reset and enable signals; Output of behavioral simulation results: Write the behavioral simulation results of the Verilog code module into a txt file and save it to the preset path. 4. A functional verification platform for Verilog code, characterized in that, based on the functional verification method of Verilog code according to any one of claims 1 to 3 in the functional verification method of Verilog code of claim 1, it includes a front end layer, service layer and data layer, among which: Front-end layer: including parameter configuration module, verification mode selection module, verification incentive configuration module, and verification result display module, which is used to provide developers with interactive windows for parameters, modes, and incentive configurations, as well as a display window for displaying verification results, and for input Perform data processing and logical analysis of information; Service layer: including Matlab simulation module and EDA simulation module, which are used to complete the execution of simulation business and provide a calling interface for the front-end layer; Data layer: includes verification module, log printing module, and storage module, which are used to complete the processing and storage of input data and verification results. 5. A functional verification platform for Verilog code according to claim 4, the verification mode selection module provides three verification modes: automatic verification, code debugging and simulation file generation, wherein: Automatic verification: It is an unattended verification mode. The developer does not check the verification results in real time, but only checks the historical verification records after all verifications are completed. All verifications in this mode are run through the command line, and the EDA simulation tool interface is not displayed; Code debugging: It is an attended verification mode. Developers need to check the results of each verification in real time to check the functional correctness of the current Verilog code. Verification in this mode is performed in the EDA simulation tool, and the EDA of each verification is displayed in real time. Simulation tool interface; Simulation file generation: only generates simulation files without modification and execution of simulation files. It is used to generate simulation files for new projects or codes after the project to be verified or the Verilog code changes. 6. A Verilog code function verification platform according to claim 4, the Matlab simulation module is embedded in the Matlab simulation script in step 2 of the Verilog code function verification method of claim 1, and whether to select according to the verification mode Execute the script. If the verification mode is automatic verification or code debugging, the Matlab simulation script will be executed; if the verification mode is simulation file generation, the Matlab simulation script will not be executed. 7. A Verilog code function verification platform according to claim 4, the EDA simulation module is embedded in the EDA simulation script in step 3 of the Verilog code function verification method of claim 1, according to the verification mode and verification Number of times to selectively execute the script content. If the verification mode is automatic verification or code debugging, and it is currently the first verification, the script content will be executed completely; if the verification mode is automatic verification or code debugging, but it is not the first verification, Then only the modification and running part of the simulation file of the script will be executed; if the verification mode is simulation file generation, only the simulation file generation part of the script will be executed.