CN102156628B - Microprocessor, method of prefetching data to the cache memory hierarchy of the microprocessor - Google Patents

Abstract

A microprocessor and method of prefetching data into a cache memory hierarchy of the microprocessor, the microprocessor comprising: the first cache memory and the second cache memory belong to different levels, and the level of the second cache memory is lower than that of the first cache memory; the data prefetcher monitors the loading operation, records the loading operation of the current cache line as a recent history, judges whether the recent history shows that a definite direction exists, and prefetches one or more cache lines to the first cache memory if the recent history shows that the definite direction exists, otherwise, prefetches one or more cache lines to the second cache memory. The data cache also determines whether the recent history indicates that the load operation is a large data volume. Under other conditions, the condition of large data volume is enabled to prefetch a larger number of cache lines. The data cache also determines whether the recent history indicates that the load operation occurred in consecutive clock cycles. The present invention can provide additional prefetching modes.

Description

Microprocessor, method of prefetching data to the cache memory hierarchy of the microprocessor

technical field

The present invention relates to the field of microprocessors, and in particular to data prefetching techniques for microprocessors.

Background technique

The Intel Core microprocessor architecture (microarchitecture) implements a hardware prefetcher (hardware prefetcher, related to the data cache unit prefetcher/DataCache Unit Prefetcher), which is used to prefetch the first layer data cache memory (L1Dcache). By identifying a pattern of contents of a cache line, the data cache unit prefetcher prefetches a subsequent next cache line into the first level data cache memory. If each successive load corresponds to a lower address than each previous address, the previously mentioned successive cache lines are prefetched.

Contents of the invention

One embodiment of the present invention provides a microprocessor. The microprocessor includes a first and a second cache memory belonging to different levels of a cache memory hierarchy of the microprocessor, wherein the second cache memory is at a lower level of the cache memory hierarchy than the First cache memory. The microprocessor also includes a load unit for receiving a load operation related to a memory. The microprocessor includes a data prefetcher coupled to the first and second cache memories. The data prefetcher is used to monitor the above load operations, and record the load operations on the current cache line as a recent history. The data prefetcher is also used to determine whether the recent history shows that the current cache line load operation has a clear direction. If the recent history shows that the above-mentioned clear direction exists, the data prefetcher prefetches one or more cache columns into the first cache memory. If the recent history shows that there is no such clear direction, the data prefetcher prefetches one or more cache columns into the second cache memory.

Another embodiment of the present invention discloses a method for prefetching data into a cache memory hierarchy of a microprocessor, wherein the cache memory hierarchy includes a first cache memory and a second cache memory, The above-mentioned first and second cache memories belong to different levels of the cache hierarchy, and the level of the second cache memory is lower than that of the first cache memory. The method includes monitoring load operations on a memory received by a load unit of the microprocessor, and recording the load operations on the current cache line as a recent history. The method further includes judging whether the recent history shows that there is a clear direction for the loading operation of the current cache row. When the recent history shows a clear direction, the disclosed method includes prefetching one or more cache lines into the first cache memory. When the recent history does not show a clear direction, the disclosed method includes prefetching one or more cache lines into the second cache memory.

Compared with the prior art, the present invention can provide additional prefetching modes.

Description of drawings

FIG. 1 is a block diagram illustrating a microprocessor disclosed in the present invention, which has a data prefetcher;

Figure 2 is a flowchart describing the operation of the microprocessor of Figure 1;

FIG. 3 is a block diagram illustrating another microprocessor disclosed by the present invention, which has a data prefetcher;

FIG. 4 is a flowchart describing how the data prefetcher in the embodiment of FIG. 3 implements the operation of step 204 in FIG. 2 .

A brief description of the symbols in the drawings is as follows:

100: microprocessor; 102: instruction cache memory;

112: instruction translator; 116: register alias table;

118: reservation station; 122: loading unit;

126: bus interface unit; 132: first layer data cache memory;

134: second layer cache memory;

136: Data prefetcher; 142: History queue;

144: Historical record details; 146: Control logic;

148: clock counter; 152: address field;

154: size field; 156: continuity field;

158: direction field; 162: cache column counter;

164: latest previous clock;

304: lowest pointer; 306: highest pointer;

308: lowest pointer change counter; 312: highest pointer change counter.

Detailed ways

The present invention describes a data prefetcher. Compared with Intel's data cache unit prefetcher, the data prefetcher disclosed in the present invention also provides additional prefetching modes. First, the disclosed data prefetcher will consider whether there is a clear load direction; if it is uncertain that there is a clear load direction, the data will be prefetched to the second level cache memory ( L2) instead of Level 1 Data Cache (L1D). Second, the disclosed data prefetcher will determine the time interval between loads of the same cache line. If the interval is short (eg, occurs in consecutive clock cycles), the data prefetcher will prefetch a larger number of cache rows (compared to other cases). Third, the disclosed data prefetcher observes the amount of data loaded. If the amount of data is quite large, the data prefetcher will prefetch a larger number of cache columns (compared to other situations).

Referring to FIG. 1 , it provides a block diagram illustrating a microprocessor 100 disclosed according to an embodiment of the present invention. The microprocessor 100 has a data prefetcher 136 therein. The microprocessor 100 includes an instruction cache (instruction cache) 102; the instruction cache 102 is coupled to an instruction translator (instruction translator) 112; the instruction translator 112 is coupled to a register alias table (registeralias table , RAT) 116; the register alias table 116 is coupled to a reservation station (reservation stations) 118; and the reservation station 118 is coupled to a load unit (load unit) 122. The reservation station 118 issues instructions to the load unit 122 (or to other execution units, not shown in the figure) for execution out of program sequence. A retirement unit (not shown in the figure) includes a recorder buffer for retiring instructions according to program order. The loading unit 122 reads data from a first level data cache (L1D cache) 132 . A level 2 cache (L2 cache) supports the level 1 data cache 132 and the instruction cache 102 . The second layer cache memory 134 reads and writes the system memory (systemmemory) through a bus interface unit (bus interface unit) 126; Or memory bus memory bus) interface. The microprocessor 100 also includes a data prefetcher 136, or a prefetch unit prefetch unit, for prefetching data from the system memory to the second level cache memory 134 and the first level data cache memory 132, which will be discussed in detail below its content.

Data prefetcher 136 includes a control logic 146 . The control logic 146 is coupled to and controls a history queue (history queue) 142, a cache line counter (cache line counter) 162, a clock cycle counter (clock cycle counter) 148 and a latest previous clock register (most recent previous) clock cycle register) 164. The history queue 142 records the history record entries 144 in a queue. Each historical record item 144 includes an address field (an address field) 152, a size field (a size field) 154, a continuous field (a consecutive filed) 156, and a direction field (a direction field) 158. The address column 152 stores the load address (load address) of the load operation (load operation) recorded in the corresponding history record item 144 . The size field 154 stores the size (number of bytes) of the load operation. The continuity field 156 indicates whether the load operation received by the data prefetcher 136 is within consecutive clock cycles from the most recent previous load operation. Direction field 158 displays the direction of the load operation relative to the most recent previous load operation.

Since the data prefetcher 136 starts to track the current cache line accesses, the cache line counter 162 counts the total number of load operations of the cache line, which will be discussed corresponding to step 204 in FIG. 2 . The clock counter 148 increments with the microprocessor 100 clock. Thus, while a load operation is being processed in step 204, the result of the control logic 146 sampling the clock counter 148 can be used to indicate at which time the new load operation is relative to other load operations at the moment. The clock cycle is received, and is particularly used to determine whether the load operation is received in consecutive clock cycles after the previous load operation was received, so as to set the continuity field 156 in the history entry 144 . The functions of the clock counter 148 and the latest previous clock register 164 are further discussed below in FIG. 2 .

Referring to FIG. 2 , a flow chart is used to describe the operation of the microprocessor 100 of FIG. 1 . The process starts at step 202 .

At step 202 , a new load operation is passed from the load unit 122 to the level 1 data cache 132 . The load operation clearly indicates a load address to indicate the address of the data to be loaded in the memory. In addition, the load operation also clearly indicates the size of the data to be loaded, for example, 1, 2, 4 , 8 or 16 bytes. The flowchart then goes to step 204 .

In step 204 , the data prefetcher 136 peeks at the first level data cache memory 132 to detect the new load operation and its related information. According to the detection result, the data prefetcher 136 configures and fills a history entry 144 in the history queue 142 . In particular, the control logic 146 fills the address field 152 with the load address and fills the size field 154 with the size of the loaded data. In addition, the control logic 146 reads and compares the values of the clock counter 148 and the latest previous clock register 164 . If the current value of the clock counter 148 is 1 more than the value of the latest previous clock register 164, the control logic 146 will set the continuity field 156 to indicate that this new load operation is the continuous time of the previous load operation. Otherwise, the control logic 146 clears the content of the continuity field 156 to indicate that the new load operation does not occur within the continuous clock cycle of the previous load operation. In another embodiment, the control logic 146 sets the continuity field 156 to indicate that the load operation is a continuous clock when the current value of the clock counter 148 is N more than the value of the latest previous clock register 164 Occurs within a period, where N is a default value; otherwise, the control logic 146 clears the continuity field 156 . In one embodiment, the value of N is two. However, the default value N is a design parameter and can be set based on various parameters, such as the size of the first-level data cache memory 132 and/or the second-level cache memory 134 . In one implementation, the preset value N can be set via a model specified register (MSR) of the microprocessor 100 . After reading the content of the latest previous clock register 164 , the control logic 146 uses the value it read from the clock counter 148 to update the content of the latest previous clock register 164 . In addition, the control logic 146 will compare the load address of this new load operation with the address column 152 of the latest previous load operation recorded in the history queue 142, and fill in the address of the new load operation accordingly. Direction field 158 to indicate the direction of this new loading operation relative to the latest previous loading operation. In addition, the control logic can mark the history record item 144 as valid by setting a valid bit in the history record item 144 . In addition, the control logic 146 also increments the cache rank counter 162 . In addition, before configuring, filling and validating the configured history record item 144 and incrementing the cache column counter 162, the control logic 146 will determine whether the location of the load address of this new load operation is consistent with the history queue Other load operations in 142 are located in the same cache row; if not, then control logic 146 invalidates all historical record entries 144 in the history queue 142 to start a new cache for this new load operation. The column is recorded, and the value of the cache column counter 162 is cleared. The process in FIG. 2 enters the next step 206 .

In step 206, the data prefetcher 136 identifies a load access pattern in the cache line involved in the new load operation. In one embodiment, the prefetcher 136 identifies a load access pattern in the current cache line when the cache line counter 162 (incremented in step 204 ) is greater than or equal to a predetermined value P. In one embodiment, the P value is 4. However, the default value P is a design parameter and can be determined based on various factors, for example, the size of the first-level data cache memory 132 and/or the second-level cache memory 134 . In one embodiment, the preset value P can be set by using a model specified register (MSR) of the microprocessor. In addition, a load access pattern in the current cache line can also be detected in other ways. The process in FIG. 2 then goes to step 208 .

In step 208, the data prefetcher 136 determines whether the load access pattern has a clear direction. In one embodiment, if the direction field 158 of the history item 144 of the latest at least D load operations shows the same direction, the data prefetcher 136 will determine that there is a clear direction, where D is the default value. In one embodiment, the preset value D is 3. However, the preset value D is a design parameter and can be adjusted based on various factors, such as the size of the first-level data cache memory 132 and/or the second-level cache memory 134 . In one embodiment, the preset value D can be set by using a model-specific register (MSR) of the microprocessor 100 . Another possible implementation will be discussed below in FIG. 3 , where another way is used to determine whether a clear direction exists. If the data prefetcher 136 determines that there is a definite direction, the flow chart of FIG. 2 enters into a decision step 218 ; otherwise, it enters into another decision step 212 .

In the judging step 212 , the data prefetcher 136 judges whether the data volume of the load operation of the current cache line is too large. In one embodiment, if the statistical result of the size column 154 of the valid historical record item 144 shows that the relevant load operations have at least a data volume Y in total, the data prefetcher 136 will determine that the load operation is A large amount of data, where Y is the default value. In one embodiment, the preset value Y is 8 bytes. However, the default value Y is a design parameter, which can be determined based on various factors, such as the size of the first-level data cache memory 132 and/or the second-level cache memory 134 . In one embodiment, the preset value Y can be set by using a model-specific register (MSR) of the microprocessor 100 . In another implementation manner, the data prefetcher 136 can determine that the load operation is a large data volume when most of the load operations have at least a data volume Y; The number of data loading operations and the number of non-large data loading operations, and comparing them; can be performed in step 204 . If the loading operation is a large amount of data, the process in FIG. 2 goes to step 214 ; otherwise, the process in FIG. 2 goes to step 216 .

In step 214 , the data prefetcher 136 prefetches the next two cache columns to the second-level cache memory 134 . Since there is no clear direction in the judgment step 208, the data prefetcher 136 prefetches data to the second level cache memory 134 rather than the first level data cache memory 132; the reason is that the prefetched data has a greater chance to be It is not necessary, therefore, the data prefetcher 136 does not tend to place potentially useful data in the first level data cache memory 132 . The process in FIG. 2 ends at step 214 .

In step 216 , the data prefetcher 136 only prefetches a subsequent cache row to the second-level cache memory 134 . The process in FIG. 2 ends at step 216 .

In decision step 218, the data prefetcher 136 determines whether the load operation associated with the current cache line is received in consecutive clock cycles. If the load is received in consecutive clock cycles, it means that the program is scanning the memory very fast, so the data prefetcher 136 must prefetch more data to get ahead of the program, e.g. Before the request, the data of the subsequent cache column is pre-prepared in the first-level data cache memory 132 . In one embodiment, if the continuity field 156 of the history entry 144 of the latest at least C load operations for the current cache line is marked, the data prefetcher 136 will know that the load The input operation is received in continuous clock cycles, where C is a preset value. In one embodiment, the default value C is 3, however, the default value C is a design parameter, which may be based on various factors, such as the first-level data cache memory 132 and/or the second-level cache memory 134 The size is decided. In one embodiment, the preset value C can be set by a model specific register (MSR) of the microprocessor 100 . If the loading occurs in consecutive clock cycles, the process in FIG. 2 enters the decision step 232 ; otherwise, the process enters the decision step 222 .

In the judging step 222 , the data prefetcher 136 judges whether the load operation on the current cache line is a large amount of data; the detailed technique is similar to the above judging step 212 . If the amount of data is large, the process in FIG. 2 enters step 224; otherwise, the process enters step 226.

In step 224 , the data prefetcher 136 prefetches two consecutive cache columns to the first-level data cache memory 132 following the specific direction determined in step 208 . Since the decision step 208 determines that there is a definite direction, the data prefetcher 136 will prefetch data to the first level data cache memory 132 rather than the second level cache memory 134; the reason is that the prefetched data is very likely to be If used, the prefetcher 136 tends to place potentially useful data in the first-level data cache memory 132 . The process in FIG. 2 ends at step 224 .

In step 226 , the data prefetcher 136 prefetches a subsequent cache column to the first-level data cache memory 132 according to the specific direction determined in step 208 . The process in FIG. 2 ends at step 226 .

In the judging step 232 , the data prefetcher 136 judges whether the loading operation of the current cache row is a large amount of data; the detailed content is similar to that of the aforementioned judging step 212 . If the amount of data loaded is large, the process in FIG. 2 enters step 234 ; otherwise, the process in FIG. 2 enters step 236 .

In step 234 , the data prefetcher 136 prefetches three consecutive cache columns to the first-level data cache memory 132 according to the specific direction determined in step 208 . The process in FIG. 2 ends at step 234 .

In step 236 , the data prefetcher 136 prefetches two consecutive cache columns to the first-level data cache memory 132 according to the specific direction determined in step 208 . The process in FIG. 2 ends at step 236 .

Next, the technique of FIG. 3 is discussed, which uses a block diagram to describe a microprocessor 100 implemented by another embodiment of the present invention, and the microprocessor 100 has a data prefetcher 136 . The data prefetcher 136 of FIG. 3 is similar to the data prefetcher 136 introduced in FIG. 1 , and also operates in a manner similar to that of FIG. 2 . The differences between the two implementations are discussed below. With regard to the historical record update made in step 204 in FIG. 2 and the definite direction decision made in decision step 208, the data prefetcher 136 in FIG. 3 makes the following adjustments. In the embodiment of FIG. 3 , the history item 144 of the history queue 142 does not include the directionality field 158 . In addition, the data prefetcher 136 includes a lowest pointer register (min pointer register) 304 and a highest pointer register (max pointer register) 306, which are controlled by the control logic 146 and point to the self-data prefetch in the current cache row respectively. The register 136 starts tracking the lowest and highest address variables that have occurred since the fetch of the current cache line. The data prefetcher 136 also includes a lowest pointer change counter 308 and a highest pointer change counter 312, which are used to count the lowest pointer registers 304 and the lowest pointer registers 304 and The change times of the highest pointer register 306. The following discusses how to implement the operation of the data prefetcher 136 described in step 204 in FIG. 2 with the embodiment disclosed in FIG. 3 . By determining whether the difference between the lowest pointer change counter 308 and the highest pointer change counter 312 is greater than a predetermined value, the control logic 146 determines whether there is a definite direction. In one embodiment, the default value is 1; however, the default value is a design parameter, which may be based on various variables, such as the first level data cache memory 132 and/or the second level cache memory 134 The size is decided. In one embodiment, the preset value can be set by using a model specific register (MSR) of the microprocessor 100 . If the value of the lowest pointer change counter 308 is higher than the above-mentioned preset value than the value of the highest pointer change counter 312, then the definite direction determined is downward; if the value of the highest pointer change counter 312 is higher than the lowest pointer change If the value of the counter 308 is higher than the above preset value, then it is determined that the definite direction is upward; in other cases, it is determined that there is no definite direction. In addition, if the load address of this new load operation does not point to the same cache line as other load operations recorded in the history queue 142 , the control logic 146 clears the highest pointer change counter 312 and the lowest change pointer counter 308 .

Referring now to FIG. 4 , a flow chart is used to describe how the data prefetcher 136 in the embodiment of FIG. 3 implements the actions of step 204 in FIG. 2 . The process in FIG. 4 starts from step 404 .

In the determination step 404 , the control logic 146 determines whether the new load address, especially the latest load address offset of the current cache row, is greater than the value of the highest pointer register 306 . If yes, the flow enters step 406; otherwise, the flow enters judgment step 408.

In step 406 , the control logic 146 updates the top pointer register 306 with the new load address offset and increments the top pointer change counter 312 . In this case, the flow of FIG. 4 ends at step 406 .

In the determination step 408 , the control logic 146 determines whether the latest load address offset of the current cache line is less than the value of the lowest pointer register 304 . If yes, the process in FIG. 4 enters step 412; if otherwise, the process in FIG. 4 ends.

In step 412 , the control logic 146 updates the lowest pointer register 304 with the latest load address offset and increments the lowest pointer change counter 308 . The process shown in FIG. 4 ends at step 412 .

Although the above embodiments mainly discuss the load operation, in other implementations, the disclosed prefetch technology can also be appropriately improved to apply to store operations.

Although various embodiments of the present invention have been described above, it must be declared that the above contents are some application examples of the present technology, and are not intended to limit the scope of the present invention. Those skilled in the art can follow the features of the present invention and develop many variants with the prior art. For example, the content disclosed in the present invention can be realized in the form of software, for example, the function, production, modeling, simulation, description and/or testing of the disclosed device or method. Above-mentioned software can adopt common programming language (for example, C, C++), hardware description language (hardware description language, HDL) comprises VerilogHDL, VHDL etc. or other available programming languages. The above-mentioned software can be carried on any existing computer storage medium, for example, magnetic recording device (magnetic tape), semiconductor (semiconductor), magnetic disk (magnetic disk) or optical disc (optical disc, such as CD-ROM, DVD-ROM, etc.), It can also be carried on the network, cable system or other communication media. The various devices and methods disclosed in the present invention can be implemented and protected by a semiconductor intellectual property core, such as a microprocessor core, by a hardware description language, and can be converted into hardware and manufactured in an integrated circuit. In addition, the disclosed devices and methods can also be implemented by co-designing hardware and software. Therefore, the present invention should not be limited by any of the above embodiments, but should be interpreted according to the scope defined by the claims. In particular, the present invention can be implemented in a microprocessor, implementing a commonly used computer. Those skilled in the present invention may design or adjust other structures on the basis of the present invention, on the basis of the disclosed concept and the described special implementation mode, so as to develop the same as the present invention without departing from the content defined in the claims. technology with the same purpose.

Claims (31)

1. a microprocessor, is characterized in that, comprising:

One first memory cache and one second memory cache, the different levels that belong to respectively a memory cache stratum of this microprocessor, wherein, the level in this second memory cache Gai memory cache stratum is lower than the level in this first memory cache Gai memory cache stratum;

One is written into unit, in order to receive the operation that is written into about a storer; And

One data pre-fetching device, couples above-mentioned the first memory cache and above-mentioned the second memory cache, in order to:

Monitor the above-mentioned operation that is written into, and record is about an above-mentioned recent history that is written into operation of current cache row;

Judge whether this recently historically shows that about current cache row above-mentioned, being written into operation has a specific direction; And

When the above-mentioned specific direction of this recent history display exists, one or more cache of looking ahead is listed as to this first memory cache; And do not show that in this recent history while having above-mentioned specific direction, one or more cache of looking ahead is listed as to this second memory cache.

2. microprocessor according to claim 1, is characterized in that, above-mentioned one or more cache that is taken in advance this first memory cache is classified as and followed continue one or more cache row of current cache row of this specific direction.

3. microprocessor according to claim 2, is characterized in that, above-mentioned one or more cache that is taken in advance this second memory cache is classified one or more cache row being connected in after current cache row as.

4. microprocessor according to claim 1, is characterized in that, if being at least written into for D time of occurring is recently operating as same direction, above-mentioned recent history display has above-mentioned specific direction to exist, and wherein D is greater than a default integer of 1.

5. microprocessor according to claim 4, is characterized in that, D is set by user.

6. microprocessor according to claim 1, it is characterized in that, this recent history comprises a lowest address deviator and the location deviator superlatively that is written into operation about current cache row above-mentioned, and the highest counting that comprises a lowest count of the change of counting above-mentioned lowest address deviator and count the change of above-mentioned superlatively location deviator, above-mentioned being written into that described lowest count and the highest described counting start to record current cache row from this data pre-fetching device is operating as above-mentioned recent historical beginning, wherein, when above-mentioned lowest count and above-mentioned when the gap of high counting is greater than a preset value, above-mentioned recent history display one specific direction exists.

7. microprocessor according to claim 6, is characterized in that, this preset value is set by user.

8. microprocessor according to claim 1, it is characterized in that, this data pre-fetching device is also for judging whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the constant situation of other conditions, if above-mentioned, be written into and be operating as big data quantity, the quantity of cache that this data pre-fetching device is looked ahead row is more than the quantity of the above-mentioned cache row that this data pre-fetching device is looked ahead while being written into operation for big data quantity

Wherein, if all above-mentioned data volumes that is written into operation are all at least Y byte, above-mentioned being written into of this recent history display is operating as big data quantity, and Y is a preset value.

9. microprocessor according to claim 8, is characterized in that, the parameter that this preset value Y sets for user.

10. microprocessor according to claim 8, it is characterized in that, when this recent history does not show this specific direction, if above-mentioned, be written into and be operating as big data quantity, this data pre-fetching device two caches that continue after current cache row of looking ahead are listed as to this second memory cache, if above-mentioned, be written into the non-big data quantity of operation, this data pre-fetching device cache continuing after current cache row of looking ahead is listed as to this second memory cache.

11. microprocessors according to claim 1, it is characterized in that, when this recent history display has above-mentioned specific direction, this data pre-fetching device also judges whether this recent history shows that above-mentioned being written into operates in interior being received of continuous clock pulse cycle, wherein, under the constant situation of other conditions, if above-mentioned, be written into operate in the continuous clock pulse cycle and be received, the quantity that is taken in advance the cache row of this first memory cache by this data pre-fetching device is written into operation and when continuous clock pulse is received in the cycle, by this data pre-fetching device, is not taken in advance the quantity of the cache row of this first memory cache more than above-mentioned.

12. microprocessors according to claim 11, it is characterized in that, if at present cache row up-to-date at least C time above-mentioned to be written into operation be to be received in the cycle in the front continuous clock pulse that is once written into operation, the current cache of this recent history display row all above-mentioned is written into that to operate in continuous clock pulse received in the cycle, wherein, C is greater than a default integer of 1.

13. microprocessors according to claim 12, is characterized in that, the parameter that this default integer C sets for user.

14. microprocessors according to claim 11, it is characterized in that, this data pre-fetching device is also for judging whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the constant situation of other conditions, if above-mentioned, be written into and be operating as big data quantity, be taken in advance the quantity of cache row of this first memory cache more than the above-mentioned quantity that is taken in advance the cache row of this first memory cache while being written into operation for big data quantity

Wherein, if all above-mentioned data volumes that is written into operation are all at least Y byte, above-mentioned being written into of this recent history display is operating as big data quantity, and Y is a preset value.

15. microprocessors according to claim 14, is characterized in that, also comprise:

When above-mentioned, be written into that to operate in continuous clock pulse received and during for big data quantity in the cycle, this data pre-fetching device is looked ahead and is followed continue three caches of current cache row of this specific direction to be listed as to this first memory cache; And

When above-mentioned being written into operates in continuous clock pulse in the cycle during received but non-big data quantity, this data pre-fetching device is looked ahead and is followed continue two caches of current cache row of this specific direction to be listed as to this first memory cache.

16. microprocessors according to claim 15, is characterized in that, also comprise:

To be written into operation not received but during for big data quantity in the cycle at clock pulse continuously when above-mentioned, and this data pre-fetching device is looked ahead and followed continue two caches of current cache row of this specific direction to be listed as to this first memory cache; And

When above-mentioned, be written into operation not at clock pulse continuously in the cycle during received and non-big data quantity, this data pre-fetching device is looked ahead and is followed a continue cache of current cache row of this specific direction to be listed as to this first memory cache.

17. microprocessors according to claim 1, it is characterized in that, the look ahead operation of above-mentioned one or more cache row of this data pre-fetching device inhibition itself, unless the above-mentioned quantity that is written into operation of the current cache row of this recent history display has at least P time, wherein P is preset value.

18. microprocessors according to claim 17, is characterized in that, the parameter that P sets for user.

19. 1 kinds of prefetch datas are to the method for the memory cache stratum of microprocessor, it is characterized in that, this memory cache stratum comprises one first memory cache and one second memory cache that belongs to different estate, wherein the level of this second memory cache Gai memory cache stratum is lower than the level of this first memory cache Gai memory cache stratum, and the method comprises:

Monitor one of this microprocessor and be written into the operation that is written into about a storer that unit receives, and above-mentioned being written into that record is listed as about current cache is operating as a recent history;

Judge this recently historical whether show current cache row above-mentioned be written into operation and there is a specific direction; And

When this recent history display has above-mentioned specific direction, one or more cache of looking ahead is listed as to this first memory cache, and when this recent history does not show above-mentioned specific direction, one or more cache of looking ahead is listed as to this second memory cache.

20. prefetch datas according to claim 19 are to the method for the memory cache stratum of microprocessor, it is characterized in that, above-mentioned one or more cache that is taken in advance this first memory cache is classified as and is followed continue one or more cache row of current cache row of this specific direction.

21. prefetch datas according to claim 20 are to the method for the memory cache stratum of microprocessor, it is characterized in that, above-mentioned one or more cache that is taken in advance this second memory cache is classified the one or more cache row that continue after current cache row as.

22. prefetch datas according to claim 19 are to the method for the memory cache stratum of microprocessor, it is characterized in that, if the most de novo, be at least written into for D time and be operating as same direction, the above-mentioned specific direction of this recent history display exists, wherein, D is greater than a default integer of 1.

23. prefetch datas according to claim 19 are to the method for the memory cache stratum of microprocessor, it is characterized in that, an above-mentioned lowest address deviator and that is written into operation that this recent history comprises current cache row is location deviator superlatively, and comprise a lowest count of the variation of counting this lowest address deviator and count this superlatively the highest counting of the variation of location deviator, described lowest count and the highest described counting list to state from current cache and are written into operation is recorded in this recent history, wherein, if described lowest count and the described difference of high counting are greater than a preset value, this recent history display has above-mentioned specific direction to exist.

24. prefetch datas according to claim 19 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

Judge whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the identical situation of other conditions, if above-mentioned, be written into and be operating as big data quantity, the quantity of the cache row of looking ahead is greater than the quantity that above-mentioned cache of looking ahead while being written into operation not for big data quantity is listed as

Wherein, if all above-mentioned data volumes that is written into operation are all at least Y byte, above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.

25. prefetch datas according to claim 24 are to the method for the memory cache stratum of microprocessor, it is characterized in that, if this recent history does not show above-mentioned specific direction, above-mentioned one or more cache of looking ahead is listed as and to the step of this second memory cache, is included in above-mentioned two caches that continue after current cache row of looking ahead while being operating as big data quantity that are written into and is listed as to this second memory cache, and the cache of current cache after being listed as that continue of looking ahead under other situations is listed as to this second memory cache.

26. prefetch datas according to claim 19 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

When this recent history display has above-mentioned specific direction, judge whether this recent history shows that above-mentioned to be written into operation be continuously clock pulse is received in the cycle, wherein, under the constant situation of other conditions, if above-mentioned, be written into that to operate in continuous clock pulse received in the cycle, the quantity that is taken in advance the cache row of this first memory cache is written into operation and when continuous clock pulse is received in the cycle, is not taken in advance the quantity of the cache row of this first memory cache more than above-mentioned.

27. prefetch datas according to claim 26 are to the method for the memory cache stratum of microprocessor, it is characterized in that, if at present cache row up-to-date at least C time above-mentioned to be written into operation be to be received in the cycle in the front continuous clock pulse that is once written into operation, the current cache of this recent history display row all above-mentioned is written into that to operate in continuous clock pulse received in the cycle, wherein, C is greater than a default integer of 1.

28. prefetch datas according to claim 26 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

Judge whether this recent history shows that above-mentioned being written into is operating as big data quantity, wherein, under the identical situation of other conditions, if above-mentioned, be written into and be operating as big data quantity, be taken in advance the quantity of cache row of this first memory cache more than the above-mentioned quantity that is taken in advance the cache row of this first memory cache while being written into operation for big data quantity

Wherein, if all above-mentioned data volumes that is written into operation are all at least Y byte, above-mentioned being written into of this recent history display is operating as big data quantity, and wherein Y is a preset value.

29. prefetch datas according to claim 28 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

In above-mentioned, be written into that to operate in continuous clock pulse received and during for big data quantity in the cycle, look ahead and follow continue three caches of current cache row of this specific direction to be listed as to this first memory cache;

In above-mentioned being written into, operate in continuous clock pulse in the cycle during received but non-big data quantity, look ahead and follow continue two caches of current cache row of this specific direction to be listed as to this first memory cache.

30. prefetch datas according to claim 29 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

To be written into operation non-received but during for big data quantity in the cycle in continuous clock pulse in above-mentioned, looks ahead and follow continue two caches of current cache row of this specific direction to be listed as to this first memory cache; And

To be written into operation non-in continuous clock pulse in the cycle during received and non-big data quantity in above-mentioned, looks ahead and follow a continue cache of current cache row of this specific direction to be listed as to this first memory cache.

31. prefetch datas according to claim 19 to the method for the memory cache stratum of microprocessor, is characterized in that, also comprise:

The step that suppresses the above-mentioned one or more cache row of looking ahead, unless the quantity that is written into operation of the current cache row of this recent history display is at least P time, wherein P is a preset value.

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